Task Synchronization Method, Medium and Device for Multi-Core System

Abstract

The present application provides a task synchronization method, medium and device for a multi-core system. The tasks of the multi-core system include a first task of a first core and a second task of a second core, wherein the first task is the source for triggering the second task. The method includes: obtaining a first duration between a trigger time for triggering the second task in the first task and a start synchronization time of the first task; obtaining a second duration between the trigger time and a start synchronization time of the second task; adjusting the difference between the first duration and the second duration by adjusting the trigger time; and synchronizing the first task and the second task.

Description

Technical Field

[0001] The present invention relates to the technical field of vehicle control, and particularly relates to a task synchronization method, medium and device for a multi-core system. Background Art

[0002] In a real-time operating system, two cross-core tasks can be respectively set as extended tasks, and event triggering can be placed in the extended task of the triggering core, so as to achieve task synchronization from one core to another core.

[0003] Generally, after the triggering condition is met, the setting of the triggering event is utilized, and a scheduler is used to switch the triggered task to the running state, so that the two tasks run simultaneously. However, there will be an uncertain time delay in this process. Summary of the Invention

[0004] This application provides a task synchronization method, medium and device for a multi-core system, which can avoid uncertain time delay.

[0005] The first aspect of this application discloses a task synchronization method for a multi-core system, which is used for an electronic device. The tasks of the multi-core system include a first task of a first core and a second task of a second core, where the first task is the source for triggering the second task. The method includes: obtaining a first duration between the triggering time for triggering the second task in the first task and the start synchronization time of the first task; obtaining a second duration between the triggering time and the start synchronization time of the second task; adjusting the difference between the first duration and the second duration by adjusting the triggering time; and synchronizing the first task and the second task.

[0006] In a possible implementation of the above first aspect, adjusting the difference between the first duration and the second duration by adjusting the triggering time includes adjusting the triggering time so that the first duration is close to the second duration.

[0007] In a possible implementation of the above first aspect, obtaining the first duration between the triggering time for triggering the second task in the first task and the start synchronization time of the first task includes determining the event triggering process of the second task and the synchronization process of the first task; calculating the first number of instructions of the assembly instructions between the event triggering process of the second task and the synchronization process of the first task; and multiplying the first number of instructions by the first machine cycle to obtain the first duration.

[0008] In a possible implementation of the first aspect described above, obtaining the second duration between the triggering time and the start synchronization time of the second task includes determining the synchronization process of the second task; calculating the second number of instructions between the event triggering process of the second task and the synchronization process of the second task; and multiplying the second number of instructions by a second machine cycle to obtain the second duration.

[0009] In a possible implementation of the first aspect described above, obtaining the first duration between the triggering time of the second task triggered in the first task and the start synchronization time of the first task includes determining the event triggering process of the second task and the synchronization process of the first task; starting a timer at the event triggering process of the second task and stopping the timer at the synchronization process of the first task; and obtaining the first duration according to the timer.

[0010] In a possible implementation of the first aspect described above, the on / off state of the timer is marked by flipping the status of an IO port.

[0011] In a possible implementation of the first aspect described above, it further includes sending a synchronization signal to the second core and waiting for a feedback signal at the start synchronization time of the first task; and sending a synchronization signal to the first core and waiting for a feedback signal at the start synchronization time of the second task.

[0012] In a possible implementation of the first aspect described above, the tasks of the multi-core system further include a third task, where the first task is the source for triggering the third task, and the method further includes: obtaining the third duration between the second triggering time of the third task triggered in the first task and the second start synchronization time of the first task; obtaining the fourth duration between the second triggering time and the start synchronization time of the third task; and adjusting the difference between the third duration and the fourth duration by adjusting the second triggering time.

[0013] The second aspect of the present application discloses a task synchronization method for a multi-core system, for an electronic device. The tasks of the multi-core system include a first task of a first core and a second task of a second core, where the first task is the source for triggering the second task. The method includes: running the first task on the first core; when the first task runs to a predetermined trigger point, triggering the second core to run the second task; where the first duration between the trigger point and the start synchronization time of the first task is equal to or close to the second duration between the trigger point and the start synchronization time of the second task; and synchronously running the first task and the second task.

[0014] In a possible implementation of the second aspect described above, the first duration being close to the second duration includes that the difference between the first duration and the second duration is less than or equal to one instruction cycle.

[0015] In a possible implementation of the second aspect described above, the tasks of the multi-core system further include a third task of a third core, where the first task is the source for triggering the third task, and the method further includes: when the first task runs to a second trigger point, triggering the third core to run the third task; where the third duration between the second trigger point and the second start synchronization time of the first task is equal to or close to the fourth duration between the second trigger point and the start synchronization time of the third task; and synchronously running the first task and the third task.

[0016] A third aspect of the present application discloses a computer-readable medium, where the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the methods described in the first and second aspects of the present application.

[0017] A fourth aspect of the present application discloses an electronic device, the device includes a memory storing computer-executable instructions and a processor; when the instructions are executed by the processor, the device implements the methods according to the first and second aspects of the present application.

[0018] A fifth aspect of the present application discloses a computer program product, where the computer program implements the methods described in the first and second aspects of the present application when executed by a processor.

[0019] The embodiments provided in the present application obtain the first duration between the trigger of the second task in the first task and the start synchronization time of the first task, and the second duration between the trigger of the second task and the start synchronization time of the second task. By adjusting the trigger time of the second task in advance, the difference between the first duration and the second duration can be controllably adjusted. Therefore, it is not necessary to wait for all the trigger conditions of the second task to be satisfied before triggering the event, but instead, through the way of advance compensation triggering, the hard synchronization of the two tasks can be controllably achieved at the start synchronization time of the first task and the second task. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the application scenario of the task synchronization method for the multi-core system of the present application;

[0021] Figures 2a - 2b It is a timing diagram of the task synchronization method for the multi-core system in an embodiment of the present application;

[0022] Figures 3a - 3b It is a schematic flowchart of the task synchronization method for the multi-core system in an embodiment of the present application;

[0023] Figure 4 The timing diagram of the task synchronization method for a multi-core system according to an embodiment of the present application;

[0024] Figure 5 The schematic flowchart of the task synchronization method for a multi-core system according to an embodiment of the present application;

[0025] Figure 6 The schematic flowchart of the task synchronization method for a multi-core system according to an embodiment of the present application;

[0026] Figure 7 The schematic diagram of the application scenario of the task synchronization method for a multi-core system according to an embodiment of the present application;

[0027] Figure 8 The block diagram of an electronic device according to an embodiment of the present application. Detailed implementation manners

[0028] The present application will be further described below in conjunction with specific embodiments and the accompanying drawings. It can be understood that the illustrative embodiments of the present disclosure include, but are not limited to, the task synchronization method based on a multi-core system. The specific embodiments described herein are only for explaining the present application, rather than limiting the present application. In addition, for the sake of convenience of description, only the parts related to the present application rather than all the structures or processes are shown in the drawings.

[0029] To make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0030] The task synchronization method of the multi-core system of the present application can be applied to an application scenario as Figure 1 shown. In Figure 1 , between core 0 (core 0) and core 1 (core 1) in a multi-core operating system (multi-core OS), synchronization can be achieved in various ways.

[0031] Generally, a multi-core system can be used to schedule multiple tasks on multiple cores at a time to improve system performance. The multi-core system has a wide range of applications in multiple fields, such as wireless network applications (5G), IoT technology, biomedical systems, automotive electronics, etc.

[0032] In a real-time operating system, every executed action is placed in a task. The configuration of a task includes name, priority, scheduling, activation, etc. Usually, the priority of a task can be represented by a number, and the larger the number, the higher the priority. Tasks include basic tasks and extended tasks. Basic tasks include three states, namely Ready, Running, and Suspend. Extended tasks include four states, including the Waiting state in addition to the previous three states. When the conditions for further running of an extended task cannot be met, it will enter the waiting state. Basic tasks do not have a waiting state, so they can only be synchronized when the task starts and ends, and thus can occupy less task and execution time.

[0033] As Figure 1 shown, when the task x in Core0 is executed, the task y in Core1 can be activated by setting an event (SetEvent), so that task synchronization between task x and task y can be achieved through event triggering. In addition, the synchronization of tasks that are executed regularly can also be achieved through a scheduling table.

[0034] In some embodiments, for example, in an RTOS operating system (Real-time operating system), the triggering method of cross-core tasks is to set the tasks on different cores as extended tasks and place the event triggering in the extended task of the triggering core, so as to achieve task synchronization between different cores.

[0035] Figure 2a The timing diagram of the task synchronization method of a multi-core system in an embodiment of the present application is shown. At the beginning of time, the task x in core 0 is in the running state, while the task y in core 1 is in the waiting state. Here, task x is the source for triggering task y.

[0036] When the triggering condition of task y is met, at time point T0, task y is triggered to execute in task x. For example, the SetEvent() function can be set in task x to trigger the execution of task y. The scheduler instruction switches task y from the waiting state to the ready state, and at time point Ts, the scheduler instruction switches task y from the ready state to the running state. At time point Ts, task x and task y run synchronously. There is a time delay between time point T0 of the triggering time and time point Ts of the task synchronous running.

[0037] In Figure 2a the example, task x has been in the running state from time point T0 to after time point Ts. If task x is in other states during this period, the above time delay will be in an uncertain state.

[0038] For example, in Figure 2bIn the case where the triggering condition of task y is met, at time point T0, task y is triggered to execute in task x. Since task x is in a waiting state at this time, it is necessary for the subsequent task x to switch from the waiting state to the running state, and then the scheduler instructs to switch task y from the waiting state to the ready state at time point Ts’. At time point Ts’, the scheduler instructs to switch task y from the ready state to the running state. At time point Ts’, task x and task y run synchronously. Between time point T0 of the triggering time and time point Ts’ of the task synchronous operation, it is necessary to wait until task x switches to the running state, so there is an uncertain time delay.

[0039] In Figures 2a - 2b the time delay between the triggering of the y event and the synchronous operation point of tasks x and y is uncontrollable, which is unacceptable for some situations with high real-time requirements in a real-time operating system.

[0040] To solve the above problems, an embodiment of the present application provides a task synchronization method for multi-core tasks, which does not need to wait for all the triggering conditions of the task to be met to trigger an event, but adjusts the triggering time in an advance compensation manner to controllably adjust the length between the triggering time and the start synchronization time of two tasks on different cores, avoiding uncertain time delays.

[0041] The following combines Figure 3a to illustrate the details of the embodiment of the task synchronization method for multi-core tasks according to the present application. As Figure 3a shown, a task synchronization method 300 for multi-core tasks according to an embodiment of the present application includes the following steps.

[0042] In S310, obtain a first duration between the triggering time of triggering the second task in the first task and the start synchronization time of the first task.

[0043] The electronic device applying the task synchronization method 300 for multi-core tasks can be a computer. In the field of automotive electronics, it can also be any one of the vehicle itself, the vehicle's computer, the vehicle's server, the vehicle-mounted terminal, the vehicle's processor, and the vehicle's chip, which is not limited here.

[0044] Under a multi-core real-time operating system, there are two extended tasks x and y. Task x is located on the first core (core 0), and task y is located on the second core (core 1). Among them, task x is the source for triggering task y. In some embodiments, both task x and task y are the highest-priority tasks on their respective cores. In some embodiments, it is possible to ensure that the respective tasks on the two cores are not preempted at the interrupt closing point at the switching point.

[0045] In the task table of task x, the start synchronization time of task x can be preset as T1, and a certain time T0 before time T1 can be set as the time to trigger event y. It can be understood that the start synchronization time here can refer to the time when task x meets the synchronization conditions.

[0046] After determining the trigger time of task y and the start synchronization time of task x, the first duration between the two can be determined. In some embodiments, the first duration can be calculated by various methods, such as calculating the instruction cycle or breakpoint measurement.

[0047] In S320, obtain the second duration between the trigger time and the start synchronization time of the second task.

[0048] In the task table of task y, the start synchronization time of task y can be preset as T2. After determining the trigger time of task y and the start synchronization time of task y, the second duration between the two can be determined.

[0049] In S330, adjust the difference between the first duration and the second duration by adjusting the trigger time.

[0050] After determining the start time T1 of task x and the start time T2 of task y, the first duration and the second duration can be adjusted by adjusting the trigger time T0 of task y. For example, the position of the SetEvent() function in the task table of task x can be adjusted to adjust T0. In this way, by controlling the trigger time T0 of task y, the durations between the start time T1 of task x and the trigger time T0, and between the start time T2 of task y and the trigger time T0 can be controllably determined.

[0051] In S340, synchronize the first task and the second task.

[0052] When the start time T1 of task x and the start time T2 of task y are met, task x and task y can be synchronized.

[0053] In method 300, obtain the first duration between the trigger of the second task in the first task and the start synchronization time of the first task, and the second duration between the trigger of the second task and the start synchronization time of the second task. By adjusting the trigger time of the second task in advance, the difference between the first duration and the second duration can be controllably adjusted. Therefore, there is no need to wait for all the trigger conditions of the second task to be met to trigger the event, but the two tasks are hard-synchronized at the start synchronization times of the first task and the second task by means of early compensation triggering.

[0054] Now refer to Figure 3b , Figure 3b Disclosed is a task synchronization method 301 for multi-core tasks according to an embodiment of the present application, including the following steps.

[0055] In S3011, a first task is run on a first core.

[0056] The electronic device applying the task synchronization method 301 of multi-core tasks can be a computer. In the field of automotive electronics, it can also be any one of the vehicle itself, the vehicle's computer, the vehicle's server, the in-vehicle terminal, the vehicle's processor, and the vehicle's chip, which is not limited here. It can be understood that method 301 corresponds to method 300, and the relevant steps can refer to the description in method 300. Running the first task on the first core here can be running task x on the first core (core 0).

[0057] In S3012, when the first task runs to a predetermined trigger point, the second core is triggered to run a second task; wherein, a first duration between the trigger point and the start synchronization time of the first task is equal to or close to a second duration between the trigger point and the start synchronization time of the second task.

[0058] The predetermined trigger point can be the trigger time T0 in method 300, and the trigger time T0 is adjusted according to the difference between the first duration and the second duration. When the difference between the two is small, the trigger time T0 can be determined. In some examples, the first duration can be equal to the second duration. In some other examples, the difference between the first duration and the second duration can be less than or equal to one instruction cycle.

[0059] It can be understood that the determination of the trigger point in method 301 can be implemented with reference to the examples in method 300.

[0060] In S3013, the first task and the second task are run synchronously.

[0061] When the predetermined trigger point is satisfied, the first task and the second task are run synchronously.

[0062] To better illustrate the task synchronization method of the multi-core system of the present application, Figure 4 A timing diagram of the task synchronization method of the multi-core system in an embodiment of the present application is shown.

[0063] In Figure 4 , at the beginning of time, task x in core 0 is in a running state, while task y in core 1 is in a waiting state. In the task table of task x, the start synchronization time of task x is preset as T1, and a certain time T0 before time T1 is set as the time to trigger event y. At time T0, the scheduler instructs to switch task y from the waiting state to the ready state. In the task table of task y, the start synchronization time of task y is preset as T2. Additionally, time T3 is the actual synchronization time of task x and task y.

[0064] Therefore, in some embodiments, the task synchronization method for a multi-core system further includes: at the startup synchronization time of the first task, sending a synchronization signal to the second core and waiting for a feedback signal; and at the startup synchronization time of the second task, sending a synchronization signal to the first core and waiting for a feedback signal. That is, between T1 and T3, and between T2 and T3, are the times for the two cores to send synchronization messages and wait, with a duration of one or more instruction cycles.

[0065] The difference between T1 - T0 and T2 - T0 can be calculated, and by adjusting the position of T0 in the time progress, the difference between the first duration T1 - T0 and the second duration T2 - T0 can be minimized, that is, the first duration is close to the second duration, so that T1 - T0 and T2 - T0 are as equal as possible.

[0066] Thus, T1 and T2 can be determined first, and then by adjusting T0 preset in advance, T1 - T0 and T2 - T0 can be made as equal as possible, thereby compensating for the delay between task triggering and actual synchronous execution of the task.

[0067] The first duration and the second duration can be calculated in different ways. In some embodiments, the first duration can be calculated by the number of assembly instructions between these two time points. For example, Figure 5 A method 500 for calculating the first duration according to an embodiment of the present application is shown. The method 500 includes the following steps.

[0068] In S510, determine the event trigger process of the second task and the synchronization process of the first task.

[0069] In the task list of task x, determine the synchronization process point of task x, and set the SetEvent() function at a certain process point before the synchronization process point of task x to trigger task y. Here, the previous process point is the time trigger process of the second task, and the subsequent synchronization process point of task x is the synchronization of the first task.

[0070] In S520, calculate the first number of instructions of the assembly instructions between the event trigger process of the second task and the synchronization process of the first task.

[0071] Calculate the number of all assembly instructions required between the event trigger process of the second task and the synchronization process of the first task in the task list of task x.

[0072] In S530, multiply the first number of instructions by the first machine cycle to obtain the first duration.

[0073] Multiply the number of assembly instructions obtained in S520 by the machine cycle to obtain the first duration T1 - T0.

[0074] For the second time duration, it can be obtained by using a method similar to method 500. That is, the synchronization process of the second task can be determined first; then the number of second instructions for encoding instructions between the event trigger process of the second task and the synchronization process of the second task can be calculated; finally, the second time duration can be obtained by multiplying the number of second instructions by the second machine cycle.

[0075] After obtaining the first time duration T1 - T0 and the second time duration T2 - T0, the position of the event trigger process of task y in the task list of task x can be adjusted to make the first time duration T1 - T0 and the second time duration T2 - T0 close.

[0076] In addition to using the calculation method of instruction cycles, the first and second time durations can also be calculated by breakpoint measurement. For example, Figure 6 Figure 600 shows a method for calculating the first time duration according to an embodiment of the present application. Method 600 includes the following steps.

[0077] In S610, determine the event trigger process of the second task and the synchronization process of the first task.

[0078] In the task list of task x, determine the synchronization process point of task x, that is, the synchronization process of the first task. And set the SetEvent() function at a certain process point before the synchronization process point of task x to trigger task y. Here, the process point is the time trigger process of the second task.

[0079] In S620, start the timer at the event trigger process of the second task and stop the timer at the synchronization process of the first task.

[0080] In some examples, the on - off state of the timer is marked by flipping the IO port state. For example, the IO port can be flipped at the trigger process point of task y to start the timer; and the IO port is flipped again at the synchronization process of task x to stop the timer.

[0081] In S630, obtain the first time duration according to the timer.

[0082] Obtain the first time duration according to the on - off state of the timer. For the second time duration, it can be obtained by using a method similar to method 600, which will not be elaborated here.

[0083] The task synchronization method of the multi - core system of the present application is not limited to the case of two cores, and can also be applied to the case of more than two cores. For example, Figure 7 Figure shows a multi - core scenario diagram according to an embodiment of the present application. In Figure 7 In, the multi - core system includes 3 cores, core 0, core 1, and core 2. The task x in core 0 is the source for triggering task y in core 1 and task z in core 2.

[0084] InFigure 7 In the scenario of , the task synchronization method further includes obtaining the time durations between the trigger time of task z and the start synchronization time of task x (synchronized with task z), and between the trigger time of task z and the start synchronization time of task z, and adjusting the difference between these two time durations by adjusting the trigger time of task z.

[0085] Specifically, Figure 7 the task synchronization method in the scenario of further includes the following steps.

[0086] In S710, obtain a third time duration between the second trigger time that triggers the third task in the first task and the second start synchronization time of the first task.

[0087] In S720, determine a fourth time duration between the second trigger time and the start synchronization time of the third task.

[0088] In S730, adjust the difference between the third time duration and the fourth time duration by adjusting the second trigger time.

[0089] Similar to the above methods 300 and 301, Figure 7 the task synchronization method in the scenario of further includes the following steps.

[0090] In S711, run the first task on the first core.

[0091] In S712, when the first task runs to a predetermined trigger point, trigger the second core to run the second task; wherein, the first time duration between the trigger point and the start synchronization time of the first task is equal to or close to the second time duration between the trigger point and the start synchronization time of the second task.

[0092] In S713, synchronously run the first task and the second task.

[0093] Now refer to Figure 8 , which shows a block diagram of an electronic device 800 according to an embodiment of the present application. The device 800 may include one or more processors 802, a system control logic 808 connected to at least one of the processors 802, a system memory 804 connected to the system control logic 808, a non-volatile memory (NVM) 806 connected to the system control logic 808, and a network interface 810 connected to the system control logic 808.

[0094] The processor 802 may include multiple single-core or multi-core processors. The processor 802 may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, vehicle processors, etc.). In the embodiments herein, the processor 802 may be configured to execute one or more embodiments according to various embodiments as shown in Figures 3a - 7 .

[0095] In some embodiments, the system control logic 808 may include any suitable interface controller to provide any suitable interface to at least one of the processors 802 and / or any suitable device or component communicating with the system control logic 808.

[0096] In some embodiments, the system control logic 808 may include one or more memory controllers to provide an interface to the system memory 804. The system memory 804 may be used to load and store data and / or instructions. In some embodiments, the memory 804 of the device 800 may include any suitable volatile memory, such as a suitable dynamic random access memory (DRAM).

[0097] The NVM / memory 806 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the NVM / memory 806 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as at least one of a HDD (Hard Disk Drive), a CD (Compact Disc) drive, and a DVD (Digital Versatile Disc) drive.

[0098] The NVM / memory 806 may include a portion of the storage resources installed on the device 800, or it may be accessible by the device but not necessarily part of the device. For example, the NVM / storage 806 may be accessed via the network interface 810 over a network.

[0099] Specifically, the system memory 804 and the NVM / memory 806 may respectively include: a temporary copy and a permanent copy of the instructions 820. The instructions 820 may include: instructions that, when executed by at least one of the processors 802, cause the device 800 to implement the method as Figures 3a - 7 shown. In some embodiments, the instructions 820, hardware, firmware, and / or its software components may alternatively / additionally be located in the system control logic 808, the network interface 810, and / or the processor 802.

[0100] The network interface 810 may include a transceiver for providing a radio interface for the device 800, and further communicating with any other suitable devices (such as a front-end module, an antenna, etc.) through one or more networks. In some embodiments, the network interface 810 may be integrated with other components of the device 800. For example, the network interface 810 may be integrated with at least one of the processor 802, the system memory 804, the NVM / memory 806, and a firmware device (not shown) having instructions. When at least one of the processors 802 executes the instructions, the device 800 implements one or more of the various embodiments shown in FIGS. 2-7.

[0101] The network interface 810 may further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface. For example, the network interface 810 may be a network adapter, a wireless network adapter, a telephone modem, and / or a wireless modem.

[0102] In one embodiment, at least one of the processors 802 may be packaged with the logic of one or more controllers for the system control logic 808 to form a system-in-package (SiP). In one embodiment, at least one of the processors 802 may be integrated with the logic of one or more controllers for the system control logic 808 on the same die to form a system-on-chip (SoC).

[0103] The device 800 may further include an input / output (I / O) device 812. The I / O device 812 may include a user interface that enables a user to interact with the device 800; the design of the peripheral component interface enables peripheral components to also interact with the device 800. In some embodiments, the device 800 further includes sensors for determining at least one of environmental conditions and location information related to the device 800.

[0104] In some embodiments, the user interface may include, but is not limited to, a display (e.g., a liquid crystal display, a touch screen display, etc.), a speaker, a microphone, one or more cameras (e.g., a still image camera and / or a video camera), a flashlight (e.g., a light-emitting diode flash), and a keyboard.

[0105] In some embodiments, the peripheral component interface may include, but is not limited to, a non-volatile memory port, an audio jack, and a power interface.

[0106] In some embodiments, the sensors may include, but are not limited to, a gyroscope sensor, an accelerometer, a proximity sensor, an ambient light sensor, and a positioning unit. The positioning unit may also be part of the network interface 810 or interact with the network interface 810 to communicate with components of a positioning network (e.g., Global Positioning System (GPS) satellites).

[0107] It can be understood that the structure illustrated in the embodiments of the present invention does not constitute a specific limitation on the device 800. In other embodiments of the present application, the device 800 may include more or fewer components than those illustrated, or combine certain components, or split certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0108] Program code can be applied to the input instructions to perform the various functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of the present application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0109] The program code can be implemented in a high-level procedural language or an object-oriented programming language in order to communicate with the processing system. When needed, the program code can also be implemented in assembly language or machine language. In fact, the mechanisms described herein are not limited to the scope of any particular programming language. In any case, the language can be a compiled language or an interpreted language.

[0110] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a computer-readable storage medium, the instructions representing various logics in a processor, and the instructions, when read by a machine, cause the machine to fabricate the logics for performing the techniques described herein. These representations, referred to as "IP cores", can be stored on a tangible computer-readable storage medium and provided to multiple customers or production facilities to be loaded into the manufacturing machines that actually fabricate the logics or processors.

[0111] An embodiment of the present application discloses a computer-readable medium storing one or more programs executable by one or more processors to implement the task synchronization method of the multi-core system of the present application.

[0112] An embodiment of the present application discloses a computer program product including a computer program that, when executed by a processor, implements the task synchronization method of the multi-core system of the present application.

[0113] Although the description of the present application will be introduced in conjunction with preferred embodiments, this does not mean that the features of this invention are limited to this implementation. To provide a deep understanding of the present application, the description of the present application contains many specific details. The present application can also be implemented without using these details. In addition, to avoid confusion or obscuring the focus of the present application, some specific details will be omitted in the description. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0114] In addition, various operations will be described as multiple discrete operations in a manner that is most helpful in understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations must be order-dependent.

[0115] In the accompanying drawings, some structural or method features are shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or ordering may not be required. In some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Additionally, the inclusion of a structural or method feature in a particular figure does not imply that such a feature is required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0116] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements or data, these elements or data should not be limited by these terms. These terms are used merely to distinguish one feature from another. For example, without departing from the scope of the exemplary embodiments, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature.

[0117] It should be noted that in this specification, like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

[0118] Although the present invention has been illustrated and described with reference to certain preferred embodiments thereof, those of ordinary skill in the art should understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A task synchronization method for a multi-core system, which is used for an electronic device, characterized in that, The tasks of the multi-core system include a first task of a first core and a second task of a second core, where the first task is the source for triggering the second task. The method includes: Obtaining a first duration between a trigger time for triggering the second task in the first task and a start synchronization time of the first task; Obtaining a second duration between the trigger time and a start synchronization time of the second task; Adjusting the difference between the first duration and the second duration by adjusting the trigger time; and Synchronizing the first task and the second task.

2. The method according to claim 1, wherein Adjusting the difference between the first duration and the second duration by adjusting the trigger time includes Adjusting the trigger time to reduce the difference between the first duration and the second duration.

3. The method according to claim 1, wherein Obtaining a first duration between a trigger time for triggering the second task in the first task and a start synchronization time of the first task includes Determining an event trigger process of the second task and a synchronization process of the first task; Calculating a first number of instructions of assembly instructions between the event trigger process of the second task and the synchronization process of the first task; and Multiplying the first number of instructions by a first machine cycle to obtain the first duration.

4. The method according to claim 3, characterized in that, Obtaining a second duration between the trigger time and a start synchronization time of the second task includes Determining a synchronization process of the second task; Calculating a second number of instructions of compiled instructions between the event trigger process of the second task and the synchronization process of the second task; And Multiplying the second number of instructions by a second machine cycle to obtain the second duration.

5. The method according to claim 1, wherein Obtaining a first duration between a trigger time for triggering the second task in the first task and a start synchronization time of the first task includes Determining an event trigger process of the second task and a synchronization process of the first task; Starting a timer at the event trigger process of the second task and stopping the timer at the synchronization process of the first task; and Obtaining the first duration according to the timer.

6. The method according to claim 5, wherein The on / off state of the timer is marked by flipping the state of an IO port.

7. The method according to claim 1, characterized in that, It further includes Sending a synchronization signal to the second core at the start synchronization time of the first task and waiting for a feedback signal; and Sending a synchronization signal to the first core at the start synchronization time of the second task and waiting for a feedback signal.

8. The method according to claim 1, characterized in that, The tasks of the multi-core system further include a third task, where the first task is the source for triggering the third task. The method further includes: Obtaining a third duration between a second trigger time for triggering the third task in the first task and a second start synchronization time of the first task; Obtaining a fourth duration between the second trigger time and a start synchronization time of the third task; and Adjusting the difference between the third duration and the fourth duration by adjusting the second trigger time.

9. A task synchronization method for a multi-core system, for an electronic device, characterized in that The tasks of the multi-core system include a first task of a first core and a second task of a second core, where the first task is the source for triggering the second task. The method includes: Running the first task on the first core; When the first task runs to a predetermined trigger point, trigger the second core to run the second task; wherein, the difference between the first duration between the trigger point and the start synchronization time of the first task and the second duration between the trigger point and the start synchronization time of the second task is less than or equal to one instruction cycle; and Run the first task and the second task synchronously.

10. The method according to claim 9, wherein The tasks of the multi-core system further include a third task of a third core, wherein the first task is the source for triggering the third task, and the method further includes: When the first task runs to a second trigger point, trigger the third core to run the third task; wherein, the difference between the third duration between the second trigger point and the second start synchronization time of the first task and the fourth duration between the second trigger point and the start synchronization time of the third task is less than or equal to one instruction cycle; and Run the first task and the third task synchronously.

11. A computer-readable medium, characterized in that, The medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method according to any one of claims 1 to 10.

12. An electronic device, characterized in that, The device includes a memory storing computer-executable instructions and a processor; when the instructions are executed by the processor, the device is caused to implement the method according to any one of claims 1 to 10.

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