Memory device and zq calibration method

Abstract

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, the memory device comprising: a master chip and a plurality of slave chips, provided with a first transmission end and a second transmission end, and the first transmission ends are connected to each other, and the second transmission ends are connected to each other; the master chip is provided with a first signal receiver and an address transmitter, and the slave chip is provided with a second signal receiver; the first signal receiver is used for receiving a ZQ calibration command, the master chip starts calibration based on the ZQ calibration command, and the master chip sends a ZQ flag signal after completing calibration; the address transmitter sends an address signal; the second signal receiver is used for matching the address signal and receiving the ZQ flag signal, the slave chip matching the address signal starts calibration based on the ZQ flag signal, and the current slave chip sends a ZQ flag signal after completing calibration; and the address transmitter sends a next address signal. The embodiment of the present disclosure designs a new control circuit to realize the sharing of ZQ calibration resistance by multiple chips.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a memory device and a ZQ calibration method. Background Technology

[0002] ZQ calibration is a very important function in Dynamic Random Access Memory (DRAM). Specifically, it relates to whether the output impedance of the output port is accurate and whether the termination resistor of the input port is accurate. Deviations in these parameters can cause severe distortion of the signal during transmission due to impedance mismatch. Moreover, the higher the signal frequency, the greater the impact of distortion on the signal.

[0003] JEDEC's packaging definition specifies the number of ZQ calibration resistors required for LPDDR5. For example, DIS315 chips have one ZQ calibration resistor, while POP496 chips have two ZQ calibration resistors. It is evident that the number of ZQ calibration resistors in LPDDR5 is significantly less than that in LPDDR4.

[0004] As the demand for LPDDR capacity increases, more and more chips are being placed in a single LPDDR package. Each chip requires individual ZQ calibration due to its unique characteristics. In particular, the number of ZQ calibration resistors in LPDDR5 packages is significantly reduced compared to LPDDR4, requiring more chips to share a single ZQ. How to achieve ZQ calibration by sharing ZQ calibration resistors among multiple chips is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides a memory device and a ZQ calibration method, which achieves shared ZQ calibration resistors across multiple chips by designing a novel control circuit.

[0006] This disclosure provides a memory device, including: a master chip and multiple slave chips, the master chip and slave chips being connected to the same calibration resistor; the master chip and slave chips are provided with a first transmission terminal and a second transmission terminal, and the first transmission terminals of the master chip and slave chips are interconnected, and the second transmission terminals are interconnected; the first transmission terminal is used to transmit a ZQ flag signal, and the second transmission terminal is used to transmit an address signal; the master chip is provided with a first signal receiver and an address transmitter, and the slave chips are provided with a second signal receiver; the first signal receiver is used to receive a ZQ calibration command provided by the memory through the ZQ signal terminal, and the master chip receives the ZQ calibration command based on the ZQ calibration command. The calibration process begins. After the master chip completes calibration, it sends a ZQ flag signal through the first transmission terminal. The ZQ flag signal indicates that the current chip has been calibrated using the calibration resistor. The address transmitter sends an address signal through the second transmission terminal. The address signal indicates the address of the slave chip to be calibrated using ZQ. The second signal receiver is used to match the address signal and receives the ZQ flag signal through the first transmission terminal. The slave chip with the matched address signal starts calibration based on the ZQ flag signal. After the current slave chip completes calibration, it sends the ZQ flag signal through the first transmission terminal. The address transmitter continues to send the next address signal through the second transmission terminal until all slave chips have been calibrated.

[0007] In the memory device provided in this embodiment, the first transmission terminals of the master chip and all slave chips are connected to the same bus, and the second transmission terminals of the master chip and all slave chips are also connected to the same bus. That is, the master chip and all slave chips form a broadcast loop through two buses. During ZQ calibration, the master chip performs ZQ calibration first. After completing ZQ calibration, the master chip broadcasts the address of a slave chip. The slave chip with the matching address responds to the broadcast address and performs ZQ calibration based on the ZQ flag signal. After completing ZQ calibration, the slave chip releases the ZQ flag signal, and the master chip continues to broadcast the address of another slave chip until all slave chips have completed ZQ calibration. All chips are connected to two buses, simplifying the design of the memory device package substrate.

[0008] Additionally, the address transmitter includes: an address storage unit for storing the address signals of all slave chips; and an address transmission unit connected to the address storage unit, configured to transmit the address signals of the slave chips sequentially.

[0009] In addition, the address transmitter also includes an address sorting unit, which is connected to the address storage unit and the address sending unit and is configured to sort all address signals; the address sending unit sends the sorted address signals sequentially.

[0010] In addition, the address transmitter sends the address signals of the slave chips in response to the ZQ flag signal. Since the ZQ flag indicates that the chip has completed ZQ calibration, the address signal is sent according to the ZQ flag signal to start the ZQ calibration of the next slave chip, so as to avoid calibration timing disorder.

[0011] In addition, after the last slave chip completes ZQ calibration and releases the ZQ flag signal, the master chip also sends a flag signal to indicate that all chips have completed ZQ calibration.

[0012] Additionally, the first signal receiver includes: a first AND gate, one input for receiving a ZQ calibration command and the other input for receiving a command indication signal, the command indication signal indicating that the memory is operating in command mode; a second AND gate, one input for receiving a clock signal or a power-on signal and the other input for receiving a background indication signal, the background indication signal indicating that the memory is operating in background mode; and a first input selector, the first input of which is connected to the output of the first AND gate, and the second input of which is connected to the input of the second AND gate, the first selector being used to receive the command indication signal or the background indication signal, and the first output being used to output a first internal calibration signal, the first internal calibration signal indicating the main core... The chip is calibrated; wherein, the first input selector is configured to connect the first input terminal to the first output terminal based on a command indication signal, or connect the second input terminal to the first output terminal based on a background indication signal; the second signal receiver includes: a judgment unit, used to receive the address signal transmitted by the second transmission terminal and obtain the address signal of the slave chip to which it belongs; if the address signal transmitted by the second transmission terminal is the same as the address signal of the slave chip to which it belongs, then send a first indication signal; a third AND gate, one input terminal is used to receive the ZQ flag signal, the other input terminal is used to receive the first indication signal, and the output terminal is used to output a second internal calibration signal, the second internal calibration signal being used to instruct the slave chip to perform calibration.

[0013] In addition, the master chip also includes a second signal receiver, and the slave chip also includes a first signal receiver; the master chip and the slave chip also include: a second input selector, a third input terminal connected to a first output terminal, a fourth input terminal connected to the output terminal of a third AND gate, the second selector terminal being used to receive a second indication signal or a third indication signal, the second indication signal being used to indicate that the current chip is the master chip, the third indication signal being used to indicate that the current chip is the slave chip, and the second output terminal being used to output a first internal calibration command and a second internal calibration command; wherein, the second input selector is configured to connect the third input terminal to the second output terminal based on the second indication signal, or to connect the fourth input terminal to the second output terminal based on the third indication signal.

[0014] In addition, the master chip and slave chip are packaged in the same memory device.

[0015] In addition, the main chip and some slave chips are packaged in different memory devices, wherein the connection between the first transmission end packaged in different memory devices and the connection between the second transmission end are set through wired or wireless interconnection between memory devices.

[0016] In addition, the number of slave chips is the same as the amount of binary data contained in the address signal, in order to maximize the number of slave chips and increase the number of chips sharing the same calibration resistor.

[0017] This disclosure also provides a ZQ calibration method applied to the memory device provided in the above embodiments, comprising: in command mode, acquiring a ZQ calibration command applied externally to the memory device, or in background mode, acquiring a clock signal or power-on signal applied externally to the memory device; in response to the ZQ calibration command, clock signal, or power-on signal, performing a first calibration operation on the master chip; after the first calibration operation is completed, sending a ZQ flag signal and an address signal, and simultaneously performing a second calibration operation on the master chip; slave chips that meet the address signal respond to the ZQ flag signal and perform the first calibration operation; after the slave chips complete the first calibration operation, sending a ZQ flag signal, and simultaneously performing the second calibration operation on the slave chips; the master chip resends the address signal, and slave chips that meet the address signal respond to the ZQ flag signal and perform the first calibration operation, until all slave chips complete the first calibration operation; and performing the second calibration operation on the last slave chip to complete the first calibration operation, so as to realize the sharing of ZQ calibration resistor among multiple chips.

[0018] In addition, the main chip sends an address signal in response to the ZQ flag signal.

[0019] In addition, the main chip sends the sorted address signals sequentially based on the order of all address signals.

[0020] In addition, the main chip retransmits the address signal, which also includes: after the main chip has completed the transmission of all address signals, the main chip sends a flag signal, which is used to indicate that all chips have completed ZQ calibration. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a memory device provided in an embodiment of the present disclosure;

[0023] Figure 2 This is a schematic diagram of the structure of a first signal receiver provided in an embodiment of the present disclosure;

[0024] Figure 3 This is a schematic diagram of the structure of a second signal receiver provided in an embodiment of the present disclosure;

[0025] Figure 4 This is a schematic diagram of the integrated structure of a first signal receiver and a second signal receiver provided in an embodiment of the present disclosure;

[0026] Figure 5 A timing diagram illustrating ZQ calibration of a memory device provided in another embodiment of this disclosure. Detailed Implementation

[0027] As the background technology shows, with the increasing demand for LPDDR capacity, more and more chips are put into one LPDDR package. Each chip needs to be individually calibrated due to individual differences. In particular, the number of ZQ calibration resistors in LPDDR5 packages is significantly reduced compared to the number of ZQ calibration resistors in LPDDR4, requiring more chips to share a single ZQ.

[0028] One embodiment of this disclosure provides a memory device that enables multiple chips to share a ZQ calibration resistor by designing a novel control circuit.

[0029] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0030] Figure 1 This is a schematic diagram of the memory device provided in this embodiment. Figure 2 This is a schematic diagram of the structure of the first signal receiver provided in this embodiment. Figure 3 This is a schematic diagram of the structure of the second signal receiver provided in this embodiment. Figure 4 This is a schematic diagram of the integrated structure of the first and second signal receivers provided in this embodiment. The structure of the memory device provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0031] refer to Figure 1 Memory devices, including:

[0032] The main chip 100 and multiple slave chips 101 are connected together to the same calibration resistor Rzq.

[0033] Specifically, one end of the calibration resistor Rzq is used to connect the ZQ terminals of the master chip 100 and the slave chip 101, and the other end is used to receive the calibration voltage VDD.

[0034] The master chip 100 and the slave chip 101 are provided with a first transmission terminal A and a second transmission terminal B. The first transmission terminal A of the master chip 100 and the slave chip 101 are interconnected, and the second transmission terminal B is interconnected. The first transmission terminal A is used to transmit the ZQ flag signal, and the second transmission terminal B is used to transmit the address signal.

[0035] It should be noted that, in the following description, the multiple slave chips 101 mentioned above will be referred to as the first slave chip, the second slave chip, ... the (N-1)th slave chip and the Nth slave chip in order to reflect the differences between the slave chips 101, where N is the number of slave chips 101.

[0036] The main chip 100 is equipped with a first signal receiver and an address transmitter, and the slave chip 101 is equipped with a second signal receiver.

[0037] Specifically, the first signal receiver is used to receive the ZQ calibration command provided by the memory through the ZQ signal terminal. The main chip 100 starts calibration based on the ZQ calibration command. After the main chip 100 completes calibration, it sends a ZQ flag signal through the first transmission terminal A. The ZQ flag signal indicates that the current chip has been calibrated using the calibration resistor Rzq. The address transmitter sends an address signal through the second transmission terminal B. The address signal indicates the address of the slave chip 101 to be ZQ calibrated. The second signal receiver is used to match the address signal and receive the ZQ flag signal through the first transmission terminal A. The slave chip 101 with the matched address signal starts calibration based on the ZQ flag signal. After the current slave chip 101 completes calibration, it sends a ZQ flag signal through the first transmission terminal A. The address transmitter continues to send the next address signal through the second transmission terminal B... until all slave chips 101 are calibrated.

[0038] In the memory device provided in this embodiment, the first transmission terminal A of the master chip 100 and all slave chips 101 are connected to the same bus, and the second transmission terminal B of the master chip 100 and all slave chips 101 are also connected to the same bus. That is, the master chip 100 and all slave chips 101 are connected through two buses, forming a broadcast loop. During ZQ calibration, the master chip 100 performs ZQ calibration first. After completing ZQ calibration, the master chip 100 broadcasts the address of one slave chip 101. The slave chip with the matching address responds to the broadcast address and performs ZQ calibration based on the ZQ flag signal. After completing ZQ calibration, the slave chip releases the ZQ flag signal, and the master chip continues to broadcast the address of another slave chip 101… until all slave chips 101 have completed ZQ calibration. For the memory device provided in this embodiment, all chips are connected to two buses, simplifying the design of the memory device packaging substrate.

[0039] It should be noted that the aforementioned "first signal receiver is used to receive the ZQ calibration command provided by the memory through the ZQ signal terminal, and the main chip 100 starts calibration based on the ZQ calibration command" refers to the calibration logic of the main chip 100 in command mode. In background mode, the first signal receiver receives the clock signal or power-on signal provided by the memory through the ZQ signal port or other signal interfaces, and the main chip 100 starts calibration based on the clock signal or power-on signal.

[0040] Based on the above discussion, it can be seen that the ZQ calibration of the slave chip 101 is driven by the address signal. Therefore, the number of slave chips 101 set in the memory device is related to the number of bits of the address signal. In some embodiments, the number of slave chips 101 is the same as the number of binary data contained in the address signal, so as to maximize the number of slave chips 101 and increase the number of chips sharing the same calibration resistor.

[0041] Based on the above discussion, it can be seen that after the master chip 100 broadcasts the addresses of all slave chips 101, it indicates that all slave chips 101 have completed ZQ calibration. After the last slave chip 101 completes ZQ calibration and releases the ZQ flag signal, the master chip is also used to send a flag signal. The flag signal is used to indicate that all chips have completed ZQ calibration, so as to facilitate the design of subsequent memory circuits and signal timing.

[0042] It should be noted that the flag signal can be arbitrarily set to a signal that can be recognized by the memory, such as the address signal of the main chip 100. This embodiment does not constitute a limitation on the flag signal setting method. In specific applications, the flag signal can be set according to the specific application scenario.

[0043] In some embodiments, the address transmitter includes an address storage unit and an address sending unit, wherein the address storage unit stores address signals of all slave chips 101; the address sending unit is connected to the address storage unit and configured to sequentially send the address signals of the slave chips. Further, in some embodiments, the address transmitter further includes an address sorting unit, connected to the address storage unit and the address sending unit, configured to sort all address signals, and the address sending unit sequentially sends the sorted address signals. Even further, in some embodiments, the address sending unit is configured to sequentially send address signals based on a ZQ flag signal. Since the ZQ flag indicates that the chip has completed ZQ calibration, sending address signals according to the ZQ flag signal initiates the ZQ calibration of the next slave chip 101 to avoid calibration timing errors.

[0044] In some embodiments, reference Figure 2The first signal receiver 200 includes: a first AND gate 201, one input for receiving a ZQ calibration command and the other input for receiving a command indication signal, the command indication signal being used to indicate that the memory is operating in command mode; a second AND gate 202, one input for receiving a clock signal or a power-on signal and the other input for receiving a background indication signal, the background indication signal being used to indicate that the memory is operating in background mode; and a first input selector 203, the first input of which is connected to the input of the first AND gate 201 and the second input of which is connected to the input of the second AND gate 202, the first selector being used to receive the command indication signal or the background indication signal, and the first output being used to output a first internal calibration signal, the first internal calibration signal being used to instruct the main chip 100 to perform calibration; wherein, the first input selector 203 is configured to connect the first input to the first output based on the command indication signal, or to connect the second input to the first output based on the background indication signal.

[0045] Specifically, when the memory is in command mode, it provides a command indication signal to the first signal receiver 200 of the main chip 100. The first input selector 203 connects the first input terminal to the first output terminal based on the command indication signal. At this time, the first signal receiver 200 provides a first internal calibration signal, that is, when the first signal receiver 200 receives a ZQ calibration command, it generates the first internal calibration signal, thereby controlling the main chip 100 to perform ZQ calibration. When the memory is in background mode, it provides a background indication signal to the first signal receiver 200 of the main chip 100. The first input selector 203 connects the second input terminal to the first output terminal based on the background indication signal. At this time, the first signal receiver 200 provides a first internal calibration signal, that is, when the first signal receiver 200 receives a clock signal or a power-on signal, it generates the first internal calibration signal, thereby controlling the main chip 100 to perform ZQ calibration.

[0046] In some embodiments, reference Figure 3 The second signal receiver 300 includes: a judgment unit 302, used to receive the address signal transmitted by the second transmission terminal B and obtain the address signal of the slave chip 101; if the address signal transmitted by the second transmission terminal B is the same as the address signal of the slave chip 10, then a first indication signal is sent; and a third AND gate 301, one input terminal is used to receive the ZQ flag signal, the other input terminal is used to receive the first indication signal, and the output terminal is used to output a second internal calibration signal, which is used to instruct the slave chip to perform calibration.

[0047] Specifically, regardless of whether it is in command mode or background mode, after the master chip 100 completes ZQ calibration, it sends a ZQ flag signal and an address signal. The second signal receiver 300 of the slave chip 101 performs address verification. The address signal transmitted by the second transmission terminal B is the same as the address signal of the slave chip 10, generating a first indication signal. The third AND gate 301 generates a second internal calibration signal based on the first indication signal and the ZQ flag signal. The current slave chip 101 starts to perform ZQ calibration based on the second internal calibration signal.

[0048] Figure 1 In the memory device structure shown, only the master chip receives the ZQ calibration command, and the master chip integrates the first signal receiver 200, while the slave chip integrates the second signal receiver 300, resulting in a difference in the structure of the master chip and the slave chip. In some embodiments, the master chip and the slave chip have the same structure, that is, the master chip also includes the second signal receiver 300, and the slave chip also includes the first signal receiver 200. However, it should be noted that although the slave chip includes the first signal receiver 200, the slave chip may or may not receive the ZQ calibration command.

[0049] For details, please refer to the following: Figure 4 The master chip and slave chip also include: a second input selector 401, a third input terminal connected to a first output terminal (i.e., the output terminal of the first signal receiver 200), a fourth input terminal connected to the output terminal of a third AND gate 301 (i.e., the output terminal of the third AND gate 301), a second selection terminal for receiving a second indication signal or a third indication signal, the second indication signal for indicating that the current chip is the master chip 100, the third indication signal for indicating that the current chip is the slave chip 101, and a second output terminal for outputting a first internal calibration command or a second internal calibration command; wherein, the second input selector 401 is configured to connect the third input terminal to the second output terminal based on the second indication signal, or connect the fourth input terminal to the second output terminal based on the third indication signal, the second output terminal being the output terminal of the second input selector 401.

[0050] Specifically, the second input selector 401 selects the output based on the second indication signal and the third indication signal. When the third indication signal is received, it indicates that the current chip is the master chip, and the second input selector 401 selects the output signal of the first signal receiver 200 for output. When the third indication signal is received, it indicates that the current chip is the slave chip 101, and the second input selector 401 selects the output signal of the second signal receiver 300 for output.

[0051] In some embodiments, the master chip 100 and the slave chip 101 are packaged in the same memory device.

[0052] In some embodiments, the master chip 100 and the slave chip 101 are packaged in different memory devices, wherein the connection between the first transmission terminals A and the connection between the second transmission terminals B packaged in the different memory devices are set by wired or wireless interconnection between the memory devices.

[0053] In the memory device provided in this embodiment, the first transmission terminal A of the master chip 100 and all slave chips 101 are connected to the same bus, and the second transmission terminal B of the master chip 100 and all slave chips 101 are also connected to the same bus. That is, the master chip 100 and all slave chips 101 are connected via two buses, forming a broadcast loop. During ZQ calibration, the master chip 100 performs ZQ calibration first. After completing ZQ calibration, the master chip 100 broadcasts the address of one slave chip 101. The slave chip with the matching address responds to the broadcast address and performs ZQ calibration based on the ZQ flag signal. After completing ZQ calibration, the slave chip releases the ZQ flag signal, and the master chip continues to broadcast the address of another slave chip 101… until all slave chips 101 have completed ZQ calibration. All chips are connected to two buses, simplifying the design of the memory device packaging substrate.

[0054] It should be noted that when there is a limitation on the ZQ calibration time, the number of chips sharing the ZQ calibration resistor is also limited. The longer the time required for each chip to perform ZQ calibration, the fewer chips there are to share the ZQ calibration resistor. In addition, the features disclosed in the memory devices provided in the above embodiments can be arbitrarily combined without conflict to obtain new memory device embodiments.

[0055] Another embodiment of this disclosure provides a ZQ calibration method applied to the memory device provided in the above embodiments to enable multiple chips to share a ZQ calibration resistor.

[0056] Figure 5 The timing diagram for ZQ calibration of the memory device provided in this embodiment is shown below. The ZQ calibration method provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0057] refer to Figure 5The ZQ calibration method includes: in command mode, acquiring a ZQ calibration command applied externally to the memory device, or in background mode, acquiring a clock signal or power-on signal applied externally to the memory device; in response to the ZQ calibration command, clock signal, or power-on signal, performing a first calibration operation on the master chip; after the first calibration operation is completed, sending a ZQ flag signal and an address signal, and simultaneously performing a second calibration operation on the master chip; slave chips that meet the address signal respond to the ZQ flag signal and perform the first calibration operation; after the slave chips complete the first calibration operation, sending a ZQ flag signal, and simultaneously performing the second calibration operation on the aforementioned slave chips that meet the address signal; the master chip resends the address signal, and slave chips that meet the new address signal respond to the ZQ flag signal and perform the first calibration operation... until all slave chips complete the first calibration operation, and after all slave chips complete the first calibration operation, performing the second calibration operation on the last slave chip that completes the first calibration operation.

[0058] In the ZQ calibration method provided in this embodiment, the master chip first performs ZQ calibration. After the master chip completes the ZQ calibration, it broadcasts the address of a slave chip. The slave chip with the matching address responds to the broadcast address and performs ZQ calibration based on the ZQ flag signal. After the slave chip completes the ZQ calibration, it releases the ZQ flag signal. The master chip continues to broadcast the address of another slave chip until all slave chips complete the ZQ calibration, thereby realizing the sharing of the ZQ calibration resistor among multiple chips.

[0059] It should be noted that, Figure 5 The ZQ calibration timing diagram shown uses three slave chips as an example for illustration only. It is intended to help those skilled in the art understand the implementation of ZQ calibration in this embodiment and does not constitute a limitation of this embodiment. Figure 5 The illustration and the ZQ calibration method mentioned above can be used to... Figure 5 The timing is then further derived to apply to the case of N slave chips.

[0060] In some embodiments, the main chip retransmits the address signals, and further includes: after the main chip has completed the transmission of all address signals, the main chip sends a flag signal, which is used to indicate that all chips have completed ZQ calibration, so as to facilitate the design of subsequent memory circuits and signal timing.

[0061] It should be noted that the flag signal can be arbitrarily set to a signal that can be recognized by the memory, such as the address signal of the main chip. This embodiment does not constitute a limitation on the flag signal setting method. In specific applications, the flag signal can be set according to the specific application scenario.

[0062] In some embodiments, the master chip is also used to sort the address signals of all slave chips, and the master chip sends the sorted address signals sequentially based on the sorting of all address signals.

[0063] In some embodiments, the master chip sends an address signal in response to the ZQ flag signal. Since the ZQ flag indicates that the chip has completed ZQ calibration, the address signal is sent according to the ZQ flag signal to start the ZQ calibration of the next slave chip, so as to avoid calibration timing disorder. In other embodiments, the address signal can also be sent at equal time intervals, that is, it is not limited by the ZQ flag signal.

[0064] In the ZQ calibration method provided in this embodiment, the master chip first performs ZQ calibration. After the master chip completes the ZQ calibration, it broadcasts the address of a slave chip. The slave chip with the matching address responds to the broadcast address and performs ZQ calibration based on the ZQ flag signal. After the slave chip completes the ZQ calibration, it releases the ZQ flag signal. The master chip continues to broadcast the address of another slave chip until all slave chips complete the ZQ calibration, thereby realizing the sharing of the ZQ calibration resistor among multiple chips.

[0065] It should be noted that, in this embodiment, the first calibration operation is one of the pull-up calibration operation that generates the pull-up calibration code and the pull-down calibration operation that generates the pull-down calibration code, and the second calibration operation is the other of the pull-up calibration operation and the pull-down calibration operation; in addition, the features disclosed in the ZQ calibration method provided in the above embodiments can be arbitrarily combined without conflict to obtain new ZQ calibration method embodiments.

[0066] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that, include: A master chip and multiple slave chips, wherein the master chip and the slave chips are all connected to the same calibration resistor; The master chip and the slave chip are provided with a first transmission terminal and a second transmission terminal, and the first transmission terminals of the master chip and the slave chip are interconnected, and the second transmission terminals are interconnected. The first transmission terminal is used to transmit the ZQ flag signal, and the second transmission terminal is used to transmit the address signal; The main chip is equipped with a first signal receiver and an address transmitter, and the slave chip is equipped with a second signal receiver; The first signal receiver is used to receive the ZQ calibration command provided by the memory through the ZQ signal terminal. The main chip starts calibration based on the ZQ calibration command. After the main chip completes the calibration, it sends the ZQ flag signal through the first transmission terminal. The ZQ flag signal indicates that the current chip has been calibrated using the calibration resistor. The address transmitter sends an address signal through the second transmission terminal, the address signal representing the address of the slave chip to be ZQ calibrated; The second signal receiver is used to match the address signal and receive the ZQ flag signal through the first transmission terminal. The slave chip that matches the address signal starts calibration based on the ZQ flag signal. After the slave chip completes calibration, it sends the ZQ flag signal through the first transmission terminal. The address transmitter continues to send the next address signal through the second transmission terminal until the calibration of all the slave chips is completed.

2. The memory device according to claim 1, characterized in that, The address transmitter includes: Address storage unit, used to store the address signals of all the slave chips; The address sending unit, connected to the address storage unit, is configured to sequentially send the address signals of the slave chip.

3. The memory device according to claim 2, characterized in that, The address transmitter also includes: The address sorting unit, connected to the address storage unit and the address sending unit, is configured to sort all the address signals; the address sending unit sends the sorted address signals sequentially.

4. The memory device according to any one of claims 1 to 3, characterized in that, The address transmitter responds to the ZQ flag signal by sequentially sending the address signals of the slave chip.

5. The memory device according to any one of claims 1 to 3, characterized in that, After the last slave chip completes ZQ calibration and releases the ZQ flag signal, the master chip is also used to send a flag signal to indicate that all chips have completed ZQ calibration.

6. The memory device according to claim 1, characterized in that, include: The first signal receiver includes: The first AND gate has one input terminal for receiving the ZQ calibration command and another input terminal for receiving a command indication signal, which is used to indicate that the memory is working in command mode. The second AND gate has one input terminal for receiving a clock signal or a power-on signal, and the other input terminal for receiving a background indication signal, which indicates that the memory is working in background mode. A first input selector has a first input terminal connected to the output terminal of a first AND gate, and a second input terminal connected to the input terminal of a second AND gate. The first selector terminal is used to receive the command indication signal or the background indication signal, and the first output terminal is used to output a first internal calibration signal, which is used to instruct the main chip to perform calibration. The first input selector is configured to connect the first input terminal to the first output terminal based on the command indication signal, or to connect the second input terminal to the first output terminal based on the background indication signal. The second signal receiver includes: The judgment unit is used to receive the address signal transmitted by the second transmission terminal and obtain the address signal of the slave chip to which it belongs. If the address signal transmitted by the second transmission terminal is the same as the address signal of the slave chip to which it belongs, then a first indication signal is sent. The third AND gate has one input terminal for receiving the ZQ flag signal, another input terminal for receiving the first indication signal, and an output terminal for outputting a second internal calibration signal, which is used to instruct the slave chip to perform calibration.

7. The memory device according to claim 6, characterized in that, include: The main chip further includes the second signal receiver, and the slave chip further includes the first signal receiver; The master chip and the slave chip further include: a second input selector, a third input terminal connected to the first output terminal, a fourth input terminal connected to the output terminal of the third AND gate, the second selector terminal being used to receive a second indication signal or a third indication signal, the second indication signal being used to indicate that the current chip is the master chip, the third indication signal being used to indicate that the current chip is the slave chip, and a second output terminal being used to output the first internal calibration signal and the second internal calibration signal; wherein, the second input selector is configured to connect the third input terminal to the second output terminal based on the second indication signal, or to connect the fourth input terminal to the second output terminal based on the third indication signal.

8. The memory device according to claim 1, characterized in that, The master chip and the slave chip are packaged in the same memory device.

9. The memory device according to claim 1, characterized in that, The main chip and some of the slave chips are packaged in different memory devices, wherein the connection between the first transmission terminals packaged in the different memory devices and the connection between the second transmission terminals are set through wired or wireless interconnection between the memory devices.

10. The memory device according to claim 1, characterized in that, The number of slave chips is the same as the number of binary data contained in the address signal.

11. A ZQ calibration method, applied to the memory device according to any one of claims 1 to 10, characterized in that, include: In command mode, acquire the ZQ calibration command applied externally to the memory device; or in background mode, acquire the clock signal or power-on signal applied externally to the memory device. In response to the ZQ calibration command, the clock signal, or the power-on signal, a first calibration operation is performed on the main chip; After the first calibration operation is completed, the ZQ flag signal and the address signal are sent, and the second calibration operation is performed on the main chip at the same time. The slave chip that conforms to the address signal responds to the ZQ flag signal and performs a first calibration operation; After the first calibration operation of the slave chip is completed, the ZQ flag signal is sent, and the second calibration operation is performed on the slave chip at the same time; The master chip resends the address signal, and the slave chip that satisfies the address signal performs the first calibration operation in response to the ZQ flag signal, until all slave chips have completed the first calibration operation; The second calibration operation is performed on the last chip that has completed the first calibration operation.

12. The ZQ calibration method according to claim 11, characterized in that, The main chip sends the address signal in response to the ZQ flag signal.

13. The ZQ calibration method according to claim 11, characterized in that, The main chip sends the sorted address signals sequentially based on the order of all the address signals.

14. The ZQ calibration method according to claim 11, characterized in that, The method of retransmitting the address signal by the main chip further includes: after the main chip has completed the transmission of all the address signals, the main chip sends a flag signal, which is used to indicate that all chips have completed ZQ calibration.

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