Memory device and zq calibration method

Abstract

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, comprising: two calibration resistance interfaces connected with the same ZQ calibration resistance; a first master chip, a first slave chip, a second master chip and a second slave chip commonly connected to the ZQ calibration resistance; in the command mode, a first signal receiver is used for receiving a ZQ calibration command, a second signal receiver is used for receiving and delaying the ZQ calibration command, the first master chip and the second master chip start calibration based on the ZQ calibration command, and the first master chip and the second master chip send a ZQ flag signal through a second transmission end after completing the calibration; a third signal receiver is used for receiving the ZQ flag signal through a first transmission end, the first slave chip and the second slave chip start calibration based on the ZQ flag signal, and the first slave chip and the second slave chip send the ZQ flag signal through the second transmission end after completing the calibration, and the embodiment of the present disclosure is used for realizing theoretically unlimited number of multi-chip sharing ZQ calibration resistance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a memory device and a ZQ calibration method. Background Technology

[0002] ZQ calibration is a very important function in Dynamic Random Access Memory (DRAM). Specifically, it relates to whether the output impedance of the output port is accurate and whether the termination resistor of the input port is accurate. Deviations in these parameters can cause severe distortion of the signal during transmission due to impedance mismatch. Moreover, the higher the signal frequency, the greater the impact of distortion on the signal.

[0003] JEDEC's packaging definition specifies the number of ZQ calibration resistors required for LPDDR5. For example, DIS315 chips have one ZQ calibration resistor, while POP496 chips have two ZQ calibration resistors. It is evident that the number of ZQ calibration resistors in LPDDR5 is significantly less than that in LPDDR4.

[0004] As the demand for LPDDR capacity increases, more and more chips are being placed in a single LPDDR package. Each chip requires individual ZQ calibration due to its unique characteristics. In particular, the number of ZQ calibration resistors in LPDDR5 packages is significantly reduced compared to LPDDR4, requiring more chips to share a single ZQ. How to achieve ZQ calibration by sharing ZQ calibration resistors among multiple chips is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides a memory device and a ZQ calibration method. By designing a new control circuit, a theoretically unlimited number of chips can share a ZQ calibration resistor.

[0006] This disclosure provides a memory device, including: two calibration resistor interfaces connected to the same ZQ calibration resistor; a first master chip, multiple cascaded first slave chips, a second master chip, and multiple cascaded second slave chips all connected to the ZQ calibration resistor; the first master chip, the first slave chip, the second master chip, and the second slave chip are each provided with a first transmission terminal and a second transmission terminal, which are used to transmit a ZQ flag signal; wherein, the second transmission terminal of the first master chip is connected to the first transmission terminal of the first-level first slave chip, the second transmission terminal of each level of the first slave chip is connected to the first transmission terminal of the next level of the first slave chip, the second transmission terminal of the second master chip is connected to the first transmission terminal of the first-level second slave chip, and the second transmission terminal of each level of the second slave chip is connected to the first transmission terminal of the next level of the second slave chip; the first master chip is provided with a first signal interface. The receiver includes a second signal receiver in the second master chip and a third signal receiver in the first and second slave chips. In command mode, the first signal receiver receives the ZQ calibration command provided by the memory via the ZQ signal terminal, and the second signal receiver receives and delays the ZQ calibration command via the ZQ signal terminal. The first and second master chips begin calibration based on the ZQ calibration command. After completing calibration, the first and second master chips send a ZQ flag signal via the second transmission terminal. The ZQ flag signal indicates that the current chip has been calibrated using the calibration resistor. The third signal receiver receives the ZQ flag signal via the first transmission terminal. The first and second slave chips begin calibration based on the ZQ flag signal. After completing calibration, the first and second slave chips send a ZQ flag signal via the second transmission terminal until all first or second slave chips have completed calibration.

[0007] Multiple chips calibrated via the first calibration interface are configured as a first master chip and multiple first slave chips; multiple chips calibrated via the second calibration interface are configured as a second master chip and multiple second slave chips; the first master chip performs ZQ calibration using a calibration resistor based on the ZQ calibration command provided by the memory, and the second master chip performs ZQ calibration using a calibration resistor after a delay based on the ZQ calibration command provided by the memory. After the first and second master chips have finished performing ZQ calibration using the calibration resistor, they send a ZQ flag signal to the cascaded first and second slave chips. The cascaded first and second slave chips then sequentially perform ZQ calibration using the ZQ calibration resistor based on the ZQ flag signal, thereby achieving theoretically unlimited number of chips sharing the ZQ calibration resistor for ZQ calibration.

[0008] Additionally, the second transmission terminal of the last-stage first slave chip is connected to the first transmission terminal of the first master chip; the second transmission terminal of the last-stage second slave chip is connected to the first transmission terminal of the second master chip. When the first master chip receives the ZQ flag signal, it proves that all first slave chips have completed ZQ calibration; when the second master chip receives the ZQ flag signal, it proves that all second slave chips have completed ZQ calibration, and the memory can proceed to the next operation.

[0009] In addition, the second master chip also includes a third transmission terminal, which is enabled in background mode to receive the ZQ flag signal. The third transmission terminal is connected to the second transmission terminal of the last-stage first slave chip. In background mode, the first signal receiver is used to receive the clock signal or power-on signal provided by the memory through the ZQ signal terminal. The first master chip starts calibration based on the clock signal or power-on signal. After the first master chip completes calibration, it sends the ZQ flag signal through the second transmission terminal. The first slave chip, the second master chip, and the second slave chip start calibration sequentially based on the ZQ flag signal.

[0010] In addition, the first master chip also includes a fourth transmission terminal, which is enabled in background mode and used to transmit the ZQ flag signal. The fourth transmission terminal is connected to the second transmission terminal of the last-stage second slave chip. When the first master chip receives the ZQ flag signal, it proves that all slave chips have completed ZQ calibration in background mode, and the memory can proceed to the next operation.

[0011] Additionally, the first signal receiver includes: a first AND gate, one input for receiving a ZQ calibration command and the other input for receiving a command indication signal, the command indication signal being used to characterize that the memory is operating in command mode; a second AND gate, one input for receiving a clock signal or a power-on signal and the other input for receiving a background indication signal, the background indication signal being used to characterize that the memory is operating in background mode; a first input selector, the first input being connected to the output of the first AND gate and the second input being connected to the output of the second AND gate, the first selector being used to receive the command indication signal or the background indication signal, and the first output being used to output a first internal calibration signal, the first internal calibration signal being used to instruct the first main chip and the second main chip to perform calibration; wherein, the first input selector is configured to connect the first input to the first output based on the command indication signal, or connect the second input to the first output based on the background indication signal; the second signal receiver includes: a third AND gate, one input for receiving a clock signal or a power-on signal and the other input for receiving a background indication signal; ... receive a clock signal or a power-on signal and the other input for receiving a background indication signal; the second signal receiver includes: a third AND gate, one input for receiving a clock signal or a power-on signal and the other input for receiving a background indication signal; the first input selector is configured to receive a clock signal or a power-on signal and the other input for receiving a clock signal or a power-on signal and the other input for receiving a clock signal; the second signal receiver includes: a third AND gate, one input for receiving a clock signal or a third input for receiving a clock signal or a third input for receiving a clock signal; the second input selector is configured to receive a clock signal or a third input for receiving a clock signal; the second signal receiver includes: a third The system includes: a ZQ calibration command received and delayed, with another input for receiving a command indication signal; a fourth AND gate, with one input for receiving a ZQ flag signal and another input for receiving a background indication signal; a second input selector, with a third input connected to the output of the third AND gate and a fourth input connected to the output of the fourth AND gate, the second selector being used to receive either the command indication signal or the background indication signal, and the second output being used to output a first internal calibration signal; wherein the second input selector is configured to connect the third input to the second output based on the command indication signal, or to connect the fourth input to the second output based on the background indication signal; and a third signal receiver, including: a fifth AND gate, with one input for receiving the ZQ flag signal and another input for receiving a first indication signal, the first indication signal being used to characterize whether the current chip is a first slave chip or a second slave chip, and the output being used to output a second internal calibration signal, the second internal calibration signal being used to instruct the first slave chip or the second slave chip to perform calibration.

[0012] Additionally, the first signal receiver and the second signal receiver include: a first selector, with one input terminal for receiving a ZQ calibration command, another input terminal for receiving a delayed ZQ calibration command, and a selection terminal for receiving a first main chip identifier signal or a second main chip identifier signal; the first selector is configured to output a ZQ calibration command based on the first main chip identifier signal, or output a delayed ZQ calibration command based on the second main chip identifier signal; a first AND gate, with one input terminal connected to the output terminal of the first selector, and another input terminal for receiving a command indication signal, the command indication signal being used to characterize that the memory is operating in command mode; a second selector, with one input terminal for receiving a clock signal or a power-on signal, another input terminal for receiving a ZQ flag signal transmitted through a third transmission terminal, and a selection terminal for receiving the first main chip identifier signal or the second main chip identifier signal; the second selector is configured to output a clock signal or a power-on signal based on the first main chip identifier signal, or output a ZQ flag signal based on the second main chip identifier signal; a second AND gate, with one input terminal connected to the output terminal of the first selector, and another input terminal for receiving a ZQ flag signal transmitted through a third transmission terminal, and a selection terminal for receiving a first main chip identifier signal or a second main chip identifier signal; the second selector is configured to output a clock signal or a power-on signal based on the first main chip identifier signal, or output a ZQ flag signal based on the second main chip identifier signal; a second AND gate, with one input terminal connected to the output terminal of the first selector, and another input terminal for receiving a first main chip identifier signal or a second main chip identifier signal; and ... An input terminal is connected to the output terminal of a second selector, and another input terminal is used to receive a background indication signal, which indicates that the memory is working in background mode; a first input selector has a first input terminal connected to the output terminal of a first AND gate, and a second input terminal connected to the output terminal of a second AND gate. The first selection terminal is used to receive a command indication signal or a background indication signal, and the first output terminal is used to output a first internal calibration signal, which instructs the first master chip and the second master chip to perform calibration; wherein, the first input selector is configured to connect the first input terminal to the first output terminal based on the command indication signal, or to connect the second input terminal to the first output terminal based on the background indication signal; a third signal receiver includes: a fifth AND gate, one input terminal for receiving a ZQ flag signal, and another input terminal for receiving a first indication signal, which indicates that the current chip is a first slave chip or a second slave chip, and an output terminal for outputting a second internal calibration signal, which instructs the first slave chip and the second slave chip to perform calibration.

[0013] In addition, the first master chip and the second master chip also include a third signal receiver, and the slave chip also includes a first signal receiver and / or a second signal receiver; the first master chip, the first slave chip, the second master chip and the second slave chip also include: a third input selector, a fifth input terminal for receiving a first internal calibration command, a sixth input terminal for receiving a second internal calibration command, a third selection terminal for receiving a first indication signal or a second indication signal, the second indication signal being used to characterize the current chip as the first master chip or the second master chip, and a third output terminal for outputting the first internal calibration command and the second internal calibration command; wherein, the third input selector is configured to connect the sixth input terminal to the third output terminal based on the first indication signal, or to connect the fifth input terminal to the third output terminal based on the second indication signal.

[0014] In addition, the first master chip, the first slave chip, the second master chip, and the second slave chip are packaged in the same memory device.

[0015] In addition, the first master chip and the first slave chip are packaged in different memory devices; the second master chip and the second slave chip are packaged in different memory devices; wherein, the connection between the first transmission end and the second transmission end packaged in different memory devices is set by wired or wireless interconnection between memory devices.

[0016] In addition, the number of second slave chips equals the number of first slave chips; the first master chip and the first slave chip are arranged in a first array of 1 column and N rows, and the first master chip is located at the Nth row; the second master chip and the second slave chip are arranged in a second array of 1 column and N rows, and the first master chip is located at the N / 2th row; N-1 is the number of first slave chips.

[0017] This disclosure also provides a ZQ calibration method applied to the memory device provided in the above embodiments, comprising: in command mode, acquiring a ZQ calibration command applied externally to the memory device; in response to the ZQ calibration command, performing a first calibration operation on a first master chip; after the first calibration operation is completed, transmitting a ZQ flag signal to a first-level first slave chip, and simultaneously performing a second calibration operation on the first master chip; in response to the ZQ flag signal, performing a first calibration operation on a first-level first slave chip; after the first calibration operation on the first-level first slave chip is completed, transmitting the ZQ flag signal to the next-level first slave chip, and simultaneously performing a second calibration operation on the first-level first slave chip, until the last-level first slave chip... The chip completes the first calibration operation; the second calibration operation is completed for the last-stage first slave chip; in response to the delayed ZQ calibration command, the first calibration operation is performed on the second master chip; after the first calibration operation is completed, the ZQ flag signal is transmitted to the first-stage second slave chip, and the second calibration operation is performed on the second master chip; in response to the ZQ flag signal, the first calibration operation is performed on the first-stage second slave chip; after the first calibration operation of the first-stage second slave chip is completed, the ZQ flag signal is transmitted to the next-stage second slave chip, and the second calibration operation is performed on the first-stage second slave chip, until the last-stage second slave chip completes the first calibration operation; the second calibration operation is completed on the last-stage second slave chip.

[0018] In addition, while performing the second calibration operation on the last-stage first slave chip, the process also includes transmitting the ZQ flag signal to the first master chip; while performing the second calibration operation on the last-stage second slave chip, the process also includes transmitting the ZQ flag signal to the second master chip.

[0019] In addition, in background mode, in response to the ZQ calibration command, a first calibration operation is performed on the first master chip; after the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level first slave chip, and a second calibration operation is performed on the first master chip; in response to the ZQ flag signal, a first calibration operation is performed on the first-level first slave chip; after the first calibration operation of the first-level first slave chip is completed, the ZQ flag signal is transmitted to the next-level first slave chip, and a second calibration operation is performed on the first-level first slave chip, until the last-level first slave chip completes its first calibration operation; the ZQ flag signal is transmitted to the second master chip, and a second calibration operation is performed on the last-level first slave chip. The first slave chip performs a second calibration operation; in response to the ZQ flag signal, it performs a first calibration operation on the second master chip; after the first calibration operation is completed, it transmits the ZQ flag signal to the first-level second slave chip, and simultaneously performs a second calibration operation on the second master chip; in response to the ZQ flag signal, it performs a first calibration operation on the first-level second slave chip; after the first calibration operation of the first-level second slave chip is completed, it transmits the ZQ flag signal to the next-level second slave chip, and simultaneously performs a second calibration operation on the first-level second slave chip, until the last-level second slave chip completes the first calibration operation; and finally, it completes the second calibration operation on the last-level second slave chip.

[0020] In addition, in background mode, while performing the second calibration operation on the last-stage second slave chip, it also includes transmitting the ZQ flag signal to the first master chip.

[0021] In addition, the first calibration operation is one of the pull-up calibration operation that generates the pull-up calibration code and the pull-down calibration operation that generates the pull-down calibration code, and the second calibration operation is the other of the pull-up calibration operation and the pull-down calibration operation. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram showing two calibration resistor interfaces connected to the same ZQ calibration resistor according to an embodiment of the present disclosure;

[0024] Figures 2-5 This is a schematic diagram of the structure of a memory device with different connection methods according to an embodiment of the present disclosure;

[0025] Figure 6 This is a schematic diagram of the structure of a first signal receiver provided in an embodiment of the present disclosure;

[0026] Figure 7 This is a schematic diagram of the structure of a second signal receiver provided in an embodiment of the present disclosure;

[0027] Figure 8 This is a schematic diagram of the structure of a third signal receiver provided in an embodiment of the present disclosure;

[0028] Figure 9 A schematic diagram of a structure in which the first signal receiver and the second signal receiver have the same structure, according to an embodiment of this disclosure;

[0029] Figure 10 This is a schematic diagram of the structure of a first signal receiver and a third signal receiver integrated according to an embodiment of the present disclosure;

[0030] Figure 11 Timing and schematic diagram of a ZQ calibration method for a memory device in command mode, provided in another embodiment of this disclosure;

[0031] Figure 12 The timing diagram and schematic diagram are provided for a ZQ calibration method for a memory device in background mode, according to another embodiment of this disclosure. Detailed Implementation

[0032] As the background technology shows, with the increasing demand for LPDDR capacity, more and more chips are put into one LPDDR package. Each chip needs to be individually calibrated due to individual differences. In particular, the number of ZQ calibration resistors in LPDDR5 packages is significantly reduced compared to the number of ZQ calibration resistors in LPDDR4, requiring more chips to share a single ZQ.

[0033] One embodiment of this disclosure provides a memory device that, through the design of a novel control circuit, enables theoretically unlimited numbers of chips to share a ZQ calibration resistor.

[0034] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0035] Figure 1 This is a schematic diagram showing the two calibration resistor interfaces connected to the same ZQ calibration resistor in this embodiment. Figures 2-5 This is a schematic diagram of the structure of the memory device under different connection methods provided in this embodiment. Figure 6 This is a schematic diagram of the structure of the first signal receiver provided in this embodiment. Figure 7 This is a schematic diagram of the structure of the second signal receiver provided in this embodiment. Figure 8 This is a schematic diagram of the structure of the third signal receiver provided in this embodiment. Figure 9 This is a schematic diagram of the structure when the first signal receiver and the second signal receiver provided in this embodiment have the same structure. Figure 10 This is a schematic diagram of the integrated structure of the first and third signal receivers provided in this embodiment. The structure of the memory device provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0036] Memory devices, including:

[0037] There are two calibration resistor interfaces, and both calibration resistor interfaces are connected to the same ZQ calibration resistor.

[0038] refer to Figure 1 The memory device is an LPDDR5 memory device 10, which includes: a first calibration resistor interface, a second calibration resistor interface, a first calibration command interface, and a second calibration command interface. The calibration command received by the first calibration command interface is calibrated through the calibration resistor connected to the first calibration resistor interface, and the calibration command received by the second calibration command interface is calibrated through the calibration resistor connected to the second calibration resistor interface. In this embodiment, the first and second calibration resistor interfaces are both connected to the same ZQ calibration resistor Rzq. Accordingly, the first and second calibration command interfaces perform calibration based on the ZQ calibration command through the ZQ calibration resistor Rzq.

[0039] refer to Figures 2-5 The memory device also includes: a first master chip commonly connected to the ZQ calibration resistor, multiple cascaded first slave chips, a second master chip, and multiple cascaded second slave chips.

[0040] The first master chip, the first slave chip, the second master chip, and the second slave chip are provided with a first transmission terminal A and a second transmission terminal B, wherein the first transmission terminal A and the second transmission terminal B are used to transmit the ZQ flag signal.

[0041] It should be noted that the "cascading" mentioned above refers to: multiple first slave chips respectively serving as first-level first slave chips, second-level first slave chips, ..., M-1-level first slave chips and M-level first slave chips connected end-to-end; and multiple second slave chips respectively serving as first-level second slave chips, second-level second slave chips, ..., K-1-level second slave chips and K-level second slave chips connected end-to-end. Specifically, the second transmission terminal B of the first master chip is connected to the first transmission terminal A of the first-level first slave chip, and the second transmission terminal B of each first slave chip is connected to the first transmission terminal A of the next-level first slave chip; similarly, the second transmission terminal B of the second master chip is connected to the first transmission terminal A of the first-level second slave chip, and the second transmission terminal B of each second slave chip is connected to the first transmission terminal A of the next-level second slave chip.

[0042] The first main chip is equipped with a first signal receiver, the second main chip is equipped with a second signal receiver, and the first slave chip and the second slave chip are equipped with a third signal receiver.

[0043] Specifically, in command mode, the first signal receiver is used to receive the ZQ calibration command provided by the memory through the ZQ signal terminal, the second signal receiver is used to receive and delay the ZQ calibration command through the ZQ signal terminal, the first master chip and the second slave chip start calibration based on the ZQ calibration command, and after the first master chip and the second master chip complete calibration, they send a ZQ flag signal through the second transmission terminal B. The ZQ flag signal indicates that the current chip has been calibrated using the calibration resistor; the third signal receiver is used to receive the ZQ flag signal through the first transmission terminal A, the first slave chip and the second slave chip start calibration based on the ZQ flag signal, and after the first slave chip and the second slave chip complete calibration, they send a ZQ flag signal through the second transmission terminal B, until all first slave chips or second slave chips have completed calibration.

[0044] In the memory device provided in this embodiment, multiple chips calibrated through the first calibration interface are configured as a first master chip and multiple first slave chips; multiple chips calibrated through the second calibration interface are configured as a second master chip and multiple second slave chips; the first master chip performs ZQ calibration using a calibration resistor based on the ZQ calibration command provided by the memory, and the second master chip performs ZQ calibration using a calibration resistor after a certain delay based on the ZQ calibration command provided by the memory. After the first master chip and the second master chip have finished performing ZQ calibration using the calibration resistor, they send a ZQ flag signal to the cascaded first slave chip and the second slave chip. The cascaded first slave chip and the second slave chip then sequentially perform ZQ calibration using the ZQ calibration resistor based on the ZQ flag signal, thereby realizing theoretically unlimited number of chips sharing the ZQ calibration resistor for ZQ calibration.

[0045] It should be noted that, regarding the aforementioned "delay," in some embodiments, the delay is half a calibration cycle. That is, in the first half of the calibration cycle, the first master chip and the first slave chip are calibrated based on the ZQ calibration resistor, and in the second half of the calibration cycle, the second master chip and the second slave chip are calibrated based on the ZQ calibration resistor. The specific "delay" can be limited according to the number of chips, where the number of chips includes the number of chipsets and the total number of master chips and slave chips in the same chipset. This embodiment does not constitute a limitation on the specific delay time.

[0046] for Figures 2-5 The first master chip, first slave chip, second master chip, and second slave chip shown are used to reset the chip according to the reset signal, to select the target chip for enable according to the strobe signal, and to complete data writing or reading according to the clock signal and data signal; it should be noted that... Figures 2-5 The reset signal, data signal, clock signal, and strobe signal shown are used to illustrate the operation of the first master chip, the first slave chip, the second master chip, and the second slave chip, and do not constitute a limitation on the structure of the memory device.

[0047] refer to Figures 2-5 In some embodiments, the second transmission terminal B of the last-stage first slave chip is connected to the first transmission terminal A of the first master chip; the second transmission terminal B of the last-stage second slave chip is connected to the first transmission terminal A of the second master chip. When the first master chip receives the ZQ flag signal, it proves that all first slave chips have completed ZQ calibration; when the second master chip receives the ZQ flag signal, it proves that all second slave chips have completed ZQ calibration, and the memory can proceed to the next operation.

[0048] refer to Figure 4 and Figure 5 In some embodiments, the second main chip further includes a third transmission terminal C, which is enabled in background mode and is used to receive the ZQ flag signal. Specifically, the third transmission terminal C is used to receive the ZQ flag signal sent by the last-stage first slave chip. In background mode, the second main chip starts calibration based on the ZQ flag signal.

[0049] In background mode, the first signal receiver receives the clock signal or power-on signal provided by the memory through the ZQ signal terminal. The first master chip starts calibration based on the clock signal or power-on signal. After completing calibration, the first master chip sends the ZQ flag signal through the second transmission terminal. The first slave chip, the second master chip, and the second slave chip start calibration sequentially based on the ZQ flag signal. Specifically, after the first master chip completes ZQ calibration, it sends the ZQ flag signal to the first-level first slave chip through the second transmission terminal B. The ZQ flag signal sent by the last-level first slave chip after completing ZQ calibration is received by the second master chip through the third transmission terminal C. The second master chip performs calibration based on the ZQ flag signal. After completing ZQ calibration, the second master chip sends the ZQ flag signal to the first-level second slave chip through the second transmission terminal B, until the last-level second slave chip completes ZQ calibration.

[0050] In some embodiments, the first master chip further includes a fourth transmission terminal D, which is enabled in background mode and used to transmit a ZQ flag signal. The fourth transmission terminal is connected to the second transmission terminal B of the last-stage second slave chip. When the first master chip receives the ZQ flag signal, it proves that all slave chips have completed ZQ calibration in background mode, and the memory can proceed to the next operation. It should be noted that in command mode, the first master chip receives the ZQ flag signal sent by the last-stage first slave chip through the first transmission terminal; in background mode, the first master chip receives the ZQ flag signal sent by the last-stage second slave chip through the fourth transmission terminal.

[0051] In some embodiments, reference Figure 2 , Figure 4 and combined Figure 6 The first signal receiver 100 includes: a first AND gate 101, one input for receiving a ZQ calibration command and the other input for receiving a command indication signal, the command indication signal being used to indicate that the memory is operating in command mode; a second AND gate 102, one input for receiving a clock signal or a power-on signal and the other input for receiving a background indication signal, the background indication signal being used to indicate that the memory is operating in background mode; and a first input selector 103, the first input of which is connected to the output of the first AND gate 101 and the second input of which is connected to the output of the second AND gate 102, the first selector being used to receive the command indication signal or the background indication signal, and the first output being used to output a first internal calibration signal, the first internal calibration signal being used to instruct the first main chip and the second main chip to perform calibration; wherein, the first input selector 103 is configured to connect the first input to the first output based on the command indication signal, or to connect the second input to the first output based on the background indication signal.

[0052] It should be noted that, regarding the command mode and background mode mentioned in this embodiment, the memory is started based on a preset command in command mode, and the memory is started based on its internal signals in background mode. The internal signals include the power-on signal and the clock signal.

[0053] Specifically, refer to Figure 2 and combined Figure 6 When the memory is in command mode, it provides a command indication signal to the first signal receiver 100 of the first main chip. The first input selector 103 connects the first input terminal to the first output terminal based on the command indication signal. At this time, the first signal receiver 100 provides a first internal calibration signal based on the output of the first AND gate 101. That is, when the first signal receiver 100 receives the ZQ calibration command, it generates the first internal calibration signal, thereby controlling the first main chip to perform ZQ calibration. Figure 4 and combined Figure 6 When the memory is in background mode, a background indication signal is provided to the first signal receiver 100 of the first main chip. The first input selector 103 connects the second input terminal to the first output terminal based on the background indication signal. At this time, the first signal receiver 100 provides a first internal calibration signal based on the output of the second AND gate 102. That is, when the first signal receiver 100 receives a clock signal or a power-on signal, it generates the first internal calibration signal, thereby controlling the first main chip to perform ZQ calibration.

[0054] In some embodiments, reference Figure 2 , Figure 4 and combined Figure 7 The second signal receiver 200 includes: a third AND gate 203, one input for receiving and delaying a ZQ calibration command, and another input for receiving a command indication signal; a fourth AND gate 204, one input for receiving a ZQ flag signal, and another input for receiving a background indication signal; and a second input selector 205, the third input connected to the output of the third AND gate 203, the fourth input connected to the output of the fourth AND gate 204, the second selector for receiving either the command indication signal or the background indication signal, and the second output for outputting a first internal calibration signal; wherein the second input selector 205 is configured to connect the third input to the second output based on the command indication signal, or to connect the fourth input to the second output based on the background indication signal.

[0055] refer to Figure 7 In some embodiments, the memory device further includes a delay unit 201 for delaying the ZQ calibration signal received by the second signal receiver 200.

[0056] Specifically, refer to Figure 2 and combined Figure 7When the memory is in command mode, it provides a command indication signal to the second signal receiver 200 of the second main chip. The second input selector 205 connects the third input terminal to the second output terminal based on the command indication signal. At this time, the second signal receiver 200 provides a first internal calibration signal based on the output of the third AND gate 203. That is, when the second signal receiver 200 receives a delayed ZQ calibration command, it generates the first internal calibration signal, thereby controlling the second main chip to perform ZQ calibration. (Reference) Figure 4 and combined Figure 7 When the memory is in background mode, a background indication signal is provided to the second signal receiver 200 of the second main chip. The second input selector 205 connects the fourth input terminal to the second output terminal based on the background indication signal. At this time, the second signal receiver 200 provides a first internal calibration signal based on the output of the fourth AND gate 204. That is, when the second signal receiver 200 receives the ZQ flag signal, it generates the first internal calibration signal, thereby controlling the second main chip to perform ZQ calibration.

[0057] In some embodiments, reference Figure 8 The third signal receiver 300 includes: a fifth AND gate 305, one input terminal for receiving the ZQ flag signal, another input terminal for receiving the first indication signal, the first indication signal for indicating that the current chip is a slave chip, and an output terminal for outputting a second internal calibration signal, the second internal calibration signal for instructing the first slave chip and the second slave chip to perform calibration.

[0058] Specifically, the third signal receiver 300 is disposed in the first slave chip and the second slave chip. The third signal receiver 300 continuously receives the first indication signal so that when the third signal receiver 300 receives the ZQ flag signal, it can generate a second internal calibration signal, thereby controlling the first slave chip and the second slave chip to perform ZQ calibration.

[0059] In some embodiments, the first signal receiver 100 and the second signal receiver 200 have the same structure, that is, the receivers in the first main chip and the second main chip have the same structure. (Refer to...) Figure 9The first signal receiver 100 and the second signal receiver 200 include: a first selector 401, with one input terminal for receiving a ZQ calibration command, another input terminal for receiving a delayed ZQ calibration command, and a selection terminal for receiving a first main chip identifier signal or a second main chip identifier signal; the first selector 401 is configured to output a ZQ calibration command based on the first main chip identifier signal, or output a delayed ZQ calibration command based on the second main chip identifier signal; a first AND gate 101, with one input terminal connected to the output terminal of the first selector 401, and another input terminal for receiving a command indication signal, the command indication signal being used to characterize that the memory is operating in command mode; a second selector 402, with one input terminal for receiving a clock signal or a power-on signal, another input terminal for receiving a ZQ flag signal transmitted by a third transmission terminal, and a selection terminal for receiving the first main chip identifier signal or the second main chip identifier signal; the second selector... Device 402 is configured to output a clock signal or a power-on signal based on a first main chip identification signal, or to output a ZQ flag signal based on a second main chip identification signal; second AND gate 102 has one input connected to the output of second selector 402, and the other input used to receive a background indication signal, which indicates that the memory is working in background mode; first input selector 103 has a first input connected to the output of first AND gate 101, and a second input connected to the output of second AND gate 102, the first selection terminal used to receive a command indication signal or a background indication signal, and the first output terminal used to output a first internal calibration signal, which instructs the first main chip and the second main chip to perform calibration; wherein, first input selector 103 is configured to connect the first input terminal to the first output terminal based on the command indication signal, or connect the second input terminal to the first output terminal based on the background indication signal.

[0060] Specifically, if the first signal receiver 100 receives the first main chip identification signal, and is selected to be turned on by the first selector 401 and the second selector 402, the circuit principle of the first signal receiver 100 is the same as... Figure 6 The same applies; if the first signal receiver 100 receives the second main chip identification signal, and is selected to be turned on by the first selector 401 and the second selector 402, the circuit principle of the first signal receiver 100 is the same as... Figure 7 same.

[0061] In some embodiments, the ZQ calibration command is delayed by the delay unit 201, which may consist of an even number of inverters. This disclosure does not limit the structure of the delay unit 201.

[0062] Figure 2 and Figure 4In the memory device structure shown, only the first master chip and the second master chip receive the ZQ calibration command, and the structures of the first master chip, the first slave chip, the second master chip, and the second slave chip differ; Reference Figure 3 and Figure 5 In some embodiments, the first master chip, the first slave chip, the second master chip, and the second slave chip have the same structure. In this case, the first slave chip and the second slave chip also need to receive ZQ calibration commands. The first master chip and the second master chip also include a third signal receiver 300, and the first slave chip and the second slave chip also include a first signal receiver 100 and / or a second signal receiver 200.

[0063] refer to Figure 10 The first master chip, the first slave chip, the second master chip, and the second slave chip further include: a third input selector 403, a fifth input terminal for receiving a first internal calibration signal, a sixth input terminal for receiving a second internal calibration signal, a third selection terminal for receiving a first indication signal or a second indication signal, the second indication signal being used to indicate that the current chip is the first master chip or the second master chip, and a third output terminal for outputting a first internal calibration command or a second internal calibration command; wherein, the third input selector 403 is configured to connect the sixth input terminal to the third output terminal based on the first indication signal, or to connect the fifth input terminal to the third output terminal based on the second indication signal.

[0064] Specifically, the third input selector 403 selects the output based on the first indication signal and the second indication signal. When the second indication signal is received, it indicates that the current chip is the first master chip or the second master chip, and the third input selector 403 selects the output signal of the first signal receiver 100 or the second signal receiver 200 for output. When the first indication signal is received, it indicates that the current chip is the first slave chip or the second slave chip, and the third input selector 403 selects the output signal of the third signal receiver 300 for output.

[0065] It should be noted that, Figure 10 The example is Figure 8 and Figure 9 In some embodiments, the combination performed by the third input selector 403... Figures 7-9 Alternatively, the third input selector 403 can be used to combine the first master chip, the second master chip, the first slave chip, and the second slave chip to achieve the same receiving structure.

[0066] refer to Figures 2-5In this embodiment, the number of first slave chips equals the number of second slave chips. The first master chip and the first slave chips are arranged in a first array with 1 column and N rows, and the first master chip is located at row N. The second master chip and the second slave chip are arranged in a second array with 1 column and N rows, and the second master chip is located at row N / 2. N-1 represents the number of first slave chips and the number of second slave chips. In other embodiments, the chips can be arranged in an array with i columns and j rows according to the number of chips and the layout area to be set. In this case, the first master chip is located at the array position in the first column and j-th row, and the second master chip is located at the array position in the array position in the i / 2+1 column and j / 2 row.

[0067] It is understood that the number of chips in the loop varies depending on the mode of the memory. In the embodiment shown in this disclosure, in command mode, the memory includes two calibration loops, and each calibration loop contains one master chip and N-1 slave chips. In background mode, the memory includes only one calibration loop, and the calibration loop contains two master chips and 2N-2 slave chips.

[0068] In some embodiments, the first master chip and the first slave chip are packaged in the same memory device, and the second master chip and the second slave chip are packaged in the same memory device; in some embodiments, the first master chip and the first slave chip are packaged in different memory devices, and the second master chip and the second slave chip are packaged in different memory devices, wherein the connection between the first transmission terminal A and the second transmission terminal B packaged in different memory devices is set through wired or wireless interconnection between memory devices.

[0069] In this embodiment, multiple chips calibrated through the first calibration interface are configured as one first master chip and multiple first slave chips; multiple chips calibrated through the second calibration interface are configured as one second master chip and multiple second slave chips. The first master chip performs ZQ calibration using a calibration resistor based on the ZQ calibration command provided by the memory. The second master chip performs ZQ calibration using a calibration resistor after a delay, based on the ZQ calibration command provided by the memory. After the first and second master chips have finished performing ZQ calibration using the calibration resistor, they send a ZQ flag signal to the cascaded first and second slave chips. The cascaded first and second slave chips then sequentially perform ZQ calibration using the ZQ calibration resistor based on the ZQ flag signal, thereby achieving theoretically unlimited number of chips sharing the ZQ calibration resistor for ZQ calibration.

[0070] It should be noted that in this embodiment, the flag bit is used to characterize whether the loop containing the main chip is in ZQ calibration state. Specifically, when the main chip receives a ZQ calibration command or receives a ZQ flag signal for the first time, the flag bit is in a first state; correspondingly, after the main chip, with the flag bit in the first state, receives the ZQ flag signal, the flag bit is in a second state. Furthermore, when there is a time limit for ZQ calibration, the number of chips sharing the ZQ calibration resistor is also limited; the longer the time required for each chip to perform ZQ calibration, the fewer chips share the ZQ calibration resistor. In addition, the features disclosed in the memory device provided in the above embodiments can be arbitrarily combined without conflict to obtain new memory device embodiments.

[0071] Another embodiment of this disclosure provides a ZQ calibration method applied to the memory device provided in the above embodiments, thereby enabling theoretically unlimited number of chips to share a ZQ calibration resistor for ZQ calibration.

[0072] Figure 11 This embodiment provides the timing diagram and schematic diagram corresponding to the ZQ calibration method for memory devices in command mode. Figure 12 The following is a timing diagram and schematic diagram of the ZQ calibration method provided in this embodiment for a memory device in background mode. The ZQ calibration method provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0073] refer to Figure 11 The ZQ calibration method includes: in command mode, acquiring a ZQ calibration command applied externally to the memory device; in response to the ZQ calibration command, performing a first calibration operation on the first master chip; after the first calibration operation is completed, transmitting a ZQ flag signal to the first-level slave chip, and simultaneously performing a second calibration operation on the first master chip; in response to the ZQ flag signal, performing a first calibration operation on the first-level slave chip; after the first calibration operation of the first-level slave chip is completed, transmitting the ZQ flag signal to the next-level slave chip, and simultaneously performing a second calibration operation on the first-level slave chip, until the last-level slave chip completes its first calibration operation, and then performing a second calibration operation on the last slave chip. The first slave chip completes the second calibration operation; in response to the delayed ZQ calibration command, the first calibration operation is performed on the second master chip. After the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level second slave chip, and the second calibration operation is performed on the second master chip. In response to the ZQ flag signal, the first calibration operation is performed on the first-level second slave chip. After the first calibration operation of the first-level second slave chip is completed, the ZQ flag signal is transmitted to the next-level second slave chip, and the second calibration operation is performed on the first-level second slave chip, until the last-level second slave chip completes the first calibration operation and the second calibration operation is performed on the last-level second slave chip.

[0074] It should be noted that, Figure 11 The ZQ calibration timing diagram shown uses a three-level slave chip as an example for illustration. It is only for those skilled in the art to understand the implementation of ZQ calibration in this embodiment and does not constitute a limitation of this embodiment. Figure 11 The illustration and the ZQ calibration method mentioned above can be used to... Figure 11 The timing is further derived to apply to the case of K first slave chips and second slave chips.

[0075] In some embodiments, while performing the second calibration operation on the last-stage first slave chip, the method further includes: transmitting a ZQ flag signal to the first master chip; while performing the second calibration operation on the last-stage second slave chip, the method further includes: transmitting a ZQ flag signal to the second master chip. When the first master chip receives the ZQ flag signal, it proves that all first slave chips have completed ZQ calibration; when the second master chip receives the ZQ flag signal, it proves that all second slave chips have completed ZQ calibration, and the memory can proceed to the next step. By transmitting the ZQ flag signal back to the master chip through the last-stage slave chip, it indicates that all chips have completed ZQ calibration, which facilitates the design of memory circuits and signal timing.

[0076] refer to Figure 12 The ZQ calibration method further includes: in background mode, in response to a ZQ calibration command, performing a first calibration operation on a first master chip; after the first calibration operation is completed, transmitting a ZQ flag signal to a first-level slave chip, while simultaneously performing a second calibration operation on the first master chip; in response to the ZQ flag signal, performing a first calibration operation on a first-level slave chip; after the first calibration operation on the first-level slave chip is completed, transmitting the ZQ flag signal to the next-level slave chip, while simultaneously performing a second calibration operation on the first-level slave chip, until the last-level slave chip completes its first calibration operation; transmitting the ZQ flag signal to a second master chip, while... A second calibration operation is performed on the last-stage first slave chip; in response to the ZQ flag signal, a first calibration operation is performed on the second master chip; after the first calibration operation is completed, the ZQ flag signal is transmitted to the first-stage second slave chip, and a second calibration operation is performed on the second master chip; in response to the ZQ flag signal, a first calibration operation is performed on the first-stage second slave chip; after the first calibration operation of the first-stage second slave chip is completed, the ZQ flag signal is transmitted to the next-stage second slave chip, and a second calibration operation is performed on the first-stage second slave chip, until the last-stage second slave chip completes the first calibration operation; the second calibration operation is completed on the last-stage second slave chip.

[0077] It should be noted that, Figure 12The ZQ calibration timing diagram shown uses a three-level slave chip as an example for illustration. It is only for those skilled in the art to understand the implementation of ZQ calibration in this embodiment and does not constitute a limitation of this embodiment. Figure 12 The illustration and the ZQ calibration method mentioned above can be used to... Figure 12 The timing is further derived to apply to the case of K first slave chips and second slave chips.

[0078] In some embodiments, in background mode, while performing the second calibration operation on the last-stage second slave chip, the process also includes transmitting a ZQ flag signal to the first master chip. When the first master chip receives the ZQ flag signal, it indicates that all chips have completed ZQ calibration, and the memory can proceed to the next step. The last-stage slave chip sends the ZQ flag signal back to the master chip to indicate that all chips have completed ZQ calibration, which facilitates the design of memory circuitry and signal timing.

[0079] It should be noted that, in this embodiment, the first calibration operation is one of the pull-up calibration operation that generates the pull-up calibration code and the pull-down calibration operation that generates the pull-down calibration code, and the second calibration operation is the other of the pull-up and pull-down calibration operations. The first calibration operation requires calibration using a calibration resistor, while the second calibration operation is based on the result of the first calibration operation and does not require a calibration resistor. Furthermore, the features disclosed in the ZQ calibration method provided in the above embodiments can be arbitrarily combined without conflict to obtain new ZQ calibration method embodiments.

[0080] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that, include: Two calibration resistor interfaces, and both calibration resistor interfaces are connected to the same ZQ calibration resistor; A first master chip, multiple cascaded first slave chips, a second master chip, and multiple cascaded second slave chips are all connected to the ZQ calibration resistor. The first master chip, the first slave chip, the second master chip, and the second slave chip are provided with a first transmission terminal and a second transmission terminal, which are used to transmit the ZQ flag signal. Wherein, the second transmission terminal of the first master chip is connected to the first transmission terminal of the first slave chip of the first level, the second transmission terminal of each first slave chip of the first level is connected to the first transmission terminal of the next first slave chip, the second transmission terminal of the second master chip is connected to the first transmission terminal of the second slave chip of the first level, and the second transmission terminal of each second slave chip of the second level is connected to the first transmission terminal of the next second slave chip. The first master chip is provided with a first signal receiver, the second master chip is provided with a second signal receiver, and the first slave chip and the second slave chip are provided with a third signal receiver; In command mode, the first signal receiver is used to receive the ZQ calibration command provided by the memory through the ZQ signal terminal, and the second signal receiver is used to receive and delay the ZQ calibration command through the ZQ signal terminal. The first main chip and the second main chip start calibration based on the ZQ calibration command. After the first main chip and the second main chip complete the calibration, they send the ZQ flag signal through the second transmission terminal. The ZQ flag signal indicates that the current chip has been calibrated using the calibration resistor. The third signal receiver is used to receive the ZQ flag signal through the first transmission terminal. The first slave chip and the second slave chip start calibration based on the ZQ flag signal. After the first slave chip and the second slave chip complete calibration, they send the ZQ flag signal through the second transmission terminal until all the first slave chips or the second slave chips complete calibration.

2. The memory device according to claim 1, characterized in that, include: The second transmission terminal of the first slave chip in the last stage is connected to the first transmission terminal of the first master chip; The second transmission terminal of the second slave chip in the final stage is connected to the first transmission terminal of the second master chip.

3. The memory device according to claim 2, characterized in that, include: The second main chip also includes a third transmission terminal, which is enabled in background mode to receive the ZQ flag signal. The third transmission terminal is connected to the second transmission terminal of the last stage first slave chip. In the background mode, the first signal receiver is used to receive a clock signal or power-on signal provided by the memory through the ZQ signal terminal. The first main chip starts calibration based on the clock signal or the power-on signal. After the first main chip completes calibration, it sends the ZQ flag signal through the second transmission terminal. The first slave chip, the second master chip, and the second slave chip sequentially begin calibration based on the ZQ flag signal.

4. The memory device according to claim 3, characterized in that, The first master chip further includes a fourth transmission terminal, which is enabled in background mode and used to transmit the ZQ flag signal. The fourth transmission terminal is connected to the second transmission terminal of the last stage second slave chip.

5. The memory device according to claim 3, characterized in that, include: The first signal receiver includes: The first AND gate has one input terminal for receiving the ZQ calibration command and another input terminal for receiving a command indication signal, which is used to indicate that the memory is working in command mode. The second AND gate has one input terminal for receiving a clock signal or a power-on signal, and the other input terminal for receiving a background indication signal, which indicates that the memory is working in background mode. A first input selector has a first input terminal connected to the output terminal of the first AND gate, and a second input terminal connected to the output terminal of the second AND gate. The first selector terminal is used to receive the command indication signal or the background indication signal, and the first output terminal is used to output a first internal calibration signal, which instructs the first main chip and the second main chip to perform calibration. The first input selector is configured to connect the first input terminal to the first output terminal based on the command indication signal, or to connect the second input terminal to the first output terminal based on the background indication signal. The second signal receiver includes: The third AND gate has one input for receiving and delaying the ZQ calibration command, and the other input for receiving the command indication signal. The fourth AND gate has one input for receiving the ZQ flag signal and the other input for receiving the background indication signal. The second input selector has a third input terminal connected to the output terminal of the third AND gate, a fourth input terminal connected to the output terminal of the fourth AND gate, a second selection terminal for receiving the command indication signal or the background indication signal, and a second output terminal for outputting the first internal calibration signal; wherein, the second input selector is configured to connect the third input terminal to the second output terminal based on the command indication signal, or connect the fourth input terminal to the second output terminal based on the background indication signal; The third signal receiver includes: The fifth AND gate has one input terminal for receiving the ZQ flag signal and another input terminal for receiving a first indication signal, which indicates that the current chip is the first slave chip or the second slave chip. The output terminal is used to output a second internal calibration signal, which instructs the first slave chip and the second slave chip to perform calibration.

6. The memory device according to claim 3, characterized in that, include: The first signal receiver and the second signal receiver include: A first selector has one input terminal for receiving the ZQ calibration command, another input terminal for receiving the delayed ZQ calibration command, and a selection terminal for receiving a first main chip identification signal or a second main chip identification signal; the first selector is configured to output the ZQ calibration command based on the first main chip identification signal, or output the delayed ZQ calibration command based on the second main chip identification signal. The first AND gate has one input connected to the output of the first selector and the other input used to receive a command indication signal, which indicates that the memory is working in command mode. The second selector has one input terminal for receiving a clock signal or a power-on signal, another input terminal for receiving the ZQ flag signal transmitted through the third transmission terminal, and a selection terminal for receiving the first main chip identification signal or the second main chip identification signal; the second selector is configured to output the clock signal or the power-on signal based on the first main chip identification signal, or output the ZQ flag signal based on the second main chip identification signal. The second AND gate has one input connected to the output of the second selector and the other input used to receive a background indication signal, which indicates that the memory is working in background mode. A first input selector has a first input terminal connected to the output terminal of the first AND gate, and a second input terminal connected to the output terminal of the second AND gate. The first selector terminal is used to receive the command indication signal or the background indication signal, and the first output terminal is used to output a first internal calibration signal, which instructs the first main chip and the second main chip to perform calibration. The first input selector is configured to connect the first input terminal to the first output terminal based on the command indication signal, or to connect the second input terminal to the first output terminal based on the background indication signal. The third signal receiver includes: The fifth AND gate has one input terminal for receiving the ZQ flag signal and another input terminal for receiving a first indication signal, which indicates that the current chip is the first slave chip or the second slave chip. The output terminal is used to output a second internal calibration signal, which instructs the first slave chip or the second slave chip to perform calibration.

7. The memory device according to claim 5 or 6, characterized in that, include: The first master chip and the second master chip also include the third signal receiver, and the slave chip also includes the first signal receiver and / or the second signal receiver; The first master chip, the first slave chip, the second master chip, and the second slave chip further include: A third input selector has a fifth input terminal for receiving the first internal calibration command, a sixth input terminal for receiving the second internal calibration command, a third selection terminal for receiving either the first indication signal or the second indication signal, the second indication signal being used to characterize the current chip as either the first main chip or the second main chip, and a third output terminal for outputting the first internal calibration command and the second internal calibration command; wherein the third input selector is configured to connect the sixth input terminal to the third output terminal based on the first indication signal, or to connect the fifth input terminal to the third output terminal based on the second indication signal.

8. The memory device according to claim 1, characterized in that, The first master chip, the first slave chip, the second master chip, and the second slave chip are packaged in the same memory device.

9. The memory device according to claim 1, characterized in that, include: The first master chip and the first slave chip are packaged in different memory devices; The second master chip and the second slave chip are packaged in different memory devices; The connection between the first and second transmission ends, which are encapsulated in different memory devices, is set up through wired or wireless interconnection between memory devices.

10. The memory device according to claim 1, characterized in that, include: The number of the second slave chips equals the number of the first slave chips; The first master chip and the first slave chip are arranged in a first array with 1 column and N rows, and the first master chip is located at the Nth row. The second master chip and the second slave chip are arranged in a second array with 1 column and N rows, and the first master chip is located at the N / 2th row. N-1 represents the number of the first slave chips.

11. A ZQ calibration method, applied to the memory device according to any one of claims 1 to 10, characterized in that, include: In command mode, acquire the ZQ calibration command applied externally to the memory device; In response to the ZQ calibration command, a first calibration operation is performed on the first main chip; After the first calibration operation is completed, the ZQ flag signal is transmitted to the first slave chip of the first stage, and at the same time, the second calibration operation is performed on the first master chip; In response to the ZQ flag signal, the first calibration operation is performed on the first slave chip of the first stage; After the first calibration operation of the first slave chip in the first stage is completed, the ZQ flag signal is transmitted to the next first slave chip in the next stage, and the second calibration operation is performed on the first slave chip in the first stage until the last first slave chip in the last stage completes the first calibration operation. The second calibration operation is performed on the last-stage first slave chip; In response to the delayed ZQ calibration command, a first calibration operation is performed on the second main chip; After the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level second slave chip, and at the same time, the second calibration operation is performed on the second master chip; In response to the ZQ flag signal, the first calibration operation is performed on the first-stage second slave chip; After the first calibration operation of the first-level second slave chip is completed, the ZQ flag signal is transmitted to the next-level second slave chip, and the second calibration operation is performed on the first-level second slave chip until the last-level second slave chip completes the first calibration operation. The second calibration operation is performed on the last-stage second slave chip.

12. The ZQ calibration method according to claim 11, characterized in that, include: While performing the second calibration operation on the last-stage first slave chip, the method also includes: transmitting the ZQ flag signal to the first master chip; While performing the second calibration operation on the last-stage second slave chip, the method also includes transmitting the ZQ flag signal to the second master chip.

13. The ZQ calibration method according to claim 11, characterized in that, include: In background mode, in response to the ZQ calibration command, a first calibration operation is performed on the first main chip; After the first calibration operation is completed, the ZQ flag signal is transmitted to the first slave chip of the first stage, and at the same time, the second calibration operation is performed on the first master chip; In response to the ZQ flag signal, the first calibration operation is performed on the first slave chip of the first stage; After the first calibration operation of the first slave chip in the first stage is completed, the ZQ flag signal is transmitted to the next first slave chip in the next stage, and the second calibration operation is performed on the first slave chip in the first stage until the last first slave chip in the last stage completes the first calibration operation. The ZQ flag signal is transmitted to the second master chip, and a second calibration operation is performed on the last-stage first slave chip. In response to the ZQ flag signal, the first calibration operation is performed on the second main chip; After the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level second slave chip, and at the same time, the second calibration operation is performed on the second master chip; In response to the ZQ flag signal, the first calibration operation is performed on the first-stage second slave chip; After the first calibration operation of the first-level second slave chip is completed, the ZQ flag signal is transmitted to the next-level second slave chip, and the second calibration operation is performed on the first-level second slave chip until the last-level second slave chip completes the first calibration operation. The second calibration operation is performed on the last-stage second slave chip.

14. The ZQ calibration method according to claim 13, characterized in that, In the background mode, while performing the second calibration operation on the last-stage second slave chip, the process also includes transmitting the ZQ flag signal to the first master chip.

15. The ZQ calibration method according to claim 11 or 13, characterized in that, The first calibration operation is one of the pull-up calibration operation that generates a pull-up calibration code and the pull-down calibration operation that generates a pull-down calibration code, and the second calibration operation is the other of the pull-up calibration operation and the pull-down calibration operation.

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