A high-precision multi-mode analog counter for lidar

Abstract

This invention discloses a high-precision multi-mode analog counter for lidar, comprising an upward counting unit, a downward counting unit, an upward counting logic unit, a downward counting logic unit, a first mode selection switch 1, a first mode selection switch 2, and a second mode selection switch. The upward counting unit counts digital pulses upwards. A reset signal is generated by the upward counting logic unit to reset the upward counting unit, and a carry signal is generated for the downward counting unit to carry over. The downward counting unit counts downwards. A reset signal is generated by the downward counting logic unit to reset the downward counting unit, and a carry signal is generated for the upward counting unit to carry over. This invention utilizes a switched-capacitor comparator to monitor the charge release amount during each count, achieving high-precision analog counting. The addition of an upward counting unit in addition to the downward counting unit enables a multi-mode analog counter.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of laser radar, and particularly relates to a high-precision multi-mode analog counter applied to a laser radar. BACKGROUND

[0002] The receiving end of the laser radar system includes optical elements and a sensor chip, and the sensor chip is mainly responsible for extracting the 2D intensity information and 3D distance information contained in the received light signal. The common 2D intensity information can be obtained by counting the digital pulses generated by the quenching circuit of the SPAD (Single-Photon Avalanche Diode) in the chip within a certain time through the in-pixel counter of the laser radar chip.

[0003] The in-pixel counter includes a digital counter and an analog counter. The digital counter is generally composed of multiple D flip-flops, and even if a true single-phase clock D flip-flop is used, the area consumed is large, which inevitably reduces the fill factor of the pixel, and the lower fill factor leads to the reduction of the detection efficiency. The analog counter generally uses the charging and discharging of a capacitor to realize counting, and compared with the digital counter, it has a compact structure, small area and low power consumption, which is conducive to improving the fill factor of the pixel. In addition, the in-pixel analog counter has a simple structure, and the counting step can be configured, which is more suitable for array integration. Therefore, it is necessary to set an analog counter in the SPAD front-end circuit of the laser radar chip pixel.

[0004] The existing analog counter circuit is generally based on the SCS (Switched Current Source) or CTA (Charge Transfer Amplifier) structure. The analog counter based on the SCS structure has a current source that is always on, which has high power consumption and does not meet the requirement of small power consumption of the SPAD front-end circuit, so generally the analog counter based on the CTA is considered.

[0005] A typical analog counter based on the CTA is as shown in Figure 1As shown, charge sharing strategy is adopted. The analog counter includes integration capacitor C1 and discharge capacitor Cp. ΦTRG is the counter trigger signal pulse, and ΦDIS is the charge sharing reset pulse. ΦTRG can generate ΦDIS after a certain delay, and controls the on-off of TRG switch and DIS switch. After TRG switch is turned on, the charge on integration capacitor C1 is shared to discharge capacitor Cp. After TRG switch is turned off, the sharing is ended, and at this time, the output voltage Vo has a voltage drop of ΔVo, which is an effective count. After DIS switch is turned on, the charge on discharge capacitor Cp is released to the ground, and is prepared for receiving the shared charge of integration capacitor C1 for the next count. The count step ΔVo depends on the output voltage Vo. With continuous down-counting, Vo decreases, and ΔVo changes, thereby affecting the linearity of the counter. Because the count step only depends on Vo, the count step is not adjustable.

[0006] In order to solve the nonlinearity problem and make the count step adjustable, charge injection strategy is adopted, as shown in FIG. 2. Figure 2 As shown, an NMOS source follower Msf is added, so as to separate Vo and Cp. The count step does not depend on the change of Vo. By adjusting the bias voltage Vbias of transistor Msf, the amount of charge injected each time can be controlled, and thus the count step ΔVo can be adjusted. However, there is a loss of NMOS threshold voltage when the bias voltage Vbias is transmitted to the source voltage through the source follower Msf. Fluctuation of the threshold voltage will cause the amount of charge injected each time to change, and thus the count step ΔVo changes.

[0007] In order to avoid the influence of the threshold voltage, an operational amplifier assisted charge injection strategy is adopted, as shown in FIG. 3. Figure 3 As shown, a five-tube amplifier is introduced, so that the source voltage of MF tube is equal to the reference voltage Vref. In this way, the charge injected from C1 to Cp is a fixed amount of charge which is not affected by the threshold voltage. The fixed amount of charge is Qp=Cp×Vref, and the linearity of the counter is higher.

[0008] The CTA analog counter using the charge sharing strategy has a counting step length Delta Vo dependent on the output voltage Vo, and as the continuous down counting, Vo decreases, the counting step length changes, thereby seriously affecting the linearity of the counter, and the step length is only dependent on Vo and cannot be adjusted. The CTA analog counter using the charge injection strategy has a gate bias voltage Vbias transmitted to the source voltage through a source follower, and there is a threshold voltage loss in the source voltage, and the charge injection amount of each counting is affected by the threshold voltage. As the threshold voltage is sensitive to process deviation, the threshold voltage fluctuates, and therefore the counting step length Delta Vo of each time has deviation, thereby affecting the linearity of the analog counter. The CTA analog counter using the charge injection strategy assisted by the operational amplifier mainly has the following shortcomings: the operational amplifier has a certain restriction and influence on the in-pixel analog counter circuit in the actual design. The five-tube amplifier structure used by the operational amplifier has a tail current source, and has a certain power consumption. In order to reduce the power consumption of the in-pixel operational amplifier, a very small tail current source needs to be designed, thereby increasing the design difficulty. In addition, as the operational amplifier has a setup time, the source voltage of the Mf tube is equal to the reference voltage Vref only after a certain time through the virtual short characteristic of the operational amplifier, and therefore the operational amplifier has a certain restriction on the counter trigger signal pulse Phi TRG. For example, in the time when the TRG switch is turned on by the counter trigger signal pulse Phi TRG, the operational amplifier has not completed the setup, the source voltage of the Mf tube is not equal to the reference voltage Vref, the injected charge amount is not the fixed charge amount defined by the reference voltage Vref, and the counting step length Delta Vo has deviation.

[0009] In addition, the existing analog counter only supports a relatively single function, that is, only supports down counting, and cannot perform a certain complex in-pixel operation of the laser radar chip. SUMMARY

[0010] In order to solve the above problems in the prior art, the application provides a high-precision multi-mode analog counter applied to a laser radar.

[0011] The application provides a high-precision multi-mode analog counter applied to a laser radar, which comprises an up-counting unit, a down-counting unit, an up-counting logic unit, a down-counting logic unit, a first mode selection switch 1, a first mode selection switch 2 and a second mode selection switch.

[0012] The up-counting unit is connected with the up-counting logic unit and the down-counting logic unit, can perform up counting on the input digital pulse, and generates a reset signal through the up-counting logic unit to reset the counting MOS capacitor of the up-counting unit, and generates a carry signal for carry counting to the down-counting unit.

[0013] The downward counting unit is connected to the upward counting logic unit and the downward counting logic unit is connected. It can count the input digital pulses downward, and generate a reset signal through the downward counting logic unit to reset the counting MOS capacitor of the downward counting unit, and generate a carry signal for the upward counting unit to carry count.

[0014] The upward counting unit is connected between the first mode selection switch 1 and the second mode selection switch, and the downward counting unit is connected between the second mode selection switch and the first mode selection switch 2; the first mode selection switch 1 and the first mode selection switch 2 have the same switching state, and the first mode selection switch 1 and the second mode selection switch are complementary switches with opposite switching states.

[0015] In one embodiment of the present invention, the upward counting unit includes a data selector MUX1, a data selector MUX2, a data selector MUX3, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, an OR gate OR1, a PMOS transistor MD1, a PMOS transistor MT1, a PMOS transistor ME1, a PMOS transistor MF1, a counting MOS capacitor C1, a counting MOS capacitor CP1, a comparator COMP_UP, and an NMOS transistor NM1, wherein...

[0016] The first input terminal of data selector MUX1 receives an externally provided TRIG_UP signal, and the second input terminal receives the carry signal TRIG_UP_carry generated by the down-counting logic unit. The output terminal of data selector MUX1 is connected to the first input terminal of OR gate OR1. The first input terminal of data selector MUX2 receives an externally provided DIS_UP signal, and the second input terminal receives the carry signal DIS_UP_carry generated by the down-counting logic unit. The output terminal of data selector MUX2 is connected to the gate of PMOS transistor MD1. The control terminals of both data selectors MUX1 and MUX2 receive an external control signal SELP.

[0017] The source of the PMOS transistor MD1 is connected to the power supply terminal VDD. The drain of the PMOS transistor MD1 is simultaneously connected to the source of the MOS capacitor CP1 and the drain of the MOS capacitor CP1. The source of the PMOS transistor MT1 is connected to the first input terminal of the switched capacitor comparator COMP_UP. The gate of the MOS capacitor CP1 is connected to the ground terminal GND.

[0018] The inverter INV1 receives the clock enable signal CLK_UP at its input terminal and its output terminal is connected to the second input terminal of the OR gate OR1. The output terminal of the OR gate OR1 is connected to the gate of the PMOS transistor MT1. The input terminal of the inverter INV2 is connected to the output terminal of the OR gate OR1, and the output terminal of the inverter INV2 is connected to the gate of the PMOS transistor ME1. The drain of the PMOS transistor MT1 is simultaneously connected to the source of the PMOS transistor ME1, the drain of the PMOS transistor ME1, and the source of the PMOS transistor MF1.

[0019] The reference threshold voltage VT_ΔV_UP is input to the second input terminal of the switched capacitor comparator COMP_UP. The inverters INV3, INV4, and INV5 are connected in series between the output terminal of the switched capacitor comparator COMP_UP and the gate of the PMOS transistor MF1.

[0020] The drain of the PMOS transistor MF1 is simultaneously connected to the gate of the counting MOS capacitor C1, the drain of the NMOS transistor NM1, the first mode selection switch 1, and the second mode selection switch. The source and drain of the counting MOS capacitor C1 are simultaneously connected to the power supply terminal VDD. The source of the NMOS transistor NM1 receives the externally provided VM_UP signal. The gate of the NMOS transistor NM1 is connected to the output terminal of the data selector MUX3. The two input terminals of the data selector MUX3 receive the global reset signal RST and the RST_CAP_P generated by the downward counting logic unit, respectively. The control terminal of the data selector MUX3 receives the mode selection signal mode.

[0021] In one embodiment of the present invention, the upward counting logic unit includes a PMOS transistor MP1, an NMOS transistor MC1, inverters INV6, INV7, INV8, INV9, INV10, INV11, a D flip-flop DFF1, AND gates AND1, AND gates AND2, AND gates AND3, an OR gate OR2, delay lines D1, D2, and D3, wherein...

[0022] The source of the PMOS transistor MP1 is connected to the power supply terminal VDD, the gate of the PMOS transistor MP1 is connected to the output terminal of the AND gate AND3, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MC1, the gate of the NMOS transistor MC1 is connected to the first mode selection switch 1, and the source of the NMOS transistor MC1 is input to the externally provided signal VT_UP.

[0023] The inverters INV6, INV7, and INV8 are connected in series between the drain of the PMOS transistor MP1 and the clock pulse input of the D flip-flop DFF1. The D terminal of the D flip-flop DFF1 is connected to the power supply VDD, and the Q terminal of the D flip-flop DFF1 is connected to the second input of the OR gate OR2.

[0024] The first input terminal of AND gate AND1 receives the global reset signal RSTN, and the second input terminal is connected to the output terminal of AND gate AND3. The output terminal of AND gate AND1 is connected to the first input terminal of AND gate AND2. The delay line D1 and the inverter INV9 are connected in series between the Q terminal of D flip-flop DFF1 and the second input terminal of AND gate AND2. The output terminal of AND gate AND2 is connected to the R terminal of D flip-flop DFF1.

[0025] The first input of the OR gate OR2 receives the global reset signal RST, and the output of the OR gate OR2 outputs the RST_CAP_P signal, which is connected to one input of the data selector MUX3. The delay line D2 and the inverter INV10 are connected in series between the Q terminal of the D flip-flop DFF1 and the first input of the AND gate AND3. The second input of the AND gate AND3 receives the global reset signal RSTN.

[0026] The input terminal of inverter INV11 is connected to the output terminal of inverter INV10, and the output terminal of inverter INV11 is connected to delay line D3. Delay line D3 outputs the signal DIS_DN_carry.

[0027] In one embodiment of the present invention, both signal RST and signal RSTN are externally provided signals and are logically opposite signals.

[0028] In one embodiment of the present invention, the downward counting unit includes inverters INV12, INV13, and INV14, NMOS transistors MD2, MT2, ME2, and MF2, counting MOS capacitors C2 and CP2, a switched capacitor comparator COMP_DN, a PMOS transistor PM1, an AND gate AND4, a data selector MUX4, MUX5, and MUX6, and a first mode selection switch 3, wherein...

[0029] The inverters INV12 and INV13 are connected in series between the output of the switched capacitor comparator COMP_DN and the gate of the NMOS transistor MF2. The source of the NMOS transistor MF2 is simultaneously connected to the drain of the NMOS transistor ME2, the source of the NMOS transistor ME2, and the drain of the NMOS transistor MT2.

[0030] The two input terminals of the data selector MUX5 are respectively input to the externally provided digital pulse signal DIS_DN and the carry signal DIS_DN_carry generated by the upward counting logic unit. The output terminal of the data selector MUX5 is connected to the gate of the NMOS transistor MD2, the source of the NMOS transistor MD2 is connected to the ground terminal, and the drain of the NMOS transistor MD2 is connected to the source of the NMOS transistor MT2.

[0031] The two inputs of the data selector MUX6 are respectively the externally provided digital pulse signal TRIG_DN and the carry signal TRIG_DN_carry generated by the up-counting logic unit. The output of the data selector MUX6 is connected to the first input of the AND gate AND4, and the second input of the AND gate AND4 is connected to the clock enable signal CLK_DN. The output of the AND gate AND4 is connected to the gate of the NMOS transistor MT2. The control terminals of the data selectors MUX5 and MUX6 are both input to the external control signal SELN.

[0032] The source of the NMOS transistor MT2 is simultaneously connected to the drain of the NMOS transistor MD2, the first input terminal of the switched capacitor comparator COMP_DN, and the gate of the MOS capacitor CP2. The source and drain of the counting MOS capacitor CP2 are both connected to the power supply terminal VDD. The second input terminal of the switched capacitor comparator COMP_DN receives an externally provided reference threshold voltage VT_ΔV_DN.

[0033] One end of the first mode selection switch 3 is connected to the drain of the NMOS transistor MF2 and the second mode selection switch, and the other end is simultaneously connected to the drain of the PMOS transistor PM1, the source of the counting MOS capacitor C2, the drain of the counting MOS capacitor C2, and the first mode selection switch 2; the source of the PMOS transistor PM1 receives the externally provided VM_DN signal, and the gate of the counting MOS capacitor C2 is connected to the ground terminal;

[0034] The two input terminals of the data selector MUX4 are respectively input to the RST signal and the RST_CAP_N signal from the down-counting logic unit. The control terminal of the data selector MUX4 is input to the mode selection signal mode. The output terminal of the data selector MUX6 is connected to the gate of the PMOS transistor PM1.

[0035] In one embodiment of the present invention, the first mode selection switch 3 has the same switching state as the first mode selection switch 1.

[0036] In one embodiment of the present invention, the switched capacitor comparator COMP_DN includes a first MOS switch K1, a second MOS switch K2, a third MOS switch K3, a fourth MOS switch K4, a fifth MOS switch K5, an inverter INV15, an inverter INV16, an inverter INV17, MOS capacitors C3, C4, and C5, wherein...

[0037] The first terminal of the first MOS switch K1 serves as the first input terminal of the switched capacitor comparator COMP_DN, and the second terminal of the first MOS switch K1 is connected to the gate of the MOS capacitor C3. The first terminal of the second MOS switch K2 serves as the second input terminal of the switched capacitor comparator COMP_DN, and the second terminal of the second MOS switch K1 is connected to the gate of the MOS capacitor C3.

[0038] The source and drain of the MOS capacitor C3 are simultaneously connected to the input terminal of the inverter INV15. The third MOS switch K3 is connected between the input and output terminals of the inverter INV15. The output terminal of the inverter INV15 is connected to the gate of the MOS capacitor C4.

[0039] The source and drain of the MOS capacitor C4 are simultaneously connected to the input terminal of the inverter INV16. The third MOS switch K4 is connected between the input and output terminals of the inverter INV16. The output terminal of the inverter INV16 is connected to the gate of the MOS capacitor C5.

[0040] The source and drain of the counting MOS capacitor C5 are simultaneously connected to the input terminal of the inverter INV17. The third MOS switch K5 is connected between the input and output terminals of the inverter INV17. The output terminal of the inverter INV17 serves as the output terminal of the switched capacitor comparator COMP_DN.

[0041] In one embodiment of the present invention, when the first MOS switch K1 is off, the second MOS switch K2, the third MOS switch K3, the fourth MOS switch K4 and the fifth MOS switch K5 are all connected; when the first MOS switch K1 is connected, the second MOS switch K2, the third MOS switch K3, the fourth MOS switch K4 and the fifth MOS switch K5 are all off.

[0042] In one embodiment of the present invention, the downward counting logic unit includes a PMOS transistor MC2, an NMOS transistor NM2, inverters INV18, INV19, INV20, INV21, INV22, a D flip-flop DFF2, AND gates AND5, AND gates AND6, AND gates AND7, an OR gate OR3, delay lines D4, D5, and D6, wherein...

[0043] The gate of the PMOS transistor MC2 is connected to the first mode selection switch 2, the source of the PMOS transistor MC2 is input with the externally provided VT_DN signal, the gate of the NMOS transistor NM2 is connected to the output terminal of the OR gate OR3, the source of the NMOS transistor NM2 is connected to the ground terminal, and the drain of the PMOS transistor MC2 is connected to the drain of the NMOS transistor NM2.

[0044] The inverters INV18 and INV19 are connected in series between the drain of the PMOS transistor MC2 and the clock pulse input of the D flip-flop DFF2. The D terminal of the D flip-flop DFF2 is connected to the power supply VDD, and the Q terminal of the D flip-flop DFF2 is connected to the input of the inverter INV21.

[0045] The first input of AND gate AND5 is the global reset signal RSTN. The second input is connected between inverter INV22 and delay line D6. The output of AND gate AND5 is connected to the first input of AND gate AND6. Delay line D4 and inverter INV20 are connected in series between the Q terminal of D flip-flop DFF2 and the second input of AND gate AND6. The output of AND gate AND6 is connected to the R terminal of D flip-flop DFF2.

[0046] The output of the inverter INV21 is connected to the first input of the AND gate AND7, the second input of the AND gate AND7 receives the global reset signal RSTN, and the output of the AND gate AND7 outputs the RST_CAP_N signal and is connected to the data selector MUX4.

[0047] The first end of the delay line D5 is connected to the Q terminal of the D flip-flop DFF2, and the other end is connected to the first input terminal of the OR gate OR3. The second input terminal of the OR gate OR3 receives the global reset signal RST.

[0048] The input terminal of the inverter INV22 is connected to the first input terminal of the OR gate OR3, the output terminal of the inverter INV22 is connected to the first terminal of the delay line D6, and the second terminal of the delay line D6 is connected to the data selector MUX2.

[0049] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0050] 1. This invention provides a high-precision multi-mode analog counter for lidar. It introduces a switched capacitor comparator to monitor the amount of charge released in each count. When the charge exceeds a set threshold, the feedback is sent back to the circuit switch to precisely control the counting step size. The counting step size is not affected by the threshold voltage of the MOS device, and the process deviation is small. The switching capacitor comparator is used for comparison, which has low power consumption and high accuracy, and realizes high-precision analog counting with adjustable step size.

[0051] 2. In order to better perform on-chip data processing of the LiDAR, this invention adds an upward counting unit in addition to the downward counting unit, and realizes an upward-down or downward-upward carry-able counting mode and an upward / downward difference counting mode through a mode selection switch, thereby realizing a multi-mode analog counter. The multi-mode counter can better support the intra-pixel operation of the LiDAR chip.

[0052] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of a typical CTA-based analog counter;

[0054] Figure 2 This is a schematic diagram of an existing CTA-based analog counter;

[0055] Figure 3 This is a schematic diagram of another existing CTA-based analog counter;

[0056] Figure 4 This is a module diagram of a high-precision multi-mode analog counter for lidar provided in an embodiment of the present invention;

[0057] Figure 5 This is a circuit diagram of an upward counting unit provided in an embodiment of the present invention;

[0058] Figure 6 This is a circuit diagram of an upward counting logic unit provided in an embodiment of the present invention;

[0059] Figure 7 This is a circuit diagram of a downward counting unit provided in an embodiment of the present invention;

[0060] Figure 8 This is a circuit diagram of a switched capacitor comparator for a downward counting unit provided in an embodiment of the present invention;

[0061] Figure 9 This is a circuit diagram of a downward counting logic unit provided in an embodiment of the present invention;

[0062] Figure 10This is a specific circuit diagram of a high-precision multi-mode analog counter for lidar provided in an embodiment of the present invention;

[0063] Figure 11 This is a schematic diagram of an upward-downward carry-able counting mode provided by an embodiment of the present invention;

[0064] Figure 12 This is an internal signal timing diagram of an up-down carry-able counting mode provided in an embodiment of the present invention;

[0065] Figure 13 This is a schematic diagram of an upward / downward difference counting mode provided by an embodiment of the present invention;

[0066] Figure 14 This is an internal signal timing diagram of an upward / downward differential counting mode provided in an embodiment of the present invention. Detailed Implementation

[0067] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the high-precision multi-mode analog counter for lidar proposed according to the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0068] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0069] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0070] Please see Figure 4 , Figure 4This is a block diagram of a high-precision multi-mode analog counter for lidar provided in an embodiment of the present invention. The high-precision multi-mode analog counter includes an upward counting unit, a downward counting unit, an upward counting logic unit, a downward counting logic unit, a first mode selection switch 1, a first mode selection switch 2, and a second mode selection switch.

[0071] The up counting unit connects the up counting logic unit and the down counting logic unit. It can count the input digital pulses upwards and generate a reset signal through the up counting logic unit to reset the counting MOS capacitor of the up counting unit, and generate a carry signal for the down counting unit to carry over.

[0072] The downward counting unit is connected to the upward counting logic unit and the downward counting logic unit. It can count the input digital pulses downwards and generate a reset signal through the downward counting logic unit to reset the counting MOS capacitor of the downward counting unit and generate a carry signal for the upward counting unit to carry-count.

[0073] The upward counting unit is connected between the first mode selection switch 1 and the second mode selection switch, and the downward counting unit is connected between the second mode selection switch and the first mode selection switch 2; the first mode selection switch 1 and the first mode selection switch 2 have the same switching state, and the first mode selection switch 1 and the second mode selection switch are complementary switches with opposite switching states.

[0074] First mode selection switches 1 and 2 are used to select either the up-down or down-up carry-able counting mode, while the second mode selection switch is used to select the up / down difference counting mode. Further details can be found in the following documentation. Figure 5 , Figure 5 This is a circuit diagram of an upward counting unit provided in an embodiment of the present invention. The upward counting unit includes data selectors MUX1, MUX2, and MUX3, inverters INV1, INV2, INV3, INV4, and INV5, an OR gate OR1, PMOS transistors MD1, MT1, ME1, and MF1, a counting MOS capacitor C1, a MOS capacitor CP1, a switched capacitor comparator COMP_UP, and an NMOS transistor NM1.

[0075] Data selector MUX1 receives an externally provided TRIG_UP signal at its first input and a carry signal TRIG_UP_carry generated by the down-counting logic unit at its second input. The output of data selector MUX1 is connected to the first input of OR gate OR1. Data selector MUX2 receives an externally provided DIS_UP signal at its first input and a carry signal DIS_UP_carry generated by the down-counting logic unit at its second input. The output of data selector MUX2 is connected to the gate of PMOS transistor MD1. Both data selectors MUX1 and MUX2 receive an external control signal SELP at their control terminals.

[0076] The source of PMOS transistor MD1 is connected to the power supply terminal VDD. The drain of PMOS transistor MD1 is simultaneously connected to the source of MOS capacitor CP1, the drain of MOS capacitor CP1, the source of PMOS transistor MT1, and the first input terminal of switched capacitor comparator COMP_UP. The gate of MOS capacitor CP1 is connected to the ground terminal GND.

[0077] The input terminal of inverter INV1 receives the clock enable signal CLK_UP, and its output terminal is connected to the second input terminal of OR gate OR1. The output terminal of OR gate OR1 is connected to the gate of PMOS transistor MT1. The input terminal of inverter INV2 is connected to the output terminal of OR gate OR1, and its output terminal is connected to the gate of PMOS transistor ME1. The drain of PMOS transistor MT1 is simultaneously connected to the source, drain, and source of PMOS transistor MF1.

[0078] The reference threshold voltage VT_ΔV_UP is input to the second input terminal of the switched capacitor comparator COMP_UP. Inverters INV3, INV4 and INV5 are connected in series between the output terminal of the switched capacitor comparator COMP_UP and the gate of PMOS transistor MF1.

[0079] The drain of PMOS transistor MF1 is simultaneously connected to the gate of counting MOS capacitor C1, the drain of NMOS transistor NM1, the first mode selection switch 1, and the second mode selection switch. The source and drain of counting MOS capacitor C1 are simultaneously connected to the power supply terminal VDD. The source of NMOS transistor NM1 receives the externally provided VM_UP signal. The gate of NMOS transistor NM1 is connected to the output terminal of data selector MUX3. The two input terminals of data selector MUX3 receive the global reset signal RST and the RST_CAP_P signal generated by the down-counting logic unit, respectively. The control terminal of data selector MUX3 receives the mode selection signal mode.

[0080] Further, please see Figure 6 , Figure 6This is a circuit diagram of an upward counting logic unit provided in an embodiment of the present invention. The upward counting logic unit includes a PMOS transistor MP1, an NMOS transistor MC1, inverters INV6, INV7, INV8, INV9, INV10, INV11, a D flip-flop DFF1, AND gates AND1, AND gates AND2, AND gates AND3, an OR gate OR2, delay lines D1, D2, and D3, wherein...

[0081] The source of PMOS transistor MP1 is connected to the power supply terminal VDD, the gate of PMOS transistor MP1 is connected to the output terminal of AND gate AND3, the drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MC1, the gate of NMOS transistor MC1 is connected to the first mode 2 selection switch, and the source of NMOS transistor MC1 is input to the externally provided signal VT_UP.

[0082] Inverters INV6, INV7, and INV8 are connected in series between the drain of PMOS transistor MP1 and the clock pulse input of D flip-flop DFF1. The D terminal of D flip-flop DFF1 is connected to the power supply VDD, and the Q terminal of D flip-flop DFF1 is connected to the second input of OR gate OR2.

[0083] The first input of AND gate AND1 is connected to the global reset signal RSTN, the second input is connected to the output of AND gate AND3, the output of AND gate AND1 is connected to the first input of AND gate AND2, the delay line D1 and the inverter INV9 are connected in series between the Q terminal of D flip-flop DFF1 and the second input of AND gate AND2, and the output of AND gate AND2 is connected to the R terminal of D flip-flop DFF1.

[0084] The first input of OR gate OR2 receives the global reset signal RST, and the output of OR gate OR2 outputs the RST_CAP_P signal, which is connected to one input of data selector MUX3. Delay line D2 and inverter INV10 are connected in series between the Q terminal of D flip-flop DFF1 and the first input of AND gate AND3. The second input of AND gate AND3 receives the global reset signal RSTN.

[0085] The input of inverter INV11 is connected to the output of inverter INV10, and the output of inverter INV11 is connected to delay line D3. Delay line D3 outputs the signal DIS_DN_carry.

[0086] In this embodiment, both signal RST and signal RSTN are externally provided signals and are logically opposite signals.

[0087] Further, please see Figure 7 , Figure 7This is a circuit diagram of a downward counting unit provided in an embodiment of the present invention. The downward counting unit includes inverters INV12, INV13, and INV14, NMOS transistors MD2, MT2, ME2, and MF2, counting MOS capacitors C2 and CP2, a switched capacitor comparator COMP_DN, a PMOS transistor PM1, an AND gate AND4, a data selector MUX4, MUX5, and MUX6, and a first mode selection switch 3.

[0088] Inverters INV12 and INV13 are connected in series between the output of the switched capacitor comparator COMP_DN and the gate of NMOS transistor MF2. The source of NMOS transistor MF2 is simultaneously connected to the drain of NMOS transistor ME2, the source of NMOS transistor ME2, and the drain of NMOS transistor MT2.

[0089] The two input terminals of the data selector MUX5 are respectively input to the externally provided digital pulse signal DIS_DN and the carry signal DIS_DN_carry generated by the upward counting logic unit. The output terminal of the data selector MUX5 is connected to the gate of NMOS transistor MD2, the source of NMOS transistor MD2 is connected to the ground terminal, and the drain of NMOS transistor MD2 is connected to the source of NMOS transistor MT2.

[0090] The two inputs of data selector MUX6 are respectively the externally provided digital pulse signal TRIG_DN and the carry signal TRIG_DN_carry generated by the up-counting logic unit. The output of data selector MUX6 is connected to the first input of AND gate AND4, the second input of AND gate AND4 is connected to the clock enable signal CLK_DN, and the output of AND gate AND4 is connected to the gate of NMOS transistor MT2. The control terminals of data selectors MUX5 and MUX6 are both connected to the external control signal SELN.

[0091] The source of NMOS transistor MT2 is simultaneously connected to the drain of NMOS transistor MD2, the first input terminal of switched capacitor comparator COMP_DN, and the gate of MOS capacitor CP2. The source and drain of MOS capacitor CP2 are both connected to the power supply terminal VDD. The second input terminal of switched capacitor comparator COMP_DN receives the externally provided reference threshold voltage VT_ΔV_DN.

[0092] One end of the first mode selection switch 3 is connected to the drain of NMOS transistor MF2 and the second mode selection switch, and the other end is simultaneously connected to the drain of PMOS transistor PM1, the source of counting MOS capacitor C2, the drain of counting MOS capacitor C2, and the first mode selection switch 2; the source of PMOS transistor PM1 receives the externally provided VM_DN signal, and the gate of counting MOS capacitor C2 is connected to the ground terminal.

[0093] The two input terminals of the data selector MUX4 are respectively input to the RST signal and the RST_CAP_N signal from the down-counting logic unit. The control terminal of the data selector MUX4 is input to the mode selection signal mode. The output terminal of the data selector MUX6 is connected to the gate of the PMOS transistor PM1.

[0094] The first mode selection switch 3 has the same switching state as the first mode selection switch 1.

[0095] Please see Figure 8 , Figure 8 This is a schematic diagram of a switched-capacitor comparator COMP_DN provided in an embodiment of the present invention. The switched-capacitor comparator COMP_DN includes a first MOS switch K1, a second MOS switch K2, a third MOS switch K3, a fourth MOS switch K4, a fifth MOS switch K5, inverters INV15, INV16, and INV17, MOS capacitors C3, C4, and C5, wherein...

[0096] The first terminal of the first MOS switch K1 serves as the first input terminal of the switched capacitor comparator COMP_DN, and the second terminal of the first MOS switch K1 is connected to the gate of the MOS capacitor C3. The first terminal of the second MOS switch K2 serves as the second input terminal of the switched capacitor comparator COMP_DN, and the second terminal of the second MOS switch K1 is connected to the gate of the MOS capacitor C3.

[0097] The source and drain of MOS capacitor C3 are connected to the input of inverter INV15. The third MOS switch K3 is connected between the input and output of inverter INV15. The output of inverter INV15 is connected to the gate of MOS capacitor C4.

[0098] The source and drain of MOS capacitor C4 are connected to the input of inverter INV16. The third MOS switch K4 is connected between the input and output of inverter INV16. The output of inverter INV16 is connected to the gate of MOS capacitor C5.

[0099] The source and drain of MOS capacitor C5 are connected to the input of inverter INV17. The third MOS switch K5 is connected between the input and output of inverter INV17. The output of inverter INV17 serves as the output of switched capacitor comparator COMP_DN.

[0100] In this embodiment, when the first MOS switch K1 is off, the second MOS switch K2, the third MOS switch K3, the fourth MOS switch K4, and the fifth MOS switch K5 are all connected. When the first MOS switch K1 is connected, the second MOS switch K2, the third MOS switch K3, the fourth MOS switch K4, and the fifth MOS switch K5 are all off.

[0101] Please see Figure 9 , Figure 9 This is a circuit diagram of a downward counting logic unit provided in an embodiment of the present invention. The downward counting logic unit includes a PMOS transistor MC2, an NMOS transistor NM2, inverters INV18, INV19, INV20, INV21, INV22, a D flip-flop DFF2, AND gates AND5, AND gates AND6, AND gates AND7, an OR gate OR3, delay lines D4, D5, and D6, wherein...

[0102] The gate of PMOS transistor MC2 is connected to the first mode selection switch 2, the source of PMOS transistor MC2 is input to the externally provided VT_DN signal, the gate of NMOS transistor NM2 is connected to the output of OR gate OR3, the source of NMOS transistor NM2 is connected to the ground terminal, and the drain of PMOS transistor MC2 is connected to the drain of NMOS transistor NM2.

[0103] Inverters INV18 and INV19 are connected in series between the drain of PMOS transistor MC2 and the clock pulse input of D flip-flop DFF2. The D terminal of D flip-flop DFF2 is connected to the power supply VDD, and the Q terminal of D flip-flop DFF2 is connected to the input of inverter INV21.

[0104] The first input of AND gate AND5 is the global reset signal RSTN. The second input is connected between inverter INV22 and delay line D6. The output of AND gate AND5 is connected to the first input of AND gate AND6. Delay line D4 and inverter INV20 are connected in series between the Q terminal of D flip-flop DFF2 and the second input of AND gate AND6. The output of AND gate AND6 is connected to the R terminal of D flip-flop DFF2.

[0105] The output of inverter INV21 is connected to the first input of AND gate AND7. The second input of AND gate AND7 receives the global reset signal RSTN. The output of AND gate AND7 outputs the RST_CAP_N signal and is connected to data selector MUX4.

[0106] The first end of the delay line D5 is connected to the Q terminal of the D flip-flop DFF2, and the other end is connected to the first input terminal of the OR gate OR3, and the global reset signal RST is input to the second input terminal of the OR gate OR3.

[0107] The input of inverter INV22 is connected to the first input of OR gate OR3, the output of inverter INV22 is connected to the first end of delay line D6, and the second end of delay line D6 is connected to data selector MUX2.

[0108] Specifically, please refer to the following: Figure 7 and Figure 10 , Figure 10 This is a specific circuit diagram of a high-precision multi-mode analog counter applied to lidar, provided by an embodiment of the present invention. OUT_DN is the counting output result of the downward counting unit, which reads the voltage of the counting MOS capacitor C2. After reset, the initial voltage value of the counting MOS capacitor C2 is VM_DN, which is the source voltage value of the PMOS transistor PM1 and is an external input to the counter. Signals TRIG_DN and DIS_DN are digital pulse signals provided externally to the counter. Signals TRIG_DN_carry and DIS_DN_carry are carry signals provided by the upward counting logic unit inside the counter, for this downward counting unit to perform carry operations.

[0109] The downward counting process consists of two stages: a charge release stage and a charge reset stage. NMOS transistors MT2 and MD2 act as switches corresponding to these two stages. When MT2 is turned on, it indicates the presence of a valid input digital pulse to be counted, triggering the charge release stage. During this stage, the counting MOS capacitor C2 releases its charge, which is stored in the parasitic capacitances of MOS capacitor CP2 and NMOS transistor MD2. The count output voltage OUT_DN decreases by ΔV0. When NMOS transistor MD2 is turned on, the charge reset stage begins, and the charge stored in the parasitic capacitances of MOS capacitor CP2 and NMOS transistor MD2 is released to ground. A phase delay exists between signals TRIG_DN and DIS_DN, or between signals TRIG_DN_carry and DIS_DN_carry. Therefore, the conduction periods of NMOS transistors MT2 and MD2 are different, ensuring that the charge release and charge reset stages do not overlap and preventing charge loss.

[0110] Furthermore, the operation of the switched-capacitor comparator COMP_DN in the down-counting unit is divided into two stages: a reference threshold voltage sampling stage and a comparison stage. For example... Figure 8 As shown, the first stage is the reference threshold voltage sampling stage. K2-K5 are closed, K1 is open, and the input and output terminals of inverters INV15, INV16, and INV17 are short-circuited. Inverters INV15, INV16, and INV17 are at the logic threshold point, establishing a suitable reference point for the comparison in the next stage. The second stage is the comparison stage. K1 is closed, K2-K5 are open, and the input voltage VINN is compared with the externally provided reference threshold voltage VT_ΔV_DN. Inverters INV15, INV16, and INV17 are flipped accordingly. The TG_NIN signal controls the on / off state of switches K1 and K2-K5 in the switched capacitor comparator COMP_DN. When the down-counting unit enters the charge reset stage, the switched capacitor comparator COMP_DN enters the reference threshold voltage sampling stage; when the down-counting unit enters the charge release stage, the switched capacitor comparator COMP_DN enters the comparison stage. The switched-capacitor comparator COMP_DN monitors the amount of charge released during each count by comparing the input voltage VINN with the reference threshold voltage VT_ΔV_DN. If the charge exceeds the set threshold, feedback is sent to the gate control terminal of the MOS switch MF2, causing MOS switch MF2 to open. This forces the end of the charge release phase during the downward counting process, pending the start of the charge reset phase. Therefore, the set reference threshold voltage ensures that the amount of charge released during each count is a fixed value. VG_DN is the source voltage of the PMOS in the inverter INV13. Generally, VG_DN is less than VDD, reducing the on-current of the switching transistor MF2 and mitigating overshoot during comparison in the switched-capacitor comparator.

[0111] Furthermore, an additional MOS transistor ME2 with its source and drain interconnected is added to the circuit of the down-counting unit, and a control signal is present at the gate. When the channel of ME2 is not conducting, it does not affect the on / off state of the downward counting unit circuit, acting as a virtual switch. The charge injection effect generated when this virtual switch is turned on and off is used to compensate for the charge in the downward counting unit circuit, correcting the waveform of the downward counting unit's output signal and facilitating subsequent processing of the counting output results by subsequent circuits.

[0112] like Figure 9As shown, MC2 is a single-transistor comparator that compares the count output OUT_DN of the down-counting unit with the count threshold. VT_DN is the source voltage of the single-transistor comparator. When the count output OUT_DN is less than the set count threshold, MC2 is turned on, and the monostable circuit generates a reset carry pulse signal. After the reset carry pulse signal is generated, an RST_CAP_N signal is first generated to reset the down-counting MOS capacitor C2, then an RST_2T_N signal is generated to reset the single-transistor comparator MC2, and finally carry signals TRIG_UP_carry and DIS_UP_carry are generated for the up-counting unit to perform carry operations.

[0113] Please see Figure 11 , Figure 11 This is a schematic diagram of an upward-downward carry-capable counting mode provided by an embodiment of the present invention. First mode selection switches 1, 2, and 3 are enabled, while a second mode selection switch is disabled. The direction of the carry count is controlled by external input signals SELN and SELP. When SELN is low and SELP is high, the upward counting unit acts as the master counter, and the downward counting unit acts as the carry counter; when SELN is high and SELP is low, the downward counting unit acts as the master counter, and the upward counting unit acts as the carry counter. This mode is equivalent to cascading analog counting units, expanding the counting range of the analog counters and contributing to the research of high dynamic range analog front-end circuits for lidar.

[0114] Please see Figure 12 , Figure 12 This is an internal signal timing diagram of an up-and-down carry-capable counting mode provided in an embodiment of the present invention. In this mode, the up-counting unit acts as the main counter, and the down-counting unit acts as the carry counter. After the up-counting unit's output OUT_UP reaches the counting threshold, it generates a reset signal RST_CAP_P and carry signals TRIG_DN_carry and DIS_DN_carry. The up-counting unit restarts counting after being reset, while the down-counting unit performs carry counting, with the carry count result being OUT_DN.

[0115] Please see Figure 13 , Figure 13This is a schematic diagram of an upward / downward differential counting mode provided by an embodiment of the present invention. In this mode, the second mode selection switch is on, and the first mode selection switches 1, 2, and 3 are off. The upward counting unit and the downward counting unit share the same counting MOS capacitor C2, whose initial voltage value after reset is VM_UP. CLK_UP and CLK_DN ​​are clock enable signals; upward counting occurs when CLK_UP is enabled, and downward counting occurs when CLK_DN ​​is enabled. The clock enable signals CLK_UP and CLK_DN ​​do not overlap, so there is no simultaneous upward and downward counting within any given time period. Ultimately, upward / downward differential counting is achieved, and the counting output is OUT_UP. Therefore, the difference is OUT_UP - VM_UP.

[0116] Please see Figure 14 , Figure 14 This is an internal signal timing diagram of an upward / downward differential counting mode provided in an embodiment of the present invention. In this mode, the step size for upward counting and downward counting is the same, the counting output result is OUT_UP, and the difference in counts is negative.

[0117] This invention relates to a high-precision multi-mode analog counter for lidar. A switched-capacitor comparator is introduced to monitor the amount of charge released during each count. Once a set threshold is exceeded, the charge is fed back to the circuit switch to precisely control the counting step size. The counting step size is not affected by the threshold voltage of the MOS device, resulting in small process deviations. The switched-capacitor comparator provides low power consumption and high accuracy, achieving high-precision analog counting with adjustable step size.

[0118] To better perform on-chip data processing for the LiDAR, an upward counting unit was added in addition to the downward counting unit. Through a mode selection switch, it is possible to achieve upward-down or downward-up carry-able counting mode and upward / down difference counting mode, thus realizing a multi-mode analog counter. The multi-mode counter can better support the intra-pixel operation of the LiDAR chip.

[0119] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-precision multi-mode analog counter applied to a laser radar, characterized in that, The up-counting unit, the down-counting unit, the up-counting logic unit, the down-counting logic unit, the first mode selection switch 1, the first mode selection switch 2 and the second mode selection switch are connected, wherein The up-counting unit is connected with the up-counting logic unit and the down-counting logic unit, can count up the input digital pulse, and generates a reset signal through the up-counting logic unit to reset the counting MOS capacitor of the up-counting unit, and generates a carry signal for the down-counting unit to count by carry; The down-counting unit is connected with the up-counting logic unit and the down-counting logic unit, can count down the input digital pulse, and generates a reset signal through the down-counting logic unit to reset the counting MOS capacitor of the down-counting unit, and generates a carry signal for the up-counting unit to count by carry; The up-counting unit is connected between the first mode selection switch 1 and the second mode selection switch, and the down-counting unit is connected between the second mode selection switch and the first mode selection switch 2; the first mode selection switch 1 and the first mode selection switch 2 have the same switch state, and the first mode selection switch 1 and the second mode selection switch are complementary switches and have opposite switch states.

2. The high precision multi-mode analog counter for use in a lidar according to claim 1, characterized in that, The up-counting unit comprises a data selector MUX1, a data selector MUX2, a data selector MUX3, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, an OR gate OR1, a PMOS tube MD1, a PMOS tube MT1, a PMOS tube ME1, a PMOS tube MF1, a counting MOS capacitor C1, a MOS capacitor CP1, a switched capacitor comparator COMP_UP and an NMOS tube NM1, wherein The first input end of the data selector MUX1 inputs an externally provided TRIG_UP signal, and the second input end inputs a carry signal TRIG_UP_carry generated by the down-counting logic unit, and the output end of the data selector MUX1 is connected with the first input end of the OR gate OR1; the first input end of the data selector MUX2 inputs an externally provided DIS_UP signal, and the second input end inputs a DIS_UP_carry signal generated by the down-counting logic unit, and the output end of the data selector MUX2 is connected with the gate of the PMOS tube MD1; the control ends of the data selector MUX1 and the data selector MUX2 both input an external control signal SELP; The source of the PMOS tube MD1 is connected with a power supply end VDD, and the drain of the PMOS tube MD1 is simultaneously connected with the source of the MOS capacitor CP1, the drain of the MOS capacitor CP1, the source of the PMOS tube MT1 and the first input end of the switched capacitor comparator COMP_UP; the gate of the MOS capacitor CP1 is connected with a ground end GND; An input terminal of the inverter INV1 inputs a clock enable signal CLK_UP, an output terminal of the inverter INV1 is connected to a second input terminal of the OR gate OR1, an output terminal of the OR gate OR1 is connected to a gate of the PMOS transistor MT1, an input terminal of the inverter INV2 is connected to the output terminal of the OR gate OR1, and an output terminal of the inverter INV2 is connected to a gate of the PMOS transistor ME1; a drain of the PMOS transistor MT1 is connected to a source of the PMOS transistor ME1, a drain of the PMOS transistor ME1 and a source of the PMOS transistor MF1; a second input of the switch capacitor comparator COMP_UP inputs a reference threshold voltage VT V_UP, the inverter INV3, the inverter INV4 and the inverter INV5 are connected in series between an output of the switch capacitor comparator COMP_UP and a gate of the PMOS tube MF1; A drain of the PMOS transistor MF1 is connected to a gate of the counting MOS capacitor C1, a drain of the NMOS transistor NM1, a first mode selection switch 1 and a second mode selection switch, a source and a drain of the counting MOS capacitor C1 are connected to a power supply terminal VDD, a source of the NMOS transistor NM1 inputs an externally provided VM_UP signal, a gate of the NMOS transistor NM1 is connected to an output terminal of the data selector MUX3, two input terminals of the data selector MUX3 input a global reset signal RST and a RST_CAP_P generated by the down counting logic unit respectively, and a control terminal of the data selector MUX3 inputs a mode selection signal mode.

3. The high precision multi-mode analog counter for use in a lidar according to claim 2, characterized in that, The up counting logic unit comprises a PMOS transistor MP1, an NMOS transistor MC1, an inverter INV6, an inverter INV7, an inverter INV8, an inverter INV9, an inverter INV10, an inverter INV11, a D flip-flop DFF1, an AND gate AND1, an AND gate AND2, an AND gate AND3, an OR gate OR2, a delay line D1, a delay line D2 and a delay line D3, wherein, A source of the PMOS transistor MP1 is connected to a power supply terminal VDD, a gate of the PMOS transistor MP1 is connected to an output terminal of the AND gate AND3, a drain of the PMOS transistor MP1 is connected to a drain of the NMOS transistor MC1, a gate of the NMOS transistor MC1 is connected to a first mode selection switch 1, and a source of the NMOS transistor MC1 inputs an externally provided signal VT_UP; The inverter INV6, the inverter INV7 and the inverter INV8 are connected in series between the drain of the PMOS transistor MP1 and a clock pulse input terminal of the D flip-flop DFF1, a D terminal of the D flip-flop DFF1 is connected to a power supply terminal VDD, and a Q terminal of the D flip-flop DFF1 is connected to a second input terminal of the OR gate OR2; A first input terminal of the AND gate AND1 inputs a global reset signal RSTN, a second input terminal of the AND gate AND1 is connected to an output terminal of the AND gate AND3, an output terminal of the AND gate AND1 is connected to a first input terminal of the AND gate AND2, the delay line D1 and the inverter INV9 are connected in series between the Q terminal of the D flip-flop DFF1 and a second input terminal of the AND gate AND2, and an output terminal of the AND gate AND2 is connected to an R terminal of the D flip-flop DFF1. The first input end of the OR gate OR2 inputs a global reset signal RST, and the output end of the OR gate OR2 outputs an RST_CAP_P signal connected to one input end of the data selector MUX3. The delay line D2 and the inverter INV10 are connected in series between the Q end of the D flip-flop DFF1 and the first input end of the AND gate AND3, and the second input end of the AND gate AND3 inputs a global reset signal RSTN; The input end of the inverter INV11 is connected to the output end of the inverter INV10, the output end of the inverter INV11 is connected to the delay line D3, and the delay line D3 outputs a signal DIS_DN_carry.

4. The high precision multi-mode analog counter for use in a lidar according to claim 3, characterized in that, The signal RST and the signal RSTN are both externally provided signals and are logically opposite signals.

5. The high precision multi-mode analog counter for use in a lidar according to claim 3, wherein, The downward counting unit comprises an inverter INV12, an inverter INV13, an inverter INV14, an NMOS tube MD2, an NMOS tube MT2, an NMOS tube ME2, an NMOS tube MF2, a counting MOS capacitor C2, a MOS capacitor CP2, a switched capacitor comparator COMP_DN, a PMOS tube PM1, an AND gate AND4, a data selector MUX4, a data selector MUX5, a data selector MUX6 and a first mode selection switch 3, wherein, The inverter INV12 and the inverter INV13 are connected in series between the output end of the switched capacitor comparator COMP_DN and the gate of the NMOS tube MF2, and the source of the NMOS tube MF2 is connected to the drain of the NMOS tube ME2, the source of the NMOS tube ME2 and the drain of the NMOS tube MT2; The two input ends of the data selector MUX5 input an externally provided digital pulse signal DIS_DN signal and a carry signal DIS_DN_carry signal generated by the upward counting logic unit respectively, and the output end of the data selector MUX5 is connected to the gate of the NMOS tube MD2. The source of the NMOS tube MD2 is connected to the ground end, and the drain of the NMOS tube MD2 is connected to the source of the NMOS tube MT2. The two input ends of the data selector MUX6 input an externally provided digital pulse signal TRIG_DN signal and a carry signal TRIG_DN_carry signal generated by the upward counting logic unit respectively, and the output end of the data selector MUX6 is connected to the first input end of the AND gate AND4. The second input end of the AND gate AND4 inputs a clock enable signal CLK_DN, and the output end of the AND gate AND4 is connected to the gate of the NMOS tube MT2. The control ends of the data selector MUX5 and the data selector MUX6 both input an external control signal SELN. The source of the NMOS transistor MT2 is connected to the drain of the NMOS transistor MD2, the first input terminal of the switched capacitor comparator COMP DN and the gate of the MOS capacitor CP2, the source and the drain of the MOS capacitor CP2 are connected to the power supply terminal VDD, and the second input terminal of the switched capacitor comparator COMP DN inputs a reference threshold voltage VT provided externally. V_DN; One end of the first mode selection switch 3 is connected to the drain of the NMOS tube MF2 and the second mode selection switch, and the other end is simultaneously connected to the drain of the PMOS tube PM1, the source of the counting MOS capacitor C2, the drain of the counting MOS capacitor C2 and the first mode selection switch 2; the source of the PMOS tube PM1 inputs the VM_DN signal provided externally, and the gate of the counting MOS capacitor C2 is connected to the ground end; Two input ends of the data selector MUX4 input the RST signal and the RST_CAP_N signal from the downward counting logic unit respectively, the control end of the data selector MUX4 inputs the mode selection signal mode, and the output end of the data selector MUX6 is connected to the gate of the PMOS tube PM1.

6. The high precision multi-mode analog counter for use in a lidar according to claim 5, characterized in that, The first mode selection switch 3 has the same switch state as the first mode selection switch 1.

7. The high precision multi-mode analog counter for use in a lidar according to claim 5, wherein, The switch capacitor comparator COMP_DN includes a first MOS switch K1, a second MOS switch K2, a third MOS switch K3, a fourth MOS switch K4, a fifth MOS switch K5, an inverter INV15, an inverter INV16, an inverter INV17, a MOS capacitor C3, a MOS capacitor C4 and a MOS capacitor C5, wherein, The first end of the first MOS switch K1 serves as the first input end of the switch capacitor comparator COMP_DN, the second end of the first MOS switch K1 is connected to the gate of the MOS capacitor C3, the first end of the second MOS switch K2 serves as the second input end of the switch capacitor comparator COMP_DN, and the second end of the second MOS switch K1 is connected to the gate of the MOS capacitor C3; The source and drain of the MOS capacitor C3 are simultaneously connected to the input end of the inverter INV15, the third MOS switch K3 is connected between the input end and the output end of the inverter INV15, and the output end of the inverter INV15 is connected to the gate of the MOS capacitor C4; The source and drain of the MOS capacitor C4 are simultaneously connected to the input end of the inverter INV16, the third MOS switch K4 is connected between the input end and the output end of the inverter INV16, and the output end of the inverter INV16 is connected to the gate of the MOS capacitor C5; The source and drain of the MOS capacitor C5 are simultaneously connected to the input end of the inverter INV17, the third MOS switch K5 is connected between the input end and the output end of the inverter INV17, and the output end of the inverter INV17 serves as the output end of the switch capacitor comparator COMP_DN.

8. The high precision multi-mode analog counter for use in a lidar according to claim 7, characterized in that, When the first MOS switch K1 is disconnected, the second MOS switch K2, the third MOS switch K3, the fourth MOS switch K4 and the fifth MOS switch K5 are all connected; when the first MOS switch K1 is connected, the second MOS switch K2, the third MOS switch K3, the fourth MOS switch K4 and the fifth MOS switch K5 are all disconnected.

9. The high precision multi-mode analog counter for use in a lidar according to claim 7, characterized in that, The downward counting logic unit comprises a PMOS tube MC2, an NMOS tube NM2, an inverter INV18, an inverter INV19, an inverter INV20, an inverter INV21, an inverter INV22, a D flip-flop DFF2, an AND gate AND5, an AND gate AND6, an AND gate AND7, an OR gate OR3, a delay line D4, a delay line D5 and a delay line D6, wherein, a gate of the PMOS tube MC2 is connected with a first mode selection switch 2, a source of the PMOS tube MC2 inputs a VT_DN signal provided externally, a gate of the NMOS tube NM2 is connected with an output end of the OR gate OR3, a source of the NMOS tube NM2 is connected with a ground end, and a drain of the PMOS tube MC2 is connected with a drain of the NMOS tube NM2; the inverter INV18 and the inverter INV19 are connected in series between the drain of the PMOS tube MC2 and a clock pulse input end of the D flip-flop DFF2, a D end of the D flip-flop DFF2 is connected with a power supply end VDD, and a Q end of the D flip-flop DFF2 is connected with an input end of the inverter INV21; a first input end of the AND gate AND5 inputs a global reset signal RSTN signal, a second input end is connected between an inverter INV22 and the delay line D6, an output end of the AND gate AND5 is connected with a first input end of the AND gate AND6, the delay line D4 and the inverter INV20 are connected in series between the Q end of the D flip-flop DFF2 and a second input end of the AND gate AND6, and an output end of the AND gate AND6 is connected with an R end of the D flip-flop DFF2; an output end of the inverter INV21 is connected with a first input end of the AND gate AND7, a second input end of the AND gate AND7 inputs the global reset signal RSTN signal, and an output end of the AND gate AND7 outputs an RST_CAP_N signal and is connected with the data selector MUX4; a first end of the delay line D5 is connected with the Q end of the D flip-flop DFF2, and the other end is connected with a first input end of the OR gate OR3, and a second input end of the OR gate OR3 inputs the global reset signal RST; an input end of the inverter INV22 is connected with the first input end of the OR gate OR3, and an output end of the inverter INV22 is connected with a first end of the delay line D6, and a second end of the delay line D6 is connected with the data selector MUX2.

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