A communication method and system based on streaming DMA
By designing a streaming DMA controller and arbitrator, MAC-free Ethernet communication was achieved, solving the problems of low transmission rate and communication difficulties in the existing technology, improving data transmission efficiency and reducing development costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU EBOYLAMP ELECTRONICS CO LTD
- Filing Date
- 2023-08-09
- Publication Date
- 2026-06-26
Smart Images
Figure CN117318811B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of DMA communication, specifically relating to a communication method and system based on streaming DMA. Background Technology
[0002] The data acquisition and processing system mainly consists of two modules: a data acquisition module and a data processing module. Due to the specific application, the data acquisition module needs to be installed on a high tower, while the data processing module is located on the ground, and communication between the two modules relies solely on a single fiber optic link. The tower-mounted data acquisition module acquires high-speed data and transmits it via fiber optic cable to the ground-based data processing module for processing and storage. Because maintaining the tower equipment is difficult, ground-based control commands, program updates, and remote debugging are required. These functions are accomplished through communication between the CPUs of the two modules, and this inter-CPU communication data stream also requires the use of the single fiber optic link. Figure 1 As shown.
[0003] Existing CPU-to-CPU communication requires custom-developed drivers and applications. To achieve CPU-to-CPU communication, a PCIe communication driver and application between the CPU and FPGA need to be developed. The FPGA uses the PCIe bus to allocate registers for the CPU to achieve data transfer between the FPGA and CPU within the module. The driver needs to provide a custom register read / write interface, and the application encapsulates a custom protocol according to functional requirements. Commonly used software tools (such as SSH, Telnet, etc.) cannot be used, requiring additional software development. This results in a high degree of application customization, poor software scalability, and low register access and transfer rates. If FPGA MAC and PHYIP cores are used to implement CPU-to-CPU Ethernet communication, this network communication must occupy a dedicated network link. Since this data processing system only has one fiber optic link, and both CPU-to-CPU communication and high-speed data flow must be transmitted through this single fiber optic link, FPGA MAC and PHYIP cores cannot be used. Summary of the Invention
[0004] The purpose of this invention is to address the problems mentioned in the background art by proposing a communication method and system based on streaming DMA.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:
[0006] This invention proposes a communication method based on streaming DMA, applied to communication between a transmitter and a receiver. The transmitter and receiver are connected via an optical fiber link. The transmitter includes a first CPU module and a first FPGA module. The first FPGA module includes a first acquisition module, a first FIFO, a first arbitrator, a second FIFO, and a first streaming DMA controller. The receiver includes a second CPU module and a second FPGA module. The second FPGA module includes a third FIFO, a second arbitrator, a fourth FIFO, and a second streaming DMA controller. The communication method based on streaming DMA includes:
[0007] When the sending end sends data, the first acquisition module acquires high-speed data from the outside and stores it in the first FIFO;
[0008] The first streaming DMA controller moves the Ethernet data from the first CPU module to the second FIFO;
[0009] The first arbitrator sends the data from the first FIFO and the second FIFO to the optical fiber link and transmits them to the receiving end through the optical module.
[0010] When the receiving end receives data, the second arbitrator will parse the high-speed data and Ethernet data from the data received from the fiber optic link and store them in the third FIFO and the fourth FIFO respectively; and the high-speed data stored in the third FIFO will be processed by the second FPGA module.
[0011] The second streaming DMA controller moves the Ethernet data in the fourth FIFO to the second CPU module.
[0012] Preferably, the first streaming DMA controller transfers Ethernet data from the first CPU module to the second FIFO, including:
[0013] The first CPU module includes a first virtual network card driver, a first operating system network protocol stack, and a first application program;
[0014] The first application generates Ethernet data, which is transmitted to the first virtual network card driver through the first operating system network protocol stack. Then, the streaming DMA controller moves the Ethernet data on the first virtual network card driver to the second FIFO. The first arbitrator sends the data on each FIFO to the fiber optic link and transmits it to the receiving end.
[0015] Preferably, the second streaming DMA controller transfers Ethernet data from the fourth FIFO to the second CPU module, including:
[0016] The second CPU module includes a second virtual network card driver, a second operating system network protocol stack, and a second application.
[0017] The Ethernet data stored in the fourth FIFO is transferred by the second streaming DMA controller to the second virtual network card driver. The second virtual network card driver then transmits the received Ethernet data to the second application through the second operating system network protocol stack.
[0018] Preferably, the streaming DMA controller then moves the Ethernet data from the first virtual network card driver to the second FIFO, including:
[0019] The first virtual network card driver sets the bus address and length of the received Ethernet data in the descriptor of the first streaming DMA controller. The first streaming DMA controller reads the data from the first virtual network card driver according to the bus address and length in the descriptor and stores it in the second FIFO.
[0020] Preferably, the Ethernet data stored in the fourth FIFO is transferred to the second virtual network card driver by the second streaming DMA controller, including:
[0021] The second virtual network interface card driver sets the bus address and length in the descriptor of the second streaming DMA controller, and the second streaming DMA controller writes Ethernet data to the second virtual network interface card driver according to the bus address in the descriptor.
[0022] A communication system based on streaming DMA includes a transmitter and a receiver connected via an optical fiber link. The transmitter includes a first CPU module and a first FPGA module. The first FPGA module includes a first acquisition module, a first FIFO, a first arbitrator, a second FIFO, and a first streaming DMA controller. The receiver includes a second CPU module and a second FPGA module. The second FPGA module includes a third FIFO, a second arbitrator, a fourth FIFO, and a second streaming DMA controller. A communication method based on streaming DMA includes:
[0023] When the sending end sends data, the first acquisition module is used to acquire high-speed data from the outside and store it in the first FIFO;
[0024] The first streaming DMA controller is used to transfer Ethernet data from the first CPU module to the second FIFO;
[0025] The first arbitrator is used to send the data in the first FIFO and the second FIFO to the optical fiber link and transmit them to the receiving end through the optical module.
[0026] When the receiving end receives data, the second arbitrator is used to parse the high-speed data and Ethernet data from the data received from the fiber optic link and store them into the third FIFO and the fourth FIFO respectively; and the high-speed data stored in the third FIFO is processed by the second FPGA module.
[0027] The second streaming DMA controller is used to transfer Ethernet data from the fourth FIFO to the second CPU module.
[0028] Preferably, when the first streaming DMA controller moves the Ethernet data from the first CPU module to the second FIFO, it performs the following operations:
[0029] The first CPU module includes a first virtual network card driver, a first operating system network protocol stack, and a first application program;
[0030] The first application generates Ethernet data, which is transmitted to the first virtual network card driver through the first operating system network protocol stack. Then, the streaming DMA controller moves the Ethernet data on the first virtual network card driver to the second FIFO. The first arbitrator sends the data on each FIFO to the fiber optic link and transmits it to the receiving end.
[0031] Preferably, when the second streaming DMA controller transfers Ethernet data from the fourth FIFO to the second CPU module, it performs the following operations:
[0032] The second CPU module includes a second virtual network card driver, a second operating system network protocol stack, and a second application.
[0033] The Ethernet data stored in the fourth FIFO is transferred by the second streaming DMA controller to the second virtual network card driver. The second virtual network card driver then transmits the received Ethernet data to the second application through the second operating system network protocol stack.
[0034] Preferably, when the streaming DMA controller moves the Ethernet data from the first virtual network card driver to the second FIFO, it performs the following operations:
[0035] The first virtual network card driver sets the bus address and length of the received Ethernet data in the descriptor of the first streaming DMA controller. The first streaming DMA controller reads the data from the first virtual network card driver according to the bus address and length in the descriptor and stores it in the second FIFO.
[0036] Preferably, when the Ethernet data stored in the fourth FIFO is transferred from the second streaming DMA controller to the second virtual network card driver, the following operations are performed:
[0037] The second virtual network interface card driver sets the bus address and length in the descriptor of the second streaming DMA controller, and the second streaming DMA controller writes Ethernet data to the second virtual network interface card driver according to the bus address in the descriptor.
[0038] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0039] This invention is based on streaming DMA to realize a MAC-free Ethernet communication method. This network data stream can reuse a single fiber optic link with other types of data streams, and the access speed of streaming DMA is greatly improved. It solves the problem of low transmission rate when accessing via registers in the prior art. At the same time, this invention does not require drivers to provide customized register read and write interfaces, does not require applications to encapsulate custom protocols according to functional needs, and does not require additional development tools, thus greatly reducing costs. Attached Figure Description
[0040] Figure 1 This is the communication method between CPU modules in the prior art of this invention;
[0041] Figure 2 This is a block diagram of the communication method based on streaming DMA of the present invention;
[0042] Figure 3 This is a schematic diagram of the architecture of the virtual network card driver of the present invention;
[0043] Figure 4 This is a schematic diagram of the Ethernet data transmission process of the present invention;
[0044] Figure 5 This is a schematic diagram of the Ethernet data receiving process of the present invention. Detailed Implementation
[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0046] It should be noted that when a component is referred to as being "connected" to another component, it can be directly connected to the other component or there may be an intervening component. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to limit the application.
[0047] In one embodiment, such as Figure 2As shown, a communication method based on streaming DMA is applied to communication between a transmitter and a receiver. The transmitter and receiver are connected via an optical fiber link. The transmitter includes a first CPU module and a first FPGA module. The first FPGA module includes a first acquisition module, a first FIFO, a first arbitrator, a second FIFO, and a first streaming DMA controller. The receiver includes a second CPU module and a second FPGA module. The second FPGA module includes a third FIFO, a second arbitrator, a fourth FIFO, and a second streaming DMA controller. The communication method based on streaming DMA includes:
[0048] When the sending end sends data, the first acquisition module acquires high-speed data and stores it in the first FIFO.
[0049] The first streaming DMA controller moves the Ethernet data from the first CPU module to the second FIFO, specifically including:
[0050] The first CPU module includes a first virtual network card driver, a first operating system network protocol stack, and a first application program;
[0051] The first application generates Ethernet data, which is transmitted to the first virtual network card driver via the first operating system network protocol stack. Then, the first streaming DMA controller moves the Ethernet data on the first virtual network card driver to the second FIFO. The first arbitrator sends the data on each FIFO to the fiber optic link and transmits it to the receiving end.
[0052] Specifically, the first streaming DMA controller moves Ethernet data from the first virtual network card driver to the second FIFO, including:
[0053] The first virtual network card driver sets the bus address and length of the received Ethernet data in the descriptor of the first streaming DMA controller. The first streaming DMA controller reads the data from the first virtual network card driver according to the bus address and length in the descriptor and stores it in the second FIFO.
[0054] The first arbitrator sends the data from both the first and second FIFOs to the fiber optic link via the optical module and transmits it to the receiving end.
[0055] When the receiving end receives data, the second arbitrator will parse the high-speed data and Ethernet data from the data received from the fiber optic link and store them in the third FIFO and the fourth FIFO respectively; and the high-speed data stored in the third FIFO will be processed by the second FPGA module.
[0056] The second streaming DMA controller transfers Ethernet data from the fourth FIFO to the second CPU module, specifically including:
[0057] The second CPU module includes a second virtual network card driver, a second operating system network protocol stack, and a second application.
[0058] The Ethernet data stored in the fourth FIFO is transferred by the second streaming DMA controller to the second virtual network card driver. The second virtual network card driver then transmits the received Ethernet data to the second application through the second operating system network protocol stack.
[0059] The Ethernet data stored in the fourth FIFO is transferred to the second virtual network card driver by the second streaming DMA controller, including:
[0060] The second virtual network interface card driver sets the bus address and length in the descriptor of the second streaming DMA controller, and the second streaming DMA controller writes Ethernet data to the second virtual network interface card driver according to the bus address in the descriptor.
[0061] It should be noted that the first and second FPGA modules transmit data via the Aurora protocol. The first CPU module and the first FPGA module, as well as the second CPU module and the second FPGA module, can be connected via a PCIe bus or other buses. The streaming DMA controller in each FPGA module uses the FPGA module's XDMAIP core. The first operating system network protocol stack requests a first socket buffer, the first virtual network card driver releases the data in the first socket buffer, and the second virtual network card driver requests a second socket buffer. The second operating system network protocol stack releases the data in the second socket buffer. The XDMAIP core of the first FPGA module converts the data in the first socket buffer into a data stream, which is then sent to the first FPGA module via the first virtual network card driver. The data is then sent to the receiving optical module via the optical module. The receiving optical module sends the received data stream to the second FPGA module, where the XDMAIP core moves the data to the second socket buffer, thus enabling interaction between each FPGA module and its corresponding CPU module. The first arbitrator adds header information to the data in the first and second FIFOs and sends the data in chronological order. The second arbitrator parses the high-speed data and Ethernet data based on the packet header information.
[0062] It should be noted that each virtual network card driver initializes the corresponding streaming DMA controller, that is, each virtual network card driver sets the bus address and length in the descriptor of the corresponding streaming DMA controller.
[0063] The architecture of each virtual network adapter driver is as follows: Figure 3As shown, the system comprises a network protocol interface layer, a network device interface layer, and a device driver function layer. The network protocol interface layer provides a unified send / receive interface to the network device interface layer, sending data through the `dev_queue_xmit()` function and receiving data through the `netif_rx()` function, using a pointer to a `struct sk_buffer` data structure to the socket buffer. The network device interface layer uses the `net_device` structure to provide a unified interface to the network protocol interface layer for describing network device attributes and planning the functional interfaces that the device driver function layer needs to implement. The device driver function layer provides the specific implementation of the functional interfaces defined by `net_device`, handling the reception of Ethernet data frames through the `dma_start_xmit()` function (sending Ethernet data frames) and interrupt service routines of the streaming DMA controller.
[0064] like Figure 4 As shown, the Ethernet data transmission process is as follows:
[0065] Firstly, in the five-layer protocol of the TCP / IP network model (application layer, transport layer, network layer, data link layer, and physical layer), the data link layer and physical layer of the TCP / IP network model have been modified, and the drivers of each virtual network card are located in the data link layer;
[0066] The network layer sends data packets by calling the dev_queue_xmit(skb) interface, with the socket buffer pointer skb as the function parameter;
[0067] Call the network device interface layer operation ndev_device->netdev_ops.ndo_start_xmit(skb, dev);
[0068] The ndo_start_xmit() interface is initialized as a DMA send function during the initialization of the virtual network card driver, that is, calling dma_start_xmit(skb) to send network packet data through the streaming DMA controller;
[0069] dma_start_xmit first converts the skb->data data segment address to the PCIe bus address, which is the PCIe bus address of the memory where the network packet data is located;
[0070] Fill the bus address and length of the first socket buffer into the descriptor of the first streaming DMA controller;
[0071] The first streaming DMA controller is started to read. The first streaming DMA controller converts the network packet data in the first socket buffer into a data stream according to the bus address and length in the descriptor and sends it to the optical module to be sent to the receiving end.
[0072] like Figure 5 As shown, the Ethernet data reception process is as follows:
[0073] When the second FPGA module receives a network data packet, it stores it in the fourth FIFO;
[0074] The bus address and length of the second socket buffer are filled into the descriptor of the second streaming DMA controller;
[0075] Initiate the second streaming DMA controller to write; the second streaming DMA controller moves network packets to the socket buffer specified by the descriptor.
[0076] Then the second FPGA module triggers the MSI-X interrupt service function, and all network data packets are sent to the second socket buffer through the second CPU module.
[0077] The interrupt service routine requests a new socket buffer skb_buffer, converts the skb->data data segment address into a PCIe bus address, and updates the descriptor of the second streaming DMA controller for the next transfer by the second streaming DMA controller.
[0078] The interrupt service function calls the netif_rx(skb) function to pass the received network data to the network layer, completing the reception of the network data packet.
[0079] In terms of hardware, each CPU module uses a Phytium D2000-8 domestic processor, and each FPGA module uses a Xilinx FPGAV7. In terms of software, each FPGA module logically instantiates one PCIe Endpoint. The FPGA module receives network data and inputs it into the corresponding FIFO, and uses an XDMA core as the DMA controller. The D2000-8 runs the domestic Kylin V10 desktop Linux operating system and deploys a MAC-free streaming DMA virtual network card driver, which can abstract a network card device within the system. Network communication functions are tested using the iperf3 network performance testing tool and SSH service software.
[0080] The effect is as follows:
[0081] The TCP network bandwidth was tested and found to reach 900 Mbits / sec.
[0082] UDP network bandwidth can reach 800 Mbits / sec, with latency jitter of less than 0.01 ms.
[0083] Telnet and SSH can be used to log in to each other, and TFTP and SFTP can transfer files correctly between boards.
[0084] In another embodiment, a streaming DMA-based communication system includes a transmitter and a receiver connected via an optical fiber link. The transmitter includes a first CPU module and a first FPGA module. The first FPGA module includes a first acquisition module, a first FIFO, a first arbitrator, a second FIFO, and a first streaming DMA controller. The receiver includes a second CPU module and a second FPGA module. The second FPGA module includes a third FIFO, a second arbitrator, a fourth FIFO, and a second streaming DMA controller. The streaming DMA-based communication method includes:
[0085] When the sending end sends data, the first acquisition module is used to acquire high-speed data from the outside and store it in the first FIFO;
[0086] The first streaming DMA controller is used to transfer Ethernet data from the first CPU module to the second FIFO;
[0087] The first arbitrator is used to send the data in the first FIFO and the second FIFO to the optical fiber link and transmit them to the receiving end through the optical module.
[0088] When the receiving end receives data, the second arbitrator is used to parse the high-speed data and Ethernet data from the data received from the fiber optic link and store them into the third FIFO and the fourth FIFO respectively; and the high-speed data stored in the third FIFO is processed by the second FPGA module.
[0089] The second streaming DMA controller is used to transfer Ethernet data from the fourth FIFO to the second CPU module.
[0090] In this embodiment, when the first streaming DMA controller moves the Ethernet data from the first CPU module to the second FIFO, it performs the following operations:
[0091] The first CPU module includes a first virtual network card driver, a first operating system network protocol stack, and a first application program;
[0092] The first application generates Ethernet data, which is transmitted to the first virtual network card driver through the first operating system network protocol stack. Then, the streaming DMA controller moves the Ethernet data on the first virtual network card driver to the second FIFO. The first arbitrator sends the data on each FIFO to the fiber optic link and transmits it to the receiving end.
[0093] In this embodiment, when the second streaming DMA controller transfers Ethernet data from the fourth FIFO to the second CPU module, it performs the following operations:
[0094] The second CPU module includes a second virtual network card driver, a second operating system network protocol stack, and a second application.
[0095] The Ethernet data stored in the fourth FIFO is transferred by the second streaming DMA controller to the second virtual network card driver. The second virtual network card driver then transmits the received Ethernet data to the second application through the second operating system network protocol stack.
[0096] In this embodiment, when the streaming DMA controller moves the Ethernet data from the first virtual network card driver to the second FIFO, it performs the following operations:
[0097] The first virtual network card driver sets the bus address and length of the received Ethernet data in the descriptor of the first streaming DMA controller. The first streaming DMA controller reads the data from the first virtual network card driver according to the bus address and length in the descriptor and stores it in the second FIFO.
[0098] In this embodiment, when the Ethernet data stored in the fourth FIFO is transferred from the second streaming DMA controller to the second virtual network card driver, the following operations are performed:
[0099] The second virtual network interface card driver sets the bus address and length in the descriptor of the second streaming DMA controller, and the second streaming DMA controller writes Ethernet data to the second virtual network interface card driver according to the bus address in the descriptor.
[0100] It should be noted that the limitations on the method in this invention also apply to the limitations on the system, and will not be described again.
[0101] This invention is based on streaming DMA to realize a MAC-free Ethernet communication method. This network data stream can reuse a single fiber optic link with other types of data streams, and the access speed of streaming DMA is greatly improved. It solves the problem of low transmission rate when accessing via registers in the prior art. At the same time, this invention does not require drivers to provide customized register read and write interfaces, does not require applications to encapsulate custom protocols according to functional needs, and does not require additional development tools, thus greatly reducing costs.
[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0103] The embodiments described above are merely specific and detailed examples of the embodiments described in this application, and should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the appended claims.
Claims
1. A communication method based on streaming DMA, applied to communication between a transmitter and a receiver, wherein the transmitter and receiver are connected via an optical fiber link, characterized in that: The transmitting end includes a first CPU module and a first FPGA module. The first FPGA module includes a first acquisition module, a first FIFO, a first arbitrator, a second FIFO, and a first streaming DMA controller. The receiving end includes a second CPU module and a second FPGA module. The second FPGA module includes a third FIFO, a second arbitrator, a fourth FIFO, and a second streaming DMA controller. The communication method based on streaming DMA includes: When the transmitting end sends data, the first acquisition module acquires high-speed data from the outside and stores it in the first FIFO; The first streaming DMA controller moves the Ethernet data from the first CPU module to the second FIFO; The first arbitrator sends the data from both the first FIFO and the second FIFO to the optical fiber link via the optical module and transmits it to the receiving end. When the receiving end receives data, the second arbitrator parses the high-speed data and Ethernet data from the data received from the fiber optic link and stores them into the third FIFO and the fourth FIFO, respectively; and the high-speed data stored in the third FIFO is processed by the second FPGA module. The second streaming DMA controller transfers the Ethernet data in the fourth FIFO to the second CPU module; The first streaming DMA controller transfers Ethernet data from the first CPU module to the second FIFO, including: The first CPU module includes a first virtual network card driver, a first operating system network protocol stack, and a first application program; The first application generates Ethernet data, which is transmitted to the first virtual network card driver through the first operating system network protocol stack. Then, the streaming DMA controller moves the Ethernet data on the first virtual network card driver to the second FIFO. The first arbitrator sends the data on each FIFO to the optical fiber link and transmits it to the receiving end. The second streaming DMA controller transfers Ethernet data from the fourth FIFO to the second CPU module, including: The second CPU module includes a second virtual network card driver, a second operating system network protocol stack, and a second application. The Ethernet data stored in the fourth FIFO is transferred by the second streaming DMA controller to the second virtual network card driver, and the second virtual network card driver transmits the received Ethernet data to the second application through the second operating system network protocol stack.
2. The communication method based on streaming DMA as described in claim 1, characterized in that: The streaming DMA controller then moves the Ethernet data from the first virtual network card driver to the second FIFO, including: The first virtual network card driver sets the bus address and length of the received Ethernet data in the descriptor of the first streaming DMA controller. The first streaming DMA controller reads the data from the first virtual network card driver according to the bus address and length in the descriptor and stores it in the second FIFO.
3. The communication method based on streaming DMA as described in claim 1, characterized in that: The Ethernet data stored in the fourth FIFO is transferred to the second virtual network card driver by the second streaming DMA controller, including: The second virtual network interface card driver sets the bus address and length in the descriptor of the second streaming DMA controller, and the second streaming DMA controller writes Ethernet data to the second virtual network interface card driver according to the bus address in the descriptor.
4. A communication system based on streaming DMA, comprising a transmitter and a receiver connected via an optical fiber link, characterized in that: The transmitting end includes a first CPU module and a first FPGA module. The first FPGA module includes a first acquisition module, a first FIFO, a first arbiter, a second FIFO, and a first streaming DMA controller. The receiving end includes a second CPU module and a second FPGA module. The second FPGA module includes a third FIFO, a second arbiter, a fourth FIFO, and a second streaming DMA controller. The communication process based on streaming DMA includes: When the transmitting end sends data, the first acquisition module is used to acquire high-speed data from the outside and store it in the first FIFO; The first streaming DMA controller is used to transfer Ethernet data from the first CPU module to the second FIFO; The first arbiter is used to send the data in the first FIFO and the second FIFO to the optical fiber link and transmit them to the receiving end through the optical module. When the receiving end receives data, the second arbitrator is used to parse high-speed data and Ethernet data from the data received from the fiber optic link and store them into the third FIFO and the fourth FIFO respectively; and the high-speed data stored in the third FIFO is processed by the second FPGA module. The second streaming DMA controller is used to transfer Ethernet data from the fourth FIFO to the second CPU module; When the first streaming DMA controller moves the Ethernet data from the first CPU module to the second FIFO, it performs the following operations: The first CPU module includes a first virtual network card driver, a first operating system network protocol stack, and a first application program; The first application generates Ethernet data, which is transmitted to the first virtual network card driver through the first operating system network protocol stack. Then, the streaming DMA controller moves the Ethernet data on the first virtual network card driver to the second FIFO. The first arbitrator sends the data on each FIFO to the optical fiber link and transmits it to the receiving end. When the second streaming DMA controller moves Ethernet data from the fourth FIFO to the second CPU module, it performs the following operations: The second CPU module includes a second virtual network card driver, a second operating system network protocol stack, and a second application. The Ethernet data stored in the fourth FIFO is transferred by the second streaming DMA controller to the second virtual network card driver, and the second virtual network card driver transmits the received Ethernet data to the second application through the second operating system network protocol stack.
5. The communication system based on streaming DMA as described in claim 4, characterized in that: When the streaming DMA controller then moves the Ethernet data from the first virtual network card driver to the second FIFO, it performs the following operations: The first virtual network card driver sets the bus address and length of the received Ethernet data in the descriptor of the first streaming DMA controller. The first streaming DMA controller reads the data from the first virtual network card driver according to the bus address and length in the descriptor and stores it in the second FIFO.
6. The communication system based on streaming DMA as described in claim 4, characterized in that: When the Ethernet data stored in the fourth FIFO is transferred from the second streaming DMA controller to the second virtual network card driver, the following operations are performed: The second virtual network interface card driver sets the bus address and length in the descriptor of the second streaming DMA controller, and the second streaming DMA controller writes Ethernet data to the second virtual network interface card driver according to the bus address in the descriptor.