An i2c bus extension system and method
The hierarchical expansion architecture configured with main controller, I2C multiplexer, and GPIO enables three-level composite addressing of sensors, resolves I2C address conflicts, significantly expands system capacity, and improves data acquisition efficiency and access speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI IND U TECH RES INST
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-09
Smart Images
Figure CN122173428A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of computer communication technology, and in particular relates to an I2C bus expansion system and method. Background Technology
[0002] In sensor manufacturing, final quality assurance (QA) is a crucial step in ensuring product performance consistency and reliability. According to relevant national standards, when the batch size reaches 501-1200 units, a general inspection level II is used, requiring 80 samples for testing. When the batch size increases to 3201-10000 units, the sampling number increases to 125. QA testing needs to systematically verify multiple key indicators such as accuracy, sensitivity, response time, and stability. Among these, the reliability and efficiency of "sensor data communication" are the core and challenge in achieving automated batch testing.
[0003] Currently, most sensors use the I2C bus protocol to interact with host computers. However, in actual QA testing, two major challenges are faced: First, sensors produced in the same batch often have fixed and identical I2C device addresses at the factory, lacking unique identifiers. This inevitably leads to address conflicts when multiple sensors are connected to the same bus, causing data reading chaos. Second, the physical I2C interface and general-purpose input / output pin resources of the host computer or main control unit are limited, making it difficult to directly meet the data acquisition needs of parallel or rapid polling read / write operations on 80 or even hundreds of sampled sensors. Therefore, how to effectively expand the I2C bus device capacity and achieve conflict-free and efficient data acquisition under limited main control resources has become a key technical bottleneck for improving QA testing efficiency and accuracy.
[0004] To address the problems existing in the current technology, a new I2C bus expansion method needs to be developed to improve the device capacity of the I2C bus under limited master control resources, enabling efficient data acquisition from slave devices such as sensors. Summary of the Invention
[0005] This invention provides an I2C bus expansion system and method, which effectively expands the device capacity of the I2C bus and improves the data acquisition efficiency of slave devices.
[0006] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.
[0007] To achieve one or more of the above objectives or other objectives, the present invention provides an I2C bus expansion system, comprising: a master controller; at least one I2C multiplexer communicating with the master controller via an I2C bus, each of the I2C multiplexers having a unique device address, multiple independent channels, and at least one GPIO output pin; multiple slave devices connected to each independent channel, and the address selection pin of each slave device being connected to the corresponding GPIO output pin of the corresponding channel; the master controller selecting to open the independent channel of the I2C multiplexer based on a control signal from a host computer, and selecting the corresponding slave device based on the GPIO output pin after the independent channel is opened.
[0008] The I2C multiplexer is equipped with multiple electronic switches. The main controller transmits clock signals and data signals to the I2C multiplexer via the I2C bus. The multiple electronic switches selectively distribute the clock signals and data signals sent by the main controller to each independent channel.
[0009] The I2C multiplexer is also equipped with a channel selection control module, which controls the opening and closing of the electronic switch corresponding to each independent channel.
[0010] Another technical solution of the present invention provides an I2C bus expansion method, using the I2C bus expansion system described above. The method includes: after the system is powered on, the master controller initiates an I2C start signal and sends an address signal to the I2C multiplexer; the I2C multiplexer parses the address signal, and when the address signal matches, the master controller sends a channel selection code and a GPIO switching code to the designated I2C multiplexer; the channel selection code specifies the independent channel that needs to be activated inside the I2C multiplexer, and the GPIO switching code is used to select the slave device node connected to the independent channel; after the I2C multiplexer confirms that the channel selection code and GPIO switching code are configured successfully, the master controller sends a slave device address, selects the target slave device on the independent channel, and reads the slave device data source.
[0011] The main controller sends a data read command, specifying the data source of the slave device to be read; after the slave device confirms the read command, it outputs the corresponding data; after receiving the data output by the slave device, the main controller sends a non-acknowledgment signal and issues a stop signal to end the data transmission.
[0012] When the channel selection code and GPIO switching code are not configured successfully, the target slave device does not respond or does not respond in a timely manner, or the slave device does not respond or does not respond in a timely manner after receiving the read command, the system prompts an error and waits for the master controller to re-initiate the I2C start signal; when the error prompts by the system occurs consecutively for more than 3 times, the electronic switch of the I2C multiplexer and the internal register of the I2C multiplexer are reset, and after a delay of 80ms-120ms, the system waits for the master controller to re-initiate the I2C start signal.
[0013] The method also includes establishing a slave device topology mapping table. The master controller performs automatic scanning, traversing the addresses of all preset I2C multiplexers, the independent channels of each I2C multiplexer, and the GPIO configuration under each independent channel. For each independent channel, it sequentially traverses all GPIO switching codes, and under each GPIO switching code, it performs communication addressing to activate each slave device and records the slave device address information. Based on the scan results, a slave device topology mapping table is created. The topology mapping table records the identifier of each slave device, the corresponding physical path information, and the slave device status. The physical path information includes: the slave device address, the channel selection code of the independent channel it belongs to, the GPIO configuration, and the address of the I2C multiplexer where the independent channel is located. Based on the address information of each slave device recorded in the topology mapping table, the master controller establishes communication with the slave device and performs data transmission with the slave device.
[0014] When the system is powered on and initialized, the main controller periodically performs an automatic scanning step or performs an automatic scan when a communication abnormality is detected during system operation, and updates the slave device topology mapping table.
[0015] The access requests of the slave devices in the slave device topology mapping table are sorted by priority. When the master controller executes slave device access, it accesses the slave devices according to the preset priority of the access requests.
[0016] Multiple slave devices configured with the same GPIO under the same channel in the slave device topology mapping table are divided into an access group. When the master controller initiates access to multiple slave devices in an access group, the master controller sends the channel selection code and GPIO switching code of the access group at one time to establish a fixed physical communication path. While maintaining the physical communication path unchanged, the master controller sends the different slave device addresses of each slave device in the access group in sequence to continuously access multiple slave devices in the access group.
[0017] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The present invention realizes a three-level composite addressing mechanism of channel selection code - GPIO switching code - slave device address through a hierarchical expansion architecture of master controller - I2C multiplexer - channel selection - GPIO configuration, which solves the problem of fixed I2C address conflict when slave devices generated in the same batch are connected to the I2C bus in the prior art, and realizes the advantages of significant system capacity expansion and flexible configuration.
[0018] 2. By creating a topology mapping table for slave devices, the physical paths of all slave devices are automatically discovered and recorded when the system is powered on. Based on this topology mapping table, all communication visitors can obtain accurate query paths, reducing the difficulty of system deployment and maintenance.
[0019] 3. Based on the created slave device topology mapping table, access priorities can be set, and access can be performed based on priorities, improving access efficiency. Simultaneously, this invention groups slave devices with the same GPIO configuration under the same channel into an access group. When accessing multiple slave devices within an access group, only one physical communication channel needs to be established, and multiple slave device addresses can be continuously sent for continuous data reading, significantly improving access speed.
[0020] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 This is a diagram of an I2C bus expansion system architecture according to the present invention.
[0023] Figure 2 This is a schematic diagram of an I2C multiplexer structure according to the present invention. Detailed Implementation
[0024] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0027] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0028] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the expectation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.
[0029] Example 1 Example 1 provides an I2C bus expansion system, such as Figure 1As shown, the I2C bus expansion system includes: a master controller; at least one I2C multiplexer, which communicates with the master controller via the I2C bus. Each I2C multiplexer has a unique device address, multiple independent channels, and at least one GPIO output pin. Each independent channel is connected to an I2C bus branch, and multiple slave devices are attached to the I2C bus branch of each independent channel. Each I2C multiplexer has at least one GPIO output pin, which is connected to the address selection pin of each slave device.
[0030] Based on the control signals from the host computer, the main controller selects and opens an independent channel of the I2C multiplexer, and after the independent channel is opened, selects the corresponding slave device based on the GPIO output pin.
[0031] The GPIO switching code (e.g., binary code, consisting of S3, S2, S1, S0) sent by the master controller can control the state of each GPIO output pin, thereby enabling precise selection of multiple slave devices on the same channel. Each slave device (e.g., a sensor) has its address selection pin or chip select enable pin connected to a GPIO output pin. When the master controller sends a specific GPIO switching code, the I2C multiplexer decodes it into the corresponding GPIO pin level (high or low). Each GPIO pin corresponds to two selection areas, and the slave device within each selection area can be selected based on its address.
[0032] The I2C bus expansion system in Example 1 connects the slave devices originally mounted on the I2C bus to various I2C bus branches. Each slave device is selected hierarchically through the master controller-I2C multiplexer-independent channel-GPIO switching code-slave device address. Therefore, multiple slave devices with the same slave device address can be mounted on different channels and selected using different GPIO pins (to distinguish slave devices). Without adding a master controller, the I2C bus mounting capability is significantly enhanced while avoiding address conflicts and data reading chaos.
[0033] For the structure of the I2C multiplexer, please refer to [link / reference]. Figure 2 The main controller is equipped with a clock interface (SCL) and a data interface (SDA). The I2C bus (including clock and data lines) connects the clock interface (SCL) and data interface (SDA) on the main controller to the corresponding interfaces on the I2C multiplexer. The I2C multiplexer is equipped with multiple electronic switches, each of which is used to selectively connect the clock signal and data signal from the main controller to each channel. Figure 2Channels 0 to 3 in the I2C bus have I2C bus branches on each channel, and the clock interface (SCL) and data interface (SDA) of each slave device are connected to the I2C bus branch.
[0034] The I2C multiplexer is equipped with a channel selection control module. The channel selection control module parses the channel selection code sent by the main controller and controls the opening and closing of the electronic switch corresponding to each independent channel, thereby selectively activating the target independent channel.
[0035] Example 2 Example 2 provides an I2C bus expansion method. This method uses an I2C bus expansion system from Example 1. The method includes: after system power-on, the master controller initiates an I2C start signal and sends an address signal to the I2C multiplexer; the I2C multiplexer parses the address signal, and when the address signal matches, the master controller sends a channel selection code and a GPIO switching code to the designated I2C multiplexer; the channel selection code specifies the independent channel that needs to be activated within the I2C multiplexer, and the GPIO switching code is used to select the slave device node mounted on the independent channel; after the I2C multiplexer confirms that the channel selection code and GPIO switching code are configured successfully, the master controller sends the slave device address, selects the target slave device on the independent channel, and reads the slave device data source.
[0036] The following describes an I2C bus expansion method provided in Embodiment 2, which includes the following steps: Step 1: Create a topology mapping table for the device.
[0037] After the system is powered on, the main controller performs an automatic scan, traversing the addresses of all preset I2C multiplexers, the independent channels of each I2C multiplexer, and the GPIO configuration (GPIO switching codes) under each independent channel; for each independent channel, it sequentially traverses all GPIO switching codes, and performs communication addressing for the slave device under each GPIO switching code, activating each slave device and recording the slave device address information.
[0038] Based on the scan results, a topology mapping table is created for each slave device. The topology mapping table records the identifier of each slave device (this identifier is used to mark the slave device and is used for subsequent identification), the corresponding physical path information, and the slave device status. The physical path information includes: slave device address, channel selection code of the independent channel, GPIO configuration, and address of the I2C multiplexer where the independent channel is located.
[0039] The master controller establishes communication with each slave device and performs data transmission operations based on the address information of each slave device recorded in the topology mapping table.
[0040] By creating a slave device topology mapping table, all slave device status information, physical path information, and identifiers can be recorded. When the master controller establishes communication with the target slave device, it can directly retrieve the physical path information from the created slave device topology mapping table based on the identifier information to establish communication with the target slave device and perform data transmission operations.
[0041] As an optional implementation, during system power-on initialization, the main controller periodically performs an automatic scanning step or executes an automatic scan when a communication anomaly is detected during system operation, updating the slave device topology mapping table. For example, during the automatic scanning process, if the scan of a preset node (I2C multiplexer address + channel selection code + GPIO configuration) fails, the main controller can retry a limited number of times (e.g., 3 times). If it ultimately fails, the node (one GPIO configuration can correspond to one slave device node; taking a four-bit GIPO switching code with multiple GIPO pins as an example, multiple slave devices connected to a channel can be partitioned into multiple nodes) is marked as 'offline' or 'abnormal' in the topology mapping table, and this can be reported through the system log. The scanning process will continue without affecting the overall scanning progress.
[0042] As an optional implementation, in order to improve the efficiency of slave device access, the priority of slave device access requests in the slave device topology mapping table can be sorted. When the main controller executes slave device access, it accesses according to the preset priority of slave device access requests.
[0043] As an optional implementation, multiple slave devices with the same GPIO configuration (i.e., one slave node) under the same channel in the slave device topology mapping table can be divided into an access group. When the master controller initiates access to multiple slave devices in an access group, the master controller sends the channel selection code and GPIO switching code of the access group at one time to establish a fixed physical communication path. While maintaining the physical communication path unchanged, the master controller sends the different slave device addresses of each slave device in the access group in sequence to continuously access multiple slave devices in the access group.
[0044] The above implementation scheme further processes the created slave device topology mapping table and sets access priorities. When a slave device access request is encountered, it can prioritize accessing slave devices with higher priorities to improve access efficiency. Simultaneously, multiple slave devices under the same node can be grouped. When the main controller executes a slave device access request, it determines whether multiple slave devices within the same node (one access group) are being accessed under a single access request. It can then prioritize retrieving multiple slave devices within one access group, improving retrieval speed (only one physical communication channel needs to be established).
[0045] Step 2: Perform access from the device.
[0046] Step 2-1: After the system is powered on, the main controller initiates an I2C start signal and sends an address signal to the I2C multiplexer. The I2C multiplexer matches the received address signal and sends back a first acknowledgment signal when the signal matches. After receiving the first acknowledgment signal, the main controller sends a channel selection code and a GPIO switching code to the designated I2C multiplexer.
[0047] Step 2-2: The I2C multiplexer parses the channel selection code (parsed by the channel selection control module) and the GPIO switching code. The channel selection code specifies the independent channel that needs to be activated inside the I2C multiplexer, and the GPIO switching code is used to select the slave device node connected to the independent channel. After the I2C multiplexer confirms that the channel selection code and GPIO switching code are configured successfully, it sends back a second response signal, and the relevant node channel is opened at the same time.
[0048] Steps 2-3: The main controller receives the second feedback response signal, sends the slave device address, selects the target slave device on the independent channel, and sends back the third response signal after the target slave device responds.
[0049] After receiving the third response signal, the master controller sends a data read command, specifying the data source from the slave device. Upon confirming the read command, the slave device sends back a fourth response signal and outputs the corresponding data. Upon receiving this fourth response signal, the master controller receives the data output from the slave device, sends a non-response signal, and issues a stop signal, thus ending the data transmission.
[0050] As an optional implementation, when the following situations occur: the channel selection code and GPIO switching code are not configured successfully, the target slave device does not respond or does not respond in time, or the slave device does not respond or does not respond in time to the read command, the system prompts an error and waits for the master controller to re-initiate the I2C start signal; If the system prompts that an error occurs consecutively for three or more times, the electronic switch of the I2C multiplexer and the internal register of the I2C multiplexer will be reset. After a delay of 80ms-120ms, the system will wait for the main controller to re-initiate the I2C start signal and restart data transmission.
[0051] When the system prompts an error, the slave device topology mapping table can be updated based on the error information, and the slave device status, node status, channel status, or multiplexer status can be updated.
[0052] The above provides a detailed description of the I2C bus expansion system and method provided by this invention. Specific examples have been used to illustrate the structure and working principle of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this invention.
Claims
1. An I2C bus expansion system, characterized in that, include: Main controller; At least one I2C multiplexer communicates with the main controller via an I2C bus. Each I2C multiplexer has a unique device address, multiple independent channels, and at least one GPIO output pin. Each independent channel is equipped with multiple slave devices, and the address selection pin of each slave device is connected to the corresponding GPIO output pin of the corresponding channel; The main controller selects to open the independent channel of the I2C multiplexer based on the control signal from the host computer, and selects the corresponding slave device based on the GPIO output pin after the independent channel is opened.
2. The I2C bus expansion system according to claim 1, characterized in that, The I2C multiplexer is equipped with multiple electronic switches, and the main controller transmits clock signals and data signals to the I2C multiplexer via the I2C bus. The multiplexer selectively distributes the clock signal and the data signal sent by the main controller to each of the independent channels.
3. The I2C bus expansion system according to claim 2, characterized in that, The I2C multiplexer is also equipped with a channel selection control module, which controls the opening and closing of the electronic switch corresponding to each independent channel.
4. An I2C bus expansion method, characterized in that, Using an I2C bus expansion system according to any one of claims 1-3, the method includes: after the system is powered on, the main controller initiates an I2C start signal and sends an address signal to the I2C multiplexer; the I2C multiplexer parses the address signal, and when the address signal matches, the main controller sends a channel selection code and a GPIO switching code to the designated I2C multiplexer. The channel selection code specifies the independent channel that needs to be activated inside the I2C multiplexer, and the GPIO switching code is used to select the slave device node attached to the independent channel. After the I2C multiplexer confirms that the channel selection code and GPIO switching code are configured successfully, the master controller sends the slave device address, selects the target slave device on the independent channel, and reads the slave device data source.
5. The I2C bus expansion method according to claim 4, characterized in that, The main controller sends a data read command, specifying the data source of the slave device to be read; After confirming the read command from the device, the corresponding data is output. After receiving the data output by the slave device, the main controller sends a non-acknowledgment signal and a stop signal to end the data transmission.
6. The I2C bus expansion method according to claim 5, characterized in that, When the channel selection code and GPIO switching code are not configured successfully, the target slave device does not respond or does not respond in time, or the slave device does not respond or does not respond in time when it receives the read command, the system prompts that an error has occurred and waits for the master controller to re-initiate the I2C start signal; When the system prompts that an error occurs consecutively for three or more times, the electronic switch of the I2C multiplexer and the internal register of the I2C multiplexer are reset, and after a delay of 80ms-120ms, the system waits for the main controller to re-initiate the I2C start signal.
7. The I2C bus expansion method according to claim 4, characterized in that, It also includes establishing a device topology mapping table, whereby the master controller performs an automatic scan to traverse the addresses of all preset I2C multiplexers, the independent channels of each I2C multiplexer, and the GPIO configuration under each independent channel; For each independent channel, all GPIO switching codes are traversed sequentially, and under each GPIO switching code, communication addressing is performed to activate each slave device and the slave device address information is recorded. A topology mapping table for slave devices is created based on the scan results. The topology mapping table records the identifier of each slave device, the corresponding physical path information, and the slave device status. The physical path information includes: slave device address, channel selection code of the independent channel it belongs to, GPIO configuration, and address of the I2C multiplexer where the independent channel is located. The master controller establishes communication with each slave device and transmits data to it based on the address information of each slave device recorded in the topology mapping table.
8. The I2C bus expansion method according to claim 7, characterized in that, When the system is powered on and initialized, the main controller periodically performs an automatic scanning step or performs an automatic scan when a communication abnormality is detected during system operation, and updates the slave device topology mapping table.
9. The I2C bus expansion method according to claim 7, characterized in that, The access requests of the slave devices in the slave device topology mapping table are sorted by priority. When the master controller executes slave device access, it accesses the slave devices according to the preset priority of the access requests.
10. The I2C bus expansion method according to claim 8, characterized in that, Multiple slave devices configured with the same GPIO under the same channel in the slave device topology mapping table are divided into an access group; When the master controller initiates access to multiple slave devices within an access group, it sends the channel selection code and GPIO switching code of the access group at once to establish a fixed physical communication path. While maintaining the physical communication path unchanged, it sequentially sends the different slave device addresses of each slave device within the access group to continuously access multiple slave devices within the access group.