Method and device for generating control bits for an inverse butterfly network using a dynamic programming strategy

Abstract

The application discloses a control bit generation method and device of an inverse butterfly network adopting a dynamic programming strategy, and solves the problem of poor flexibility of the control bit generation method of the inverse butterfly network in the prior art. The method comprises the following steps: obtaining preset data; determining the inverse butterfly network, the number of stages of the inverse butterfly network and the number of switching units in each stage of the inverse butterfly network according to the preset data; obtaining node extraction position information of a plurality of extraction nodes, a plurality of output nodes and a plurality of exclusive or operation results; traversing the inverse butterfly network, and calculating the switching position information corresponding to the plurality of extraction nodes in each stage; determining the exclusive or operation result corresponding to the extraction node; judging whether the exclusive or operation result is equal to a judgment value, if yes, setting the control bit of the switching unit position corresponding to the exclusive or operation result to 1, and saving the control bit in a control bit storage list; and the flexibility of generating the corresponding control bit algorithm of the inverse butterfly network according to the extraction demand is realized, and the efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of data exchange network technology, and in particular to a method and apparatus for generating control bits in an inverse butterfly network using a dynamic programming strategy. Background Technology

[0002] In the field of communications, switching refers to the mechanism (control) responsible for establishing communication channels and transmitting communication information between the source and destination terminals on a communication network. The basic function of switching is to establish connections between any incoming and outgoing lines. The component that performs this basic function in a switching system is the switching network (or switching fabric), which is the core of the switching system. The most basic component constituting the switching network is called a switching unit. A switching network is composed of several switching units arranged in a specific topology and control method. The inverse butterfly network is a type of butterfly network in switching networks. (Inverse)butterfly networks have been widely used in cryptography, where they can effectively perform position swaps. Inverse butterfly networks can well support "bit aggregation" operations and can also be used as a method for extracting key fields. The basic switching unit of an inverse butterfly network consists of a 2-to-1 MUX selector. Multiple switching units form a stage of the inverse butterfly network, and the connections between these stages form the entire extraction network. Within each inverse butterfly network switching unit, control signals are used to determine whether two input data points should be swapped. It's important to note that different stages of the inverse butterfly network can handle different address spans, and combinations of different spans across different stages enable data extraction operations at arbitrary locations. The inverse butterfly network XORs the binary values ​​of the input and output nodes, with the result, from least significant bit to most significant bit, corresponding to the configuration values ​​for stage 1, stage 2, and so on. It's crucial that each switching unit can only have one state: switching or pass-through. Therefore, to avoid configuration conflicts, the relative order of critical data should be avoided.

[0003] In other words, the normal operation of the network depends on a complete set of network control signal configuration information. This raises the question of how to accurately and quickly obtain the control bits of each switching unit at each stage of the inverse butterfly network under different application scenarios.

[0004] In existing technologies, the application of inverse butterfly networks is mostly concentrated in the field of general-purpose processors. Bit manipulation units are implemented using inverse butterfly networks and integrated into the microprocessor architecture, enabling the processor to better execute special bit manipulation substitution instructions. However, existing technologies have the following limitations:

[0005] (1) Existing methods for generating control bits in inverse butterfly networks have poor flexibility. For example, the implementation scheme using fixed rotation operations can only generate the required configuration bits based on rotation (cyclic shift) operations, and cannot adapt to more application scenarios.

[0006] (2) The configuration bits cannot be generated efficiently for data types with large bit widths. For example, existing solutions use recursive shift functions to generate configuration bits. When the input data bit width is large, this method will perform a large number of shifts and recursions, thus increasing the latency.

[0007] (3) The connection relationships between switching units are not fully utilized. Existing control bit generation methods do not analyze in detail the locations of other switching units connected to a single switching unit. Because data may be switched to different node locations after passing through a switching unit, to obtain the routing control bit, the switching result of the previous stage needs to be known first, so as to obtain the control bit information for the current stage. Such control bit generation methods have strong inter-stage dependencies. If the control bit generation delay of the previous stage is too large, the control bit of the subsequent stage will not be generated in a timely manner.

[0008] (4) The power consumption of the basic inverse butterfly network is extended. Existing methods introduce additional timing overhead for the control bit generation logic by extending the control bit generation method to the inverse butterfly network. Summary of the Invention

[0009] This invention provides a method and apparatus for generating control bits in an inverse butterfly network using a dynamic programming strategy. This addresses the problems of existing methods for generating control bits in inverse butterfly networks, such as poor flexibility, inefficiency in generating configuration bits for large-width data types, and failure to fully utilize the connections between switching units. By using a distributed function approach, the control bit generation method is applied holistically to each switching unit of the inverse butterfly network, rather than using a recursive function approach. The control bits are obtained through step-by-step, stage-by-stage shifting, thus achieving greater flexibility and efficiency in the algorithm for generating corresponding control bits based on extraction requirements.

[0010] In a first aspect, the present invention provides a method for generating control bits in an inverse butterfly network using a dynamic programming strategy, the method comprising:

[0011] Obtain preset data, wherein the preset data includes: data extraction location, maximum value of the number of data to be extracted, and number of input data;

[0012] The inverse butterfly network, the number of stages in the inverse butterfly network, and the number of switching units in each stage of the inverse butterfly network are determined based on the preset data.

[0013] By utilizing multiple extraction nodes, multiple output nodes, and multiple XOR operation results, the extraction location information of multiple nodes is obtained;

[0014] Traverse the inverse butterfly network and calculate the exchange location information corresponding to multiple extraction nodes in each stage; wherein, the exchange location information includes: exchange address and exchange unit location;

[0015] Determine the XOR operation result corresponding to the extracted node;

[0016] Determine whether the result of the XOR operation is equal to the judgment value. If so, set the control bit of the swap unit position corresponding to the XOR operation result to 1 and store it in the control bit storage list; where 1 indicates that a swap has occurred.

[0017] Output the control bit storage list.

[0018] In conjunction with the first aspect, in one possible implementation, determining the inverse butterfly network, the number of stages in the inverse butterfly network, and the number of switching units in each stage of the inverse butterfly network based on the preset data specifically includes:

[0019] The formula for calculating the number of stages is specifically expressed as: α = log2(N);

[0020] The formula for calculating the number of switching units is specifically expressed as follows:

[0021] Where α represents the number of stages in the inverse butterfly network, N represents the number of input data, and β represents the number of switching units in each stage.

[0022] In conjunction with the first aspect, in one possible implementation, the step of obtaining multiple node extraction location information using multiple extraction nodes, multiple output nodes, and multiple XOR operation results specifically includes:

[0023] The extraction nodes and output nodes are arranged in ascending order, and the output nodes are added after the extraction nodes accordingly.

[0024] The extraction nodes and the output nodes are sorted in ascending order, and the sorted output nodes are added after the extraction nodes in ascending order.

[0025] The binary values ​​of the extracted node and the output node are XORed to obtain multiple operation results. The operation results are then added to the output node to obtain multiple node extraction position information.

[0026] In conjunction with the first aspect, in one possible implementation, the specific formula for calculating the exchange address is expressed as follows:

[0027]

[0028] Where i represents the stage of the inverse butterfly network; x represents the address in each stage; floor() represents flooring down; and % represents modulo operation.

[0029] In conjunction with the first aspect, in one possible implementation, the specific formula for calculating the position of the switching unit is expressed as follows:

[0030]

[0031] Where i represents the stage of the inverse butterfly network; x represents the address in each stage; floor() represents flooring down; and % represents modulo operation.

[0032] In conjunction with the first aspect, in one possible implementation, the node extracts location information, specifically including: an extraction node, an output node, and an XOR operation result.

[0033] In conjunction with the first aspect, in one possible implementation, before determining whether the XOR operation result is equal to the judgment value, the method further includes:

[0034] Initialize the control bit storage list by setting all control bits in the list to 0; where 0 indicates that the result of the XOR operation is not equal to the judgment value.

[0035] In a second aspect, the present invention provides a control bit generation device for an inverse butterfly network employing a dynamic programming strategy, the device comprising:

[0036] The data acquisition module is used to acquire preset data, wherein the preset data includes: data extraction location, maximum value of the number of data to be extracted, and number of input data;

[0037] The network determination module is used to determine the inverse butterfly network, the number of stages of the inverse butterfly network, and the number of switching units in each stage of the inverse butterfly network based on the preset data.

[0038] The node extraction location information acquisition module is used to obtain the extraction location information of multiple nodes by utilizing multiple extraction nodes, multiple output nodes, and multiple XOR operation results.

[0039] The exchange location information acquisition module is used to traverse the inverse butterfly network and calculate the exchange location information corresponding to multiple extraction nodes in each stage; wherein, the exchange location information includes: exchange address and exchange unit location;

[0040] An XOR operation module is used to determine the XOR operation result corresponding to the extraction node;

[0041] The judgment module is used to determine whether the XOR operation result is equal to the judgment value. If so, the control bit of the swap unit position corresponding to the XOR operation result is set to 1 and stored in the control bit storage list; where 1 indicates that a swap has occurred.

[0042] The output module is used to output the control bit storage list.

[0043] Thirdly, the present invention provides an inverse butterfly network control bit generation server employing a dynamic programming strategy, the server including a memory and a processor;

[0044] The memory is used to store computer-executable instructions;

[0045] The processor is used to execute the computer-executable instructions to implement a method for generating inverse butterfly network control bits using a dynamic programming strategy.

[0046] Fourthly, the present invention provides a computer-readable storage medium having executable instructions, wherein when a computer executes the executable instructions, it can implement a method for generating inverse butterfly network control bits using a dynamic programming strategy.

[0047] One or more technical solutions provided in this invention have at least the following technical effects or advantages:

[0048] (1) The control bit generation method proposed in this invention has high flexibility and can be adapted to various application scenarios. Instead of dividing the inverse butterfly network, it directly obtains the control bits of each switching unit by providing the input positions of key data based on the overall network topology, without limiting the application scenario. The control bit generation method proposed in this invention is applicable to any field that uses an inverse butterfly network for data extraction and rearrangement, and has a certain degree of broad applicability compared to existing methods.

[0049] (2) Use dynamic programming to generate control bit information. By extracting all possible connection relationships between switching units, the data destination after the switching unit has performed a switch can be determined without waiting for the result of the previous stage switch, thus eliminating inter-stage dependencies.

[0050] (3) Use distributed functions instead of recursive functions to generate control bit information. For data with a large bit width, such as the network packet header vector (PHV), there will be no multiple recursions and shifts, which would lead to excessive latency. Compared with existing methods, such as using recursive shift functions to generate configuration bits, when the input data bit width is large, a large number of shifts and recursions will be performed, thus increasing the latency.

[0051] (4) The proposed control bit generation method is a pure combinational logic in terms of hardware implementation. Under the condition that it is permissible, it will not introduce additional clock cycle delay and additional timing to introduce dynamic power consumption. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments of the present invention or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 A flowchart illustrating the steps of the inverse butterfly network control bit generation method using a dynamic programming strategy provided in this embodiment of the invention;

[0054] Figure 2 The node location information is extracted according to the embodiments of the present invention;

[0055] Figure 3 This provides the output of control bit information for each stage in the embodiments of the present invention;

[0056] Figure 4 This is a schematic diagram illustrating the execution result of the control bit information obtained using the method provided by this invention, as provided in an embodiment of the invention.

[0057] Figure 5 This is a schematic diagram of the network processor MAU structure provided in an embodiment of the present invention;

[0058] Figure 6 This invention provides a 128x8 extraction method for network node information.

[0059] Figure 7 This invention provides a 128x8 extraction network for control bit information at each stage.

[0060] Figure 8 A simplified schematic diagram of the testing platform provided in an embodiment of the present invention;

[0061] Figure 9 The results are for the inverse butterfly network extraction test provided in this embodiment of the invention. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0063] This invention provides a method for generating control bits in an inverse butterfly network using a dynamic programming strategy, such as... Figure 1 As shown, the method includes the following steps S101 to S107.

[0064] S101, Obtain preset data, wherein the preset data includes: data extraction location, maximum value of the number of data to be extracted, and number of input data.

[0065] S102, determine the inverse butterfly network, the number of stages in the inverse butterfly network, and the number of switching units in each stage of the inverse butterfly network according to preset data.

[0066] Specifically, in step S102, the inverse butterfly network, the number of stages in the inverse butterfly network, and the number of switching units in each order of the inverse butterfly network are determined according to preset data. This includes: First, the formula for calculating the number of stages is: α = log2(N); then, the formula for calculating the number of switching units is: Where α represents the number of stages in the inverse butterfly network, N represents the number of input data, and β represents the number of switching units in each stage.

[0067] S103: Using multiple extraction nodes, multiple output nodes, and multiple XOR operation results, the extraction position information of multiple nodes is obtained.

[0068] Specifically, in step S103, multiple extraction nodes, multiple output nodes, and multiple XOR operation results are used to obtain multiple node extraction location information, which specifically includes the following steps.

[0069] (1) Sort the multiple extraction nodes and multiple output nodes in ascending order respectively, and add the output nodes after the extraction nodes accordingly.

[0070] (2) Sort the multiple extraction nodes and multiple output nodes in ascending order, and add the sorted output nodes after the extraction nodes in ascending order.

[0071] (3) Perform XOR operation on the binary values ​​of the extracted node and the output node respectively to obtain multiple operation results, and add the operation results after the output node to obtain multiple node extraction position information.

[0072] Specifically, the node extraction location information includes: an extraction node, an output node, and an XOR operation result.

[0073] S104, traverse the inverse butterfly network and calculate the exchange location information corresponding to multiple extraction nodes in each stage; wherein, the exchange location information includes: exchange address and exchange unit location.

[0074] Specifically, in step S104, the specific formula for calculating the exchange address is expressed as follows:

[0075]

[0076] Where i represents the stage of the inverse butterfly network; x represents the address in each stage; floor() represents flooring down; and % represents modulo operation.

[0077] For example, input nodes in a reverse butterfly network are stored in different locations after passing through the network. For instance, data from input node 4'b0000 might enter the switching unit with sequence number 0 in stage 1, but could be switched to the switching unit with sequence number 1 in stage 2. The input signal can be divided into different groups in each stage. Let stage i be the number of groups, then this stage is divided into groups of 2. i Each data point is grouped into a set, such as... Figure 4 As shown in the red box. Furthermore, the inverse butterfly network has different address spans at each stage; within each group, the data address span for exchange is 2. i-1 Then, the other address that is swapped with any address x in stage i can be expressed using formula (1.1): The purpose of modulo operation is to roll back the high-order address bits that were exchanged within a packet to the low-order address bits within the same packet, in order to identify the other address that was exchanged with the high-order address. For example, in phase 1, data numbered x will be exchanged with data numbered... They exchange data.

[0078] Specifically, in step S104, the specific calculation formula for the position of the exchange unit is expressed as follows:

[0079]

[0080] Where i represents the stage of the inverse butterfly network; x represents the address in each stage; floor() represents flooring down; and % represents modulo operation.

[0081] For example, after knowing the address of another data unit that is exchanged with data at any location, it is also necessary to know the specific location of the exchange unit where the exchange occurred, that is, to know the location of the configuration bit that needs to be set to 1. This location can be expressed according to formula (1.2): For example, in stage 1, the data numbered x will be related to the data numbered x. The data is exchanged, and the location of the exchange unit where the exchange occurs is...

[0082] When calculating the switching address and the location of the switching unit, the positional relationship between each switching unit and other switching units that it may exchange with determines all possible destinations of the data after the switching unit exchanges, thereby eliminating the dependency between the generation of control bit information and the result of the previous stage of exchange.

[0083] S105, determine the XOR operation result corresponding to the extracted node.

[0084] Specifically, before step S106, the method further includes: initializing the control bit storage list and setting all control bit storage lists to 0; where 0 indicates that the result of the XOR operation is not equal to the judgment value.

[0085] S106: Determine if the XOR operation result equals the judgment value. If so, set the control bit of the swap unit corresponding to the XOR operation result to 1 and store it in the control bit storage list; where 1 indicates that a swap has occurred. Control bit information is generated using dynamic programming. By extracting all possible connection relationships between swap units, the data destination after a swap in that swap unit is determined, eliminating the need to wait for the previous level's swap result and removing inter-stage dependencies.

[0086] S107, Output control bit storage list.

[0087] The method proposed in this invention offers high flexibility and can be adapted to various application scenarios. Instead of partitioning the inverse butterfly network, it directly obtains the control bits of each switching unit based on the overall network topology and the input positions of key data, without limiting the application scenario. The control bit generation method proposed in this invention is applicable to any field using inverse butterfly networks for data extraction and rearrangement, exhibiting wider applicability compared to existing methods. It uses distributed functions instead of recursive functions to generate control bit information. For large-bit-width data, such as network packet header vectors (PHV), there are no multiple recursions and shifts, avoiding excessive latency. In contrast, existing methods, such as those using recursive shift functions to generate configuration bits, involve numerous shifts and recursions when the input data bit width is large, increasing latency.

[0088] The control bit generation method proposed in this invention is a pure combinational logic in terms of hardware implementation, and will not introduce additional clock cycle delay and dynamic power consumption due to additional timing when conditions permit.

[0089] Based on the steps S101 to S107 described above, this invention provides a specific embodiment. Using six extraction positions, defining a maximum extraction count of 16, and inputting 16 data points, the invention outputs a four-stage, eight-switching-unit inverse butterfly network control bit information. Taking the exchange of data from input nodes 0, 3, 15, 8, 6, and 5 to output nodes 0, 1, 2, 3, 4, and 5 as an example, the execution process of this invention is explained in detail. The data structure in this invention is illustrated in Table 1.

[0090] Table 1 Configuration Method Data Structure Description

[0091]

[0092] First, the user defines six data input node positions, and the results are stored in `position_couple`. The maximum number of data points of interest, `case_max`, is defined as 16, and the number of input data points, `data_max`, is also defined as 16. The number of stages in the inverse butterfly network obtained from user input is `stage_max` = 4, and the number of switching units per stage, which is also the number of control bits required per stage, is `data_per_stage` = 8. The number of data points of interest to be extracted is `data_cared` = 6. The control bit information for each stage is stored in the `stage_config_string` list and initialized to all zeros. The user input is checked for validity; if invalid, the method proposed in this invention is exited directly. The extracted node positions in `position_couple` are sorted in ascending order, and an output node position is added after the extracted position. The binary values ​​of the input and output nodes are XORed bitwise, such as... Figure 2 As shown, in the element [3, 1, '0010'], 3 represents the position of the data extraction node of interest, 1 represents the output node position to which the extracted node will ultimately be swapped, and 0010 represents the bitwise XOR result of the binary representation of extracted node 3 (0011) and the binary representation of output node 1 (0001), with the result padded to the same bit width. This result is then added to the output node position in position_couple. The final node extraction position information is as follows: Figure 2 As shown.

[0093] Then, the switching units in each stage of the inverse butterfly network are traversed, and the output node position (opposite_position) and the switching unit position (switch_position) that are swapped with the input node are obtained according to equations (1.1) and (1.2). The position XOR result in position_couple is used to determine whether the current position bit needs to be swapped. If a swap is needed, the control bit of the switching unit at the current swap position is set to 1; otherwise, it remains 0. The control bit is updated in the configuration value list stage_config_string to obtain the control bit information of all switching units in each stage. The control bit information of each stage is output as follows: Figure 3 As shown.

[0094] The control bit information is then fed into the inverse butterfly network, and the final data exchange behavior is as follows: Figure 4 As shown.

[0095] According to the embodiments provided by this invention, the control bit generation method of this invention successfully extracts and rearranges data from the input nodes according to the order requirements of the output nodes. Because the connection relationships between each switching unit are considered in advance and dynamic programming is used, this method does not need to wait for the switching results of the previous stage, thereby eliminating the dependency between switching stages. Simultaneously, the control bit information of each stage can be provided synchronously without relying on the switching results of the previous stage.

[0096] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0097] Experiments were conducted using the MAU (Match-Action Unit) in the NP network processor. The main function of this MAU is to send the network packet header vector (PHV) to the matching action core for matching and PHV modification. The main function of the inverse butterfly network within the MAU is to further extract key data and rearrange the positions of the PHV generated by the parser (Paser), thereby accelerating the processing speed of the subsequent matching action core. This extraction network is designed with muxSwitches ports to receive extraction network control bit information. The inverse butterfly network sets the behavior of each switching unit according to the control bit information to achieve the extraction and rearrangement of the data of interest. The hardware port descriptions of the inverse butterfly extraction network are shown in Table 2, and the MAU structure is as follows: Figure 5 As shown.

[0098] Table 2 Description of Inverse Butterfly Matching Network Ports

[0099]

[0100]

[0101] The MAU receives a 2048-bit PHV, and the switching precision of the inverse butterfly switching unit within the MAU is at the byte level. Therefore, each stage of the inverse butterfly extraction network requires 128 byte-level switching units, and a total of 8 stages are needed. The control plane needs to send 1024 bits of control information for inverse butterfly network extraction, with each stage requiring 128 bits of control information, for a total of 8 stages.

[0102] In the control bit generation method, the number of extractions is set to 6, and the positions of interest to be extracted are

[243] ,

[242] ,

[241] ,

[240] ,

[239] , and

[238] ; the number of input data is 256 (the precision of the inverse butterfly switching unit is at the byte level at this time); according to steps S101 to S107, the number of stages and the number of switching units of the inverse butterfly extraction network are obtained, and the correspondence between input and output nodes and the XOR result of the nodes are given, such as Figure 6 As shown.

[0103] The method provided by this invention requires swapping the data input at the input node to the corresponding output node position to achieve the extraction and rearrangement of the data of interest.

[0104] For each stage of the inverse butterfly network, the switching units in each stage are traversed, and the output node position (opposite_position) and the switching unit position (switch_position) that are swapped with the input node are obtained according to equations (1.1) and (1.2). According to steps S101 to S107, the control bit information (stage_config_string) of all switching units in each stage is obtained, and the control bit information of each stage is output as follows: Figure 7 As shown.

[0105] The obtained control bit information is fed into the muxSwitches port of the inverse butterfly extraction network through the test platform to verify that the control bit information obtained by the control bit generation method can correctly extract the data of interest to the relevant location. The test platform structure is as follows: Figure 8 As shown.

[0106] View the input PHV after passing through the inverse butterfly network, such as Figure 9 As shown, the output results are rearranged. Note that during the test, only some fields of the input PHV are valid, and invalid PHV fields will return error messages.

[0107] This invention provides a control bit generation device for an inverse butterfly network using a dynamic programming strategy. The device includes: a data acquisition module, a network determination module, a node position information extraction module, a position information exchange module, an XOR operation module, a judgment module, and an output module.

[0108] The data acquisition module is used to acquire preset data, which includes: data extraction location, maximum number of data to be extracted, and number of input data.

[0109] The network determination module is used to determine the inverse butterfly network, the number of stages in the inverse butterfly network, and the number of switching units in each stage of the inverse butterfly network based on preset data.

[0110] The node extraction location information acquisition module is used to obtain the extraction location information of multiple nodes by utilizing multiple extraction nodes, multiple output nodes, and multiple XOR operation results.

[0111] The exchange location information acquisition module is used to traverse the inverse butterfly network and calculate the exchange location information corresponding to multiple extraction nodes in each stage; wherein, the exchange location information includes: exchange address and exchange unit location.

[0112] The XOR operation module is used to determine the XOR operation result corresponding to the extracted node.

[0113] The judgment module is used to determine whether the result of the XOR operation is equal to the judgment value. If so, the control bit of the swap unit position corresponding to the XOR operation result is set to 1 and stored in the control bit storage list; where 1 indicates that a swap has occurred.

[0114] The output module is used to output a list of control bits.

[0115] The apparatus or module described in the above embodiments can be implemented by a computer chip or physical entity, or by a product with a certain function. For ease of description, the above apparatus is described by dividing it into various modules according to their functions. In implementing this invention, the functions of each module can be implemented in one or more software and / or hardware. Of course, a module that implements a certain function can also be implemented by combining multiple sub-modules or sub-units.

[0116] The methods, apparatus, or modules described in this invention can be implemented in a computer-readable program code manner. The controller can be implemented in any suitable manner, for example, as a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of a memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code manner, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included within it for implementing various functions can also be considered as structures within the hardware component. Alternatively, the device used to implement various functions can be viewed as either a software module that implements the method or a structure within a hardware component.

[0117] Some modules in the apparatus described in this invention can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, classes, etc., that perform a specific task or implement a specific abstract data type. This invention can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0118] This invention provides a reverse butterfly network control bit generation server employing a dynamic programming strategy, comprising a memory and a processor; the memory is used to store computer-executable instructions; the processor is used to execute the computer-executable instructions to implement a reverse butterfly network control bit generation method employing a dynamic programming strategy.

[0119] This invention provides a computer-readable storage medium having executable instructions. When a computer executes the executable instructions, it can implement a method for generating inverse butterfly network control bits using a dynamic programming strategy.

[0120] The aforementioned storage media include, but are not limited to, Random Access Memory (RAM), Read-Only Memory (ROM), Cache, Hard Disk Drive (HDD), or Memory Card. The memory can be used to store computer program instructions.

[0121] While this invention provides the method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-inventive labor. The order of steps listed in this embodiment is merely one possible execution order among many and does not represent the only possible execution order. In actual device or client product execution, the methods shown in this embodiment or the accompanying drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment).

[0122] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus necessary hardware. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, or it can be embodied in the process of data migration. The computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of the present invention.

[0123] The various embodiments described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. All or part of this invention can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0124] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A method for generating control bits in an inverse butterfly network using a dynamic programming strategy, characterized in that, include: Acquire preset data, wherein the preset data includes: data extraction location, maximum number of data to be extracted, and number of input data; wherein the data extraction location includes the correspondence between extraction nodes and output nodes; The inverse butterfly network, the number of stages in the inverse butterfly network, and the number of switching units in each stage of the inverse butterfly network are determined based on the preset data. Multiple node extraction position information is obtained by utilizing multiple extraction nodes, multiple output nodes, and multiple XOR operation results. Specifically, this involves: arranging the multiple extraction nodes and multiple output nodes in ascending order, and adding the corresponding output nodes after the extraction nodes; arranging the multiple extraction nodes and multiple output nodes in ascending order, and adding the sorted output nodes after the extraction nodes; and performing XOR operations on the binary values ​​of the extraction nodes and the output nodes to obtain multiple operation results, and adding these results after the output nodes to obtain the multiple node extraction position information. Traverse the inverse butterfly network and calculate the exchange location information corresponding to multiple extraction nodes in each stage; wherein, the exchange location information includes: exchange address and exchange unit location; wherein, the specific calculation formula for the exchange address is expressed as: ;in, This represents the stage of the inverse butterfly network; This represents the address in each stage; Indicates rounding down; This represents the modulo operation; the specific calculation formula for the position of the exchange unit is expressed as follows: ;in, This represents the stage of the inverse butterfly network; This represents the address in each stage; Indicates rounding down; This represents the modulo operation; Determine the XOR operation result corresponding to the extracted node; Determine whether the result of the XOR operation is equal to the judgment value. If so, set the control bit of the swap unit position corresponding to the XOR operation result to 1 and store it in the control bit storage list; where 1 indicates that a swap has occurred. Output the control bit storage list.

2. The method for generating control bits in an inverse butterfly network using a dynamic programming strategy according to claim 1, characterized in that, The step of determining the inverse butterfly network, the number of stages in the inverse butterfly network, and the number of switching units in each stage of the inverse butterfly network based on the preset data specifically includes: The formula for calculating the number of stages is as follows: ; The formula for calculating the number of switching units is specifically expressed as follows: ; in, This indicates the number of stages in the inverse butterfly network. Indicates the number of input data items; This indicates the number of exchange units in each stage.

3. The method for generating control bits in an inverse butterfly network using a dynamic programming strategy according to claim 1, characterized in that, The node extraction location information specifically includes: an extraction node, an output node, and an XOR operation result.

4. The method for generating control bits in an inverse butterfly network using a dynamic programming strategy according to claim 1, characterized in that, Before determining whether the XOR operation result is equal to the value to be determined, the method further includes: Initialize the control bit storage list by setting all control bits in the list to 0; where 0 indicates that the result of the XOR operation is not equal to the judgment value.

5. A reverse butterfly network control bit generation device employing a dynamic programming strategy, implementing the method described in any one of claims 1 to 4, characterized in that, include: The data acquisition module is used to acquire preset data, wherein the preset data includes: data extraction location, maximum value of the number of data to be extracted, and number of input data; The network determination module is used to determine the inverse butterfly network, the number of stages of the inverse butterfly network, and the number of switching units in each stage of the inverse butterfly network based on the preset data. The node extraction location information acquisition module is used to obtain the extraction location information of multiple nodes by utilizing multiple extraction nodes, multiple output nodes, and multiple XOR operation results. The exchange location information acquisition module is used to traverse the inverse butterfly network and calculate the exchange location information corresponding to multiple extraction nodes in each stage; wherein, the exchange location information includes: exchange address and exchange unit location; An XOR operation module is used to determine the XOR operation result corresponding to the extraction node; The judgment module is used to determine whether the XOR operation result is equal to the judgment value. If so, the control bit of the swap unit position corresponding to the XOR operation result is set to 1 and stored in the control bit storage list; where 1 indicates that a swap has occurred. The output module is used to output the control bit storage list.

6. A reverse butterfly network control bit generation server employing a dynamic programming strategy, characterized in that, Including memory and processor; The memory is used to store computer-executable instructions; The processor is used to execute the computer-executable instructions to implement the inverse butterfly network control bit generation method using a dynamic programming strategy as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium has executable instructions, and when the computer executes the executable instructions, it can implement the inverse butterfly network control bit generation method using a dynamic programming strategy as described in any one of claims 1-4.

Images