A method for pushing down RDL information for chip back-end design

Abstract

The application relates to the technical field of integrated circuit design, in particular to an RDL information push-down method for chip back-end design, which can filter out to-be-pushed-down information from top RDL information aggregation in a self-defined manner through configuration information, improves the flexibility of RDL information push-down, determines the RDL information content pushed to a target unit in a set graph operation mode, guarantees the completeness and reliability of the RDL information, and the set graph operation mode has higher calculation efficiency, so that the processing efficiency of the RDL information push-down is higher, that is, the reliability and efficiency of the RDL information push-down are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an RDL information pushdown method for chip back-end design. Background Technology

[0002] Currently, in chip design, after the physical verification of placement and routing is completed at the cell level, IR drop and EM electrical offset simulations are required. Typically, information on all metal layers of the chip is needed to ensure the accuracy of the simulation. However, since obtaining all metal layer information is quite complex, cell designers often add a custom top-level metal layer to facilitate rapid simulation. However, since the custom top-level metal layer differs from the actual metal layer, the above method may lead to overly ideal simulation results, resulting in a large discrepancy between the cell-level and top-level simulation results. This necessitates repeated optimization iterations, reducing simulation efficiency.

[0003] To address the aforementioned issues, existing technologies have proposed methods to push down top-level RDL information to the cell level. While existing EDA tools can perform the function of pushing down RDL information, the output RDL definition often requires users to manually recover some information, such as missing convex connection relationships. The introduction of manual recovery steps inevitably leads to a reduction in simulation efficiency.

[0004] Therefore, improving the reliability and efficiency of RDL information pushdown has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0006] A method for pushing down RDL information for chip back-end design, the method comprising:

[0007] S101, according to the preset configuration information, filter out the information to be pushed down from the obtained top-level RDL information, wherein the top-level RDL information includes several reference objects corresponding to M information types, the reference objects correspond to reference attribute information, and the reference attribute information includes at least shape information and position information, where M is a positive integer;

[0008] S102, based on the shape and position information corresponding to each reference object in the top-level RDL information, and the shape and position information corresponding to the preset target unit, the associated reference objects and the associated shapes corresponding to each reference object associated with the target unit are determined by set graphics operations.

[0009] S103, based on the associated shapes of each reference object associated with the target unit, the reference attribute information of each reference object is pushed down to the target unit.

[0010] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the RDL information pushdown method for chip back-end design provided by the present invention achieves considerable technical progress and practicality, and has broad industrial application value. It has at least the following advantages:

[0011] This invention enables customized filtering of information to be pushed down from top-level RDL information through configuration information, improving the flexibility of RDL information pushdown. It determines the RDL information content to be pushed down to the target unit through set graph operations, ensuring the completeness and reliability of RDL information. Moreover, set graph operations have higher computational efficiency, making the processing efficiency of RDL information pushdown higher, thus improving the reliability and efficiency of RDL information pushdown. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart illustrating an RDL information pushdown method for chip back-end design, provided as an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This embodiment provides a method for pushing down RDL information for chip back-end design. See [link to relevant documentation] Figure 1 This is a flowchart illustrating an RDL information pushdown method for chip back-end design provided by an embodiment of the present invention. The method includes:

[0016] S101, according to the preset configuration information, filter out the information to be pushed down from the obtained top-level RDL information, wherein the top-level RDL information includes several reference objects corresponding to M information types, the reference objects correspond to reference attribute information, and the reference attribute information includes at least shape information and position information, where M is a positive integer;

[0017] S102, based on the shape and position information corresponding to each reference object in the top-level RDL information, and the shape and position information corresponding to the preset target unit, the associated reference objects and the associated shapes corresponding to each reference object associated with the target unit are determined by set graphics operations.

[0018] S103, based on the associated shapes of each reference object associated with the target unit, the reference attribute information of each reference object is pushed down to the target unit.

[0019] Among them, the top-level RDL information can refer to the redistribution layer design data at the top level of the entire chip. The top-level RDL information includes complete interconnect information. The information type can refer to the RDL design element category. The reference object can refer to the specific design instance under the corresponding RDL design element category. The reference attribute information can be data used to describe the characteristics of the corresponding reference object. The shape information can refer to geometric shape information, such as rectangle, polygon, etc. The position information can refer to the coordinate position of the corresponding reference object in the entire chip coordinate system.

[0020] The configuration information can be customized by the user. The configuration information can be used to indicate the required reference attribute information. All the required reference attribute information is combined into the information to be pushed down.

[0021] Set-based geometric operations can refer to mathematical operations based on geometric shapes, such as intersection, union, and difference operations.

[0022] The target unit can be specified by the user. The target unit can be a basic unit or a functional module in the chip. Typically, a functional module can be considered to contain multiple basic units.

[0023] In one specific implementation, prior to step S101, the method further includes:

[0024] Enable the full-chip RDL database;

[0025] Set the target cell from which RDL information needs to be pushed down.

[0026] Enabling the full-chip RDL database can refer to loading the complete chip design database to support subsequent operations.

[0027] Specifically, multiple target units can be set simultaneously, and correspondingly, the RDL information push-down processing of multiple target units can be executed in parallel or serially.

[0028] In one specific implementation, the configuration information includes first configuration sub-information, and the information type includes at least access point, bump, first metal layer, second metal layer, redistribution via, first interlayer via, and second interlayer via.

[0029] When the first configuration sub-information is the first preset value, the access point, the bump, the first metal layer, the second metal layer, the redistribution via, the first interlayer via and the second interlayer via, and the reference attribute information corresponding to each reference object are respectively used as the information to be pushed down.

[0030] When the first configuration sub-information is the second preset value, the reference objects corresponding to the access point, the convex point and the redistribution via, and the reference attribute information corresponding to each reference object are used as the information to be pushed down.

[0031] The first configuration sub-information can be used to control the push-down range to determine the completeness of the RDL information push-down. The access point (AP) can refer to the connection point between the chip and the package. The bump can refer to the connection point between the package and the outside. The first metal layer can refer to the top metal layer, which is usually used for power / global routing. The second metal layer can refer to the second-to-top metal layer, which is usually used for signal routing. The redistribution via (RV) can refer to the via connecting the RDL metal layer. The first interlayer via (II) can refer to the standard interlayer via. The second interlayer via (HI) can refer to the high-density via.

[0032] Specifically, when the first configuration sub-information is the first preset value, it is the complete push-down mode, which means that all reference objects and reference attribute information corresponding to all information types are used as information to be pushed down. The complete push-down mode can be used in scenarios where IR / EM simulation analysis is performed accurately.

[0033] When the first configuration sub-information is the second preset value, it is in partial push-down mode. That is, only the reference objects and reference attribute information corresponding to the three more critical information types, namely access points, bumps and redistributed vias, are used as information to be pushed down. Partial push-down mode can be used for quick inspection or early chip design stage.

[0034] The first preset value can be set to 1, and the second preset value can be set to 0.

[0035] In one specific implementation, the configuration information further includes second configuration sub-information, which is a preset set of prohibited networks, and the reference attribute information further includes network information.

[0036] Before determining the information to be pushed down, the reference objects whose network information is within the second configuration sub-information are removed, and then the information to be pushed down is determined.

[0037] The prohibited network set may include several network identifiers that are prohibited from being pushed down, and the network information may refer to the electrical network identifier to which the corresponding reference object belongs.

[0038] Specifically, when determining the information to be pushed down, each reference object that conforms to the current push-down mode needs to be further filtered by the second configuration sub-information. If the network information of the reference object is included in the prohibited network set, the reference object will not be pushed down.

[0039] The set of networks to be blocked can be customized by the user according to the application scenario. For example, blocking networks dedicated to pushdown testing or networks related to pushdown encryption keys can be blocked.

[0040] In one specific implementation, the reference attribute information further includes connection information.

[0041] Connection information can refer to data describing the electrical connection relationships between RDL objects.

[0042] In one specific implementation, the step of determining, through set graph operations, each reference object associated with the target unit and its associated shape based on the shape and position information corresponding to each reference object in the top-level RDL information, and the shape and position information corresponding to the preset target unit, includes:

[0043] For any reference object in the top-level RDL information, the intersection is calculated based on the shape and position information corresponding to the reference object and the shape and position information corresponding to the preset target unit to obtain the intersection calculation result corresponding to the reference object.

[0044] If the intersection calculation result is empty, it is determined that the reference object is not associated with the target unit;

[0045] If the intersection calculation result is not empty, then the reference object is determined to be associated with the target unit, and the intersection calculation result is used as the associated shape corresponding to the reference object.

[0046] In this embodiment, the set graphics operation mainly adopts the intersection calculation method. Intersection calculation can refer to the mathematical operation of calculating the overlapping part of two geometric shapes, which is used to find the part of the reference object within the target unit.

[0047] Specifically, when performing intersection calculations, it is necessary to perform the calculations in a unified coordinate system.

[0048] In one specific implementation, after step S103, the method further includes:

[0049] The reference attribute information corresponding to each reference object under the preset information type in the top-level RDL information is output as a DEF file. The DEF file is referenced before the target cell executes the RDL script for the through-hole cell definition of the target cell.

[0050] In this context, DEF files can refer to Design Exchange Format files. In this embodiment, DEF files are used as a standard library for defining via units.

[0051] RDL scripts can refer to RDL-related design scripts executed in the target cell, used to perform specific design operations using RDL information pushed down to the target cell.

[0052] Before executing the RDL script, the via definition needs to be loaded, that is, the DEF file needs to be referenced, to ensure that all basic cells use the same via definition and to avoid different basic cells defining different vias.

[0053] In one specific implementation, the preset information type includes redistribution vias, first interlayer vias, and second interlayer vias.

[0054] Among them, redistribution vias, first interlayer vias, and second interlayer vias are via types that need to be clearly defined at the unit level. Therefore, redistribution vias, first interlayer vias, and second interlayer vias are used as preset information types.

[0055] In this embodiment, the configuration information allows for customized filtering of information to be pushed down from the top-level RDL information summary, improving the flexibility of RDL information pushdown. The RDL information content to be pushed down to the target unit is determined by set graph operations, ensuring the completeness and reliability of the RDL information. Moreover, set graph operations have higher computational efficiency, resulting in higher processing efficiency for RDL information pushdown, which in turn improves the reliability and efficiency of RDL information pushdown.

[0056] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A method for pushing down RDL information for chip back-end design, characterized in that, The method includes: S101, according to the preset configuration information, filter out the information to be pushed down from the acquired top-level RDL information, wherein the top-level RDL information includes several reference objects corresponding to M information types, the reference objects correspond to reference attribute information, the reference attribute information includes at least shape information and position information, M is a positive integer, the information types include at least access point, bump, first metal layer, second metal layer, redistribution via, first interlayer via and second interlayer via, the first metal layer is the top metal layer, the second metal layer is the second-to-top metal layer, the first interlayer via is a standard interlayer via, and the second interlayer via is a high-density via; S102, based on the shape and position information corresponding to each reference object in the top-level RDL information, and the shape and position information corresponding to the preset target unit, the associated shapes of each reference object associated with the target unit and the associated shapes of each reference object associated with the target unit are determined through set graph operations. The step of determining the associated shapes of each reference object associated with the target unit and the associated shapes of each reference object associated with the target unit through set graph operations based on the shape and position information corresponding to each reference object in the top-level RDL information, and the shape and position information corresponding to the preset target unit, includes: For any reference object in the top-level RDL information, the intersection is calculated based on the shape and position information corresponding to the reference object and the shape and position information corresponding to the preset target unit to obtain the intersection calculation result corresponding to the reference object. If the intersection calculation result is empty, it is determined that the reference object is not associated with the target unit; If the intersection calculation result is not empty, then the reference object is determined to be associated with the target unit, and the intersection calculation result is used as the associated shape corresponding to the reference object; S103, based on the associated shapes of each reference object associated with the target unit, the reference attribute information of each reference object is pushed down to the target unit.

2. The RDL information pushdown method for chip back-end design according to claim 1, characterized in that, Prior to step S101, the method further includes: Enable the full-chip RDL database; Set the target cell from which RDL information needs to be pushed down.

3. The RDL information pushdown method for chip back-end design according to claim 1, characterized in that, The configuration information includes first configuration sub-information; When the first configuration sub-information is the first preset value, the access point, the bump, the first metal layer, the second metal layer, the redistribution via, the first interlayer via and the second interlayer via, and the reference attribute information corresponding to each reference object are respectively used as the information to be pushed down. When the first configuration sub-information is the second preset value, the reference objects corresponding to the access point, the convex point and the redistribution via, and the reference attribute information corresponding to each reference object are used as the information to be pushed down.

4. The RDL information pushdown method for chip back-end design according to claim 3, characterized in that, The configuration information also includes second configuration sub-information, which is a preset set of prohibited networks, and the reference attribute information also includes network information. Before determining the information to be pushed down, the reference objects whose network information is within the second configuration sub-information are removed, and then the information to be pushed down is determined.

5. The RDL information pushdown method for chip back-end design according to claim 4, characterized in that, The reference attribute information also includes connection information.

6. The RDL information pushdown method for chip back-end design according to claim 3, characterized in that, After step S103, the method further includes: The reference attribute information corresponding to each reference object under the preset information type in the top-level RDL information is output as a DEF file. The DEF file is referenced before the target cell executes the RDL script for the through-hole cell definition of the target cell.

7. The RDL information pushdown method for chip back-end design according to claim 6, characterized in that, The preset information types include redistribution vias, first interlayer vias, and second interlayer vias.

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