Semiconductor structure and its fabrication method, memory

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory. The semiconductor structure includes: a substrate, a plurality of semiconductor pillars located above the substrate, a memory structure, and a plurality of transistors. The plurality of semiconductor pillars are arranged in an array along a first direction and a second direction. Each semiconductor pillar includes a first portion and a second portion located on the first portion. The first and second directions intersect and are both parallel to the top surface of the substrate. The memory structure includes a first electrode layer, a dielectric layer, and a second electrode layer. The first electrode layer covers the sidewalls of the first portion and is located in spaced-apart first filling regions, each first filling region surrounding the sidewalls of each first portion. The dielectric layer at least covers the surface of the first electrode layer. The second electrode layer covers the surface of the dielectric layer. The channel structure of each transistor is located within the second portion, and the extension direction of the channel structure is the same as the extension direction of the second portion.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, the size of capacitors also shrinks. Ensuring the performance of capacitors in DRAM has become a pressing issue. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a memory.

[0005] According to a first aspect of this disclosure, a semiconductor structure is provided, comprising: a substrate, a plurality of semiconductor pillars located above the substrate, a memory structure, and a plurality of transistors;

[0006] The plurality of semiconductor pillars are arranged in an array along a first direction and a second direction; each semiconductor pillar includes a first portion and a second portion located on the first portion; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;

[0007] The storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer; the first electrode layer covers the sidewall of the first portion, and the first electrode layer is located in spaced-apart first filling regions, each of the first filling regions surrounding the sidewall of each of the first portions; the dielectric layer at least covers the surface of the first electrode layer; the second electrode layer covers the surface of the dielectric layer.

[0008] The channel structure of each transistor is located within the second portion, and the channel structure extends in the same direction as the second portion.

[0009] In the above scheme, the cross-sectional shape of the channel structure includes elliptical or elongated shape.

[0010] In the above scheme, the material of the second part is different from the material of the first part.

[0011] In the above scheme, the material in the first part includes a metal compound, and the material in the second part includes a semiconductor material.

[0012] In the above scheme, the substrate includes an isolation structure, and a plurality of semiconductor pillars are located on the isolation structure.

[0013] In the above scheme, the transistor includes:

[0014] A gate structure covering at least one side of the second portion; and

[0015] The source and drain are respectively located at the two opposite ends of the second part.

[0016] In the above scheme, the semiconductor structure further includes:

[0017] Multiple bit lines are located on the transistor and electrically connected to the top of the second portion.

[0018] According to another aspect of this disclosure, a memory is provided, comprising: one or more semiconductor structures as described in any of the embodiments of this disclosure above.

[0019] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0020] A substrate is provided on which a plurality of semiconductor pillars are formed in an array along a first direction and a second direction; each semiconductor pillar includes a first portion and a second portion located on the first portion; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;

[0021] A first support layer is formed covering the sidewalls and top surface of the second part;

[0022] A first sacrificial layer is formed covering the sidewall of the first portion;

[0023] The second sacrificial layer shall be filled at least in the gaps between the first sacrificial layers;

[0024] Remove the first support layer to expose the sidewalls and top surface of the second portion;

[0025] Remove the first sacrificial layer to form a first filling region surrounding the first portion and expose the sidewalls of the first portion;

[0026] A first electrode layer is formed in the first filled region;

[0027] Remove the second sacrificial layer to form a second filling region surrounding the first electrode layer;

[0028] A dielectric layer and a second electrode layer are sequentially formed in the second filled region;

[0029] Multiple transistors are formed, wherein the channel structure of the transistors is located within the second portion, and the extension direction of the channel structure is the same as the extension direction of the second portion.

[0030] In the above scheme, a plurality of semiconductor pillars are formed on the substrate in an array along a first direction and a second direction, including:

[0031] Provide semiconductor substrates;

[0032] Multiple first trenches spaced apart along a first direction and multiple second trenches spaced apart along a second direction are formed in the semiconductor substrate; the first trenches divide the semiconductor substrate into multiple semiconductor strips, and the second trenches divide each semiconductor strip into multiple semiconductor pillars; the width of each semiconductor pillar along the first direction is different from the width of the semiconductor pillar along the second direction.

[0033] The method in the above scheme further includes:

[0034] Before the second trench is formed, a third sacrificial layer is formed on the sidewall of the first trench;

[0035] The bottom of each of the first trenches is enlarged.

[0036] Remove the third sacrificial layer;

[0037] The semiconductor strip is subjected to an oxidation treatment so that the portion of the semiconductor strip corresponding to the enlarged first trench is completely oxidized into an oxide strip, and the remaining surface of the semiconductor strip is oxidized into an oxide layer.

[0038] A first insulating material is filled into the gap between the oxide layer and the oxide strip.

[0039] The method in the above scheme further includes:

[0040] After a third sacrificial layer is formed on the sidewall of the first trench, a first insulating material is filled into the first trench in which the third sacrificial layer is formed.

[0041] Multiple second support layers are formed on the semiconductor strip and the first insulating material, spaced apart along the second direction; the first insulating material filling the first trench is removed, and the bottom of the first trench is enlarged.

[0042] In the above scheme, forming the second trench includes:

[0043] Using the second support layer as a mask, the semiconductor substrate is etched to form the second trench.

[0044] In the above scheme, forming the first support layer covering the sidewalls and top surface of the second part includes:

[0045] The space between the plurality of semiconductor pillars is filled with a first insulating material;

[0046] A portion of the first insulating material is removed along the first direction to form a plurality of first shallow trenches, the bottom surface of the first shallow trenches being flush with the bottom surface of the second portion;

[0047] A first support material is deposited on the top surface of the semiconductor pillar and within the first shallow trench.

[0048] A portion of the first insulating material is removed along the second direction to form a plurality of second shallow trenches, the bottom surface of each second shallow trench being flush with the bottom surface of the second portion;

[0049] The first support material is filled into the second shallow trench to form the first support layer.

[0050] In the above scheme, before forming the first sacrificial layer covering the sidewall of the first portion, the method further includes:

[0051] The first part is alloyed to reduce its resistance.

[0052] In the above scheme, the first part undergoes alloying treatment, including:

[0053] A metal layer is formed covering the sidewalls of the first part;

[0054] A rapid thermal annealing process is used to react the metal layer and the first part to form a metal compound.

[0055] In the above scheme, forming multiple transistors includes:

[0056] A gate structure is formed covering at least one side of the second portion;

[0057] The source and drain are formed at the two opposite ends of the second part, respectively.

[0058] This disclosure discloses a method for fabricating a semiconductor structure: Multiple semiconductor pillars are formed on a substrate, each pillar comprising a first portion and a second portion located on the first portion; a first support layer is formed covering the sidewalls and top surface of the second portion; a first sacrificial layer is formed covering the sidewalls of the first portion through the protection and support of the first support layer; a second sacrificial layer is filled at least in the gaps between the first sacrificial layers; self-isolating first electrode layers are fabricated using the double sacrificial layers (first and second sacrificial layers), resulting in a memory structure covering the sidewalls of the first portion, comprising a first electrode layer, a dielectric layer, and a second electrode layer; and a channel structure for the transistor located within the second portion is formed. In this disclosure, the multiple first electrode layers formed using the sacrificial layer method are independent of each other, improving the mutual interference problem between the multiple first electrode layers. Simultaneously, the sidewall conformality of each electrode layer and dielectric layer obtained using the double sacrificial layer method is better, thereby improving the performance of the semiconductor structure. Furthermore, forming the memory structure and transistor on the same active pillar reduces the difficulty of aligning the memory cell and the transistor, thus reducing the complexity of the fabrication process. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;

[0060] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0061] Figures 3 to 24e Cross-sectional and top views illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure;

[0062] Figure 25 This is a schematic diagram of a planar structure of a memory provided in an embodiment of this disclosure.

[0063] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0064] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0065] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0066] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0067] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0068] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0069] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0070] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0071] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0072] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0073] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0074] In some embodiments of this disclosure, whether planar transistors or buried transistors, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0075] Figure 1 This is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), the source region of transistor T is electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C can be connected to a reference voltage, which can be ground voltage or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0076] However, in order to achieve the miniaturization of memory, the size of dynamic random access memory is constantly shrinking, and the size of capacitors is also shrinking. This makes it increasingly difficult to align capacitors with transistors, and at the same time, there is the problem of mutual interference between multiple lower electrode plates of the capacitor during use.

[0077] In view of this, and to solve one or more of the above problems, this disclosure provides a method for fabricating a semiconductor structure. Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 2 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0078] S201. A substrate is provided, on which a plurality of semiconductor pillars are formed in an array along a first direction and a second direction; each semiconductor pillar includes a first portion and a second portion located on the first portion; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;

[0079] S202, Form a first support layer covering the sidewalls and top surface of the second part;

[0080] S203, A first sacrificial layer covering the sidewall of the first part;

[0081] S204. Fill at least the gaps in the first sacrificial layer with a second sacrificial layer;

[0082] S205. Remove the first support layer to expose the sidewalls and top surface of the second part;

[0083] S206. Remove the first sacrificial layer to form a first filling region surrounding the first portion and expose the sidewalls of the first portion;

[0084] S207. A first electrode layer is formed in the first filled region;

[0085] S208. Remove the second sacrificial layer to form a second filling region surrounding the first electrode layer;

[0086] S209. A dielectric layer and a second electrode layer are sequentially formed in the second filling region;

[0087] S210. A plurality of transistors are formed, wherein the channel structure of the transistors is located within the second portion, and the extension direction of the channel structure is the same as the extension direction of the second portion.

[0088] It should be understood that Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs.

[0089] Herein and in the following text, the first direction and the second direction refer to two orthogonal directions parallel to the top surface of the substrate; the third direction is the direction perpendicular to the top surface of the substrate, that is, the third direction is the extension direction of the semiconductor pillar; wherein, the top surface of the substrate can be understood as a plane perpendicular to the extension direction of the semiconductor pillar.

[0090] In some embodiments, the angle between the first direction and the second direction ranges from 0 to 90 degrees. In some specific embodiments, the first direction may be perpendicular to the second direction. It is understood that the angle between the first direction and the second direction establishes the positional relationship of the array arrangement of the semiconductor pillars along the first direction and the second direction.

[0091] For example, the first direction is represented by the X direction in the figure; the second direction is represented by the Y direction in the figure; and the third direction is represented by the Z direction in the figure.

[0092] Figures 3 to 24e The following are cross-sectional and top-view schematic diagrams illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. Figure 2 , Figures 3 to 24eThe method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0093] To clearly describe this disclosure, the following embodiments are illustrated using the example of a first direction being perpendicular to a second direction. For example, using... Figures 24a to 24e For example, the first direction is Figure 24e The X-axis direction shown in the figure; the second direction is Figure 24e The Y-axis direction is shown in the figure; the third direction is Figures 24a to 24d The Z-axis direction is shown in the figure. However, it should be noted that the description of the direction in the following embodiments is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0094] It should be noted that, Figures 4a to 24e Each figure with the same numerical designation represents a schematic diagram of multiple view planes under at least one process step; Figures 24a to 24e For example, Figure 24e This is a top-down view. Figures 24a to 24d They are respectively Figure 24e Cross-sectional view along the AA, BB, CC, and DD sections; Figures 4a to 23e And so on, which will not be repeated here or in the following text.

[0095] Execute step S201, refer to Figures 3 to 13e This forms multiple semiconductor pillars.

[0096] In some embodiments, a plurality of semiconductor pillars arranged in an array along a first direction and a second direction are formed on the substrate, including:

[0097] Provide semiconductor substrates;

[0098] Multiple first trenches spaced apart along a first direction and multiple second trenches spaced apart along a second direction are formed in the semiconductor substrate;

[0099] The first trench divides the semiconductor substrate into multiple semiconductor strips, and the second trench divides each semiconductor strip into multiple semiconductor pillars; the width of each semiconductor pillar along the first direction is different from the width of the semiconductor pillar along the second direction.

[0100] refer to Figure 3 The material of the semiconductor substrate 100 may include silicon (Si), germanium (Ge), silicon germanide (SiGe), etc.

[0101] refer to Figures 4a-4eThe top surface of the semiconductor substrate 100 is first etched using a lithography-etching (LE) process to form a plurality of first trenches T1 spaced apart along a first direction in the semiconductor substrate; here, each of the first trenches T1 extends along a second direction. The first trenches T1 divide the semiconductor substrate 100 into a plurality of semiconductor strips 102.

[0102] refer to Figures 13a-13e The top surface of the semiconductor substrate 100 is etched a second time using a photolithography-etching process to form a plurality of second trenches T2 spaced apart along a second direction in the semiconductor substrate; here, each second trench T2 extends along a first direction. The second trenches T2 divide each semiconductor strip 102 into a plurality of semiconductor pillars 103. It should be noted that... Figures 13a-13e The isolation structure 107 in the text will be discussed below. Figures 7a to 12e Please provide an explanation.

[0103] Here, the first trench T1 and the second trench T2 are located in the semiconductor substrate, that is, the depth of the first trench T1 and the second trench T2 along the third direction is less than the thickness of the semiconductor substrate 100 along the third direction.

[0104] In some embodiments, the first trench T1 and the second trench T2 include, but are not limited to, shallow trench isolation (STI) structures.

[0105] The first etching and the second etching include, but are not limited to, dry plasma etching processes.

[0106] In practical applications, the width of each semiconductor pillar 103 along the first direction is different from the width of the semiconductor pillar along the second direction, which helps to improve the stability of the semiconductor structure. For example, considering the stability of the formed semiconductor strip 102, the width of each semiconductor pillar 103 along the first direction can be greater than the width of the semiconductor pillar 103 along the second direction. That is, when forming the first trench T1, the width of the semiconductor strip 102 can be set to be wider. In this way, when the first trench T1 has a high aspect ratio, because the width of the semiconductor strip 102 is set to be wider, it has a lower aspect ratio relative to the first trench T1. The semiconductor strip 102 has better support and will not collapse, thus helping to improve the stability of the semiconductor structure.

[0107] In some embodiments, the method further includes:

[0108] Before the second trench is formed, a third sacrificial layer is formed on the sidewall of the first trench;

[0109] The bottom of each of the first trenches is enlarged.

[0110] Remove the third sacrificial layer;

[0111] The semiconductor strip is subjected to an oxidation treatment so that the portion of the semiconductor strip corresponding to the enlarged first trench is completely oxidized into an oxide strip, and the remaining surface of the semiconductor strip is oxidized into an oxide layer.

[0112] The first insulating material is filled into the gap between the oxide layer and the oxide strip.

[0113] refer to Figures 5a-5e This forms the third sacrificial layer 223.

[0114] The material of the third sacrificial layer 223 may include, but is not limited to, silicon nitride.

[0115] In practical applications, the third sacrificial material can be deposited on the sidewalls and bottom of the first trench T1 using processes such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD). The third sacrificial material at the bottom of the first trench T1 can be removed using plasma etching or reactive ion etching.

[0116] For example, using the Plasma Enhanced Chemical Vapor Deposition (PECVD) method, silicon nitride is deposited on the sidewalls and bottom of the first trench T1 using a reverse top selective deposition (RTS) process. Then, a plasma etching process is used to remove the silicon nitride at the bottom of the first trench T1 with hydrofluoric acid, resulting in silicon nitride remaining on the sidewalls of the first trench.

[0117] It should be noted that, using the RTS process, as the depth of the first trench T1 increases, the thickness of the third sacrificial layer 223 deposited on the sidewall of the first trench also increases. This ensures that even when the first trench T1 has a high aspect ratio, a thicker third sacrificial layer can be deposited on the bottom sidewall of the semiconductor strip 102, better protecting the bottom of the semiconductor strip 102 during subsequent enlargement of the first trench bottom.

[0118] refer to Figures 9a-9eUsing the third sacrificial layer 223 as a mask, the bottom of each of the first trenches T1 is enlarged to form a third trench T3 with a bowl-shaped space.

[0119] The etching process used here may include wet etching process, dry etching process, etc.

[0120] For example, in the wet etching process, using the third sacrificial layer 223 as a mask, the etchant is introduced into the bottom of the first trench T1. Through isotropic etching of the etchant, the diameter of the bottom of the first trench T1 along the X-axis is increased. That is, the diameter of the transition portion between the bottom of the semiconductor strip 102 and the substrate 101 along the X-axis is smaller than the diameter of the semiconductor strip 102 along the X-axis. It can be understood that, at the same time, due to the isotropic etching of the etchant, a third trench T3 with a bowl-shaped space is formed, increasing the depth of the bottom of the first trench T1 along the Z-axis.

[0121] refer to Figures 10a-10e Remove the third sacrificial layer; expose the sidewalls of the semiconductor strip 102.

[0122] refer to Figures 11a-11e The semiconductor strip 102 is subjected to oxidation treatment.

[0123] For example, the semiconductor strip 102 is oxidized by an oxidation process, such that the entire transition portion between the bottom of the semiconductor strip 102 and the substrate 101 is oxidized into an oxide strip 104, and the surface of the exposed second portion of the semiconductor strip is oxidized into an oxide layer 106. At the same time, the top surface of the substrate 101 is also oxidized to form a substrate oxide layer 105.

[0124] Here, the oxide strip 104 and the oxide layer 106 are made of the same material. For example, the constituent materials of the oxide strip 104 and the oxide layer 106 include, but are not limited to, silicon oxide.

[0125] It should be noted that, in the aforementioned embodiments, after enlarging the first trench T1, the transition portion between the bottom of the semiconductor strip 102 and the substrate 101 is relatively small and easily oxidized completely. Meanwhile, the semiconductor strip 102, being relatively large in size, is oxidized only on its surface.

[0126] After the semiconductor strip 102 is oxidized, the semiconductor strip 102 and the substrate 101 are electrically isolated by the oxide strip 104; this prevents leakage defects between the semiconductor strip 102 and the substrate 101.

[0127] It should be noted that in the foregoing embodiments, when forming the first trench T1, the width of the semiconductor strip 102 can be set to be relatively wide, so that after the semiconductor strip 102 is oxidized, the effective size of the semiconductor strip 102 that is not oxidized will not become very small.

[0128] refer to Figures 12a-12e The first insulating material is filled into the gap between the oxide layer and the oxide strip to form an isolation structure.

[0129] Here, the method of filling the first insulating material 201 includes, but is not limited to, processes such as PVD and CVD.

[0130] The first insulating material 201 may be made of the same or different materials as the oxide strip 104 and the oxide layer 106. For example, the constituent materials of the first insulating material 201 include, but are not limited to, silicon oxide.

[0131] In practical applications, a first insulating material 201 can be filled between multiple oxide strips 104 and between multiple semiconductor strips 102 on which oxide layers 106 are formed, such that the first insulating material 201 is substantially flush with the top surface of the semiconductor strips 102. The first insulating material 201 between the multiple oxide strips 104, together with the oxide strips 104 and the substrate oxide layer 105, constitutes an isolation structure 107 on the substrate 101. Exemplarily, the constituent materials of the isolation structure 107 include, but are not limited to, silicon oxide. The isolation structure 107 can improve the functional devices (e.g., hereinafter) on which the isolation structure 107 is located. Figures 24a-24e The leakage problem between the semiconductor pillar 103, the storage structure 315 and the substrate 101.

[0132] In some embodiments, the method further includes:

[0133] After a third sacrificial layer is formed on the sidewall of the first trench, a first insulating material is filled into the first trench in which the third sacrificial layer is formed.

[0134] Multiple second support layers are formed on the semiconductor strip and the first insulating material, spaced apart along the second direction; the first insulating material filling the first trench is removed, and the bottom of the first trench is enlarged.

[0135] refer to Figures 6a-6e The first insulating material 201 is filled in the first trench T1 in which the third sacrificial layer 223 is formed.

[0136] Here, the method of filling the first insulating material 201 includes, but is not limited to, processes such as PVD and CVD.

[0137] Here, the first insulating material 201 is made of a different material than the third sacrificial layer 223. For example, the constituent materials of the first insulating material 201 include, but are not limited to, silicon oxide.

[0138] refer to Figures 7a-7e This forms multiple second support layers 212.

[0139] Here, a second support material covering the first insulating material 201 and the semiconductor strip 102 is formed by processes including but not limited to PVD and CVD; then, the second support material is formed into multiple second support layers 212 arranged at intervals along the second direction by photolithography-etching process.

[0140] Here, the material of the second support layer 212 is different from the materials of the first insulating material 201 and the third sacrificial layer 223. For example, the constituent materials of the second support layer 212 include, but are not limited to, carbon.

[0141] refer to Figures 8a-8e Using the second support layer 212 as the support layer, remove Figures 6a-6e The first insulating material 201 is filled in the first trench, and the bottom of the first trench is enlarged.

[0142] Since the multiple semiconductor strips 102 arranged at intervals along the first direction are supported by the second support layer 212, they have a more stable structure, which makes it easier to expand the bottom of the first trench.

[0143] It is understandable that during the widening process of the bottom of the first trench, because part of the bottom of the semiconductor strip 102 is removed, the diameter of the bottom of the semiconductor strip 102 along the X-axis is smaller than the diameter of the middle and top of the semiconductor strip 102 along the X-axis and / or the diameter of the bottom of the semiconductor strip 102 along the Y-axis is smaller than the diameter of the middle and top of the semiconductor strip 102 along the Y-axis. The bottom of the semiconductor strip 102 lacks effective support, which can easily lead to the semiconductor strip 102 tilting and collapsing. At this time, using the second support layer 212 as the support layer, during the formation of the semiconductor strip 102, oxide strip 104, and isolation structure 107 (refer to...), Figures 11a-11e , Figures 12a-12e The second support layer 212 plays a role in structural support and preventing collapse, which is conducive to the stability of the formed semiconductor structure.

[0144] In some embodiments, forming the second trench includes:

[0145] Using the second support layer as a mask, the semiconductor substrate is etched to form the second trench.

[0146] Refer to the above Figures 7a-7eMultiple second support layers 212 are formed by adjusting the parameters of the photolithography-etching process, spaced apart along a second direction. These second support layers 212 extend along a first direction and cover a portion of the top surface of the semiconductor strip 102. The portion of the top surface of the semiconductor strip 102 covered by the second support layers 212 serves to protect the formation of the semiconductor pillar 103. (Reference) Figures 13a-13e The second support layer 212 serves as a support layer and also as a mask for forming the second trench T2. This is beneficial for the stability of the semiconductor structure, saves process steps, simplifies the process, and reduces manufacturing costs.

[0147] The etching process used here may include wet etching process, dry etching process, etc.

[0148] For example, in the dry etching process, the second support layer 212 is used as a mask to etch and form a plurality of second trenches T2 arranged at intervals along the second direction, and the second trenches T2 penetrate the semiconductor strip 102 along the Z-axis direction.

[0149] It should be noted that after forming the second trench T2, the process also includes filling the second trench T2 with the first insulating material 201 (see reference). Figures 14a-14e ).

[0150] Here, the method of filling the first insulating material 201 includes, but is not limited to, processes such as PVD and CVD.

[0151] Here, the first insulating material 201 may be the same as or different from the material of the isolation structure 107. For example, the constituent materials of the first insulating material 201 include, but are not limited to, silicon oxide.

[0152] Furthermore, after the second trench T2 is filled with the first insulating material 201, the second support layer 212 is removed; the top surfaces of the first insulating material 201 and the semiconductor pillar 103 are subjected to chemical mechanical polishing (CMP) to make the top surfaces of the first insulating material 201 and the semiconductor pillar 103 flush.

[0153] Perform step S202 to form the first support layer.

[0154] In some embodiments, the formation of the first support layer covering the sidewalls and top surface of the second portion includes:

[0155] The space between the plurality of semiconductor pillars is filled with a first insulating material;

[0156] A portion of the first insulating material is removed along the first direction to form a plurality of first shallow trenches, the bottom surface of the first shallow trenches being flush with the bottom surface of the second portion;

[0157] A first support material is deposited on the top surface of the semiconductor pillar and within the first shallow trench.

[0158] A portion of the first insulating material is removed along the second direction to form a plurality of second shallow trenches, the bottom surface of each second shallow trench being flush with the bottom surface of the second portion;

[0159] The first support material is filled into the second shallow trench to form the first support layer.

[0160] refer to Figures 14a-14e The space between the plurality of semiconductor pillars 103 is filled with a first insulating material 201.

[0161] Here, the method of filling the first insulating material 201 includes, but is not limited to, processes such as PVD and CVD.

[0162] Here, the first insulating material 201 may be the same as or different from the material of the isolation structure 107. For example, the first insulating material 201 may be the same as the material of the isolation structure 107, and the constituent materials of the first insulating material 201 include, but are not limited to, silicon oxide.

[0163] refer to Figures 15a to 16e This forms the first support layer.

[0164] A third etching process is performed on the first insulating material 201 using photolithography-etching to form a plurality of first shallow trenches ST1 arranged in an array along a first direction and a second direction. Each first shallow trench ST1 is located between adjacent second portions 1032 along the first direction. The bottom surface of each first shallow trench ST1 is flush with the bottom surface of the second portion 1032, exposing the opposing sidewalls between adjacent second portions 1032 along the first direction. A first support material is deposited on the top surface of the semiconductor pillar 103 and within the first shallow trenches ST1.

[0165] A fourth etching process is performed on the first insulating material 201 using photolithography-etching to form a plurality of second shallow trenches ST2 arranged in an array along a first direction and a second direction. Each second shallow trench ST2 is located between adjacent second portions 1032 along the second direction. The bottom surface of each second shallow trench ST2 is flush with the bottom surface of the second portion 1032, exposing the opposing sidewalls between adjacent second portions 1032 along the second direction. A first support material is deposited on the top surface of the semiconductor pillar 103 and within the second shallow trenches ST2 to form the first support layer 211. The method for filling the first support material includes, but is not limited to, processes such as PVD and CVD.

[0166] The third etching and the fourth etching include, but are not limited to, dry plasma etching processes.

[0167] Here, the first support material is different from the first insulating material 201. For example, the components of the first support material include, but are not limited to, carbon.

[0168] refer to Figures 17a-17e Remove the first insulating material 201 between the plurality of semiconductor pillars 103 (see reference). Figures 16a-16e ); to expose the sidewall of the first part 1031.

[0169] The portion of the first support layer 211 covering the sidewalls of the second part 1032 protects the sidewalls of the second part 1032; the portion of the first support layer 211 covering the top surface of the second part 1032 protects the top surface of the second part 1032. Simultaneously, the portion of the first support layer 211 covering the top surface of the second part 1032 forms a mesh structure, which facilitates effective support for the semiconductor pillars 103. In other words, the first support layer 211 protects both the sidewalls and top surface of the second part 1032 and supports the multiple semiconductor pillars 103 arranged in the array, thus facilitating the formation of a stable semiconductor structure.

[0170] In some embodiments, prior to forming the first sacrificial layer covering the sidewall of the first portion, the method further includes:

[0171] The first part is alloyed to reduce its resistance.

[0172] Refer to the above Figures 17a-17e Since the first support layer 211 protects both the sidewalls and top surface of the second portion 1032 and supports the array of semiconductor pillars 103, it is advantageous to alloy the exposed sidewalls of the first portion 1031 to obtain a first portion 1031 with lower resistivity.

[0173] In some embodiments, alloying the first portion includes:

[0174] A metal layer is formed covering the sidewalls of the first part;

[0175] A rapid thermal annealing process is used to react the metal layer and the first part to form a metal compound.

[0176] Continue to refer to the above. Figures 17a-17e Here, the methods for forming the metal layer include, but are not limited to, processes such as PVD, CVD, and ALD.

[0177] A rapid thermal annealing (RTP) process is used to react the metal layer and the first portion to form a metal compound.

[0178] Here, the material of the metal layer is conducive to forming a compound with the material of the first portion 1031, and the compound is capable of reducing the resistivity of the first portion 1031. For example, the constituent materials of the metal layer include, but are not limited to, one of cobalt (Co), nickel (Ni), zinc (Zn), silver (Ag), and titanium (Ti).

[0179] For example, the metal layer is composed of cobalt (Co), and the first portion 1031 is composed of silicon (Si). After a rapid thermal annealing process (RTP), cobalt reacts with silicon to generate cobalt silicide. Due to the presence of cobalt silicide, the resistivity of the first portion 1031 that has undergone alloying treatment is lower than that of the first portion 1031 that has not undergone alloying treatment, which is beneficial to reduce resistance.

[0180] Execute step S203, refer to Figures 18a-18e This forms a first sacrificial layer 221 covering the sidewall of the first portion 1031.

[0181] The material of the first sacrificial layer 221 may include, but is not limited to, silicon nitride.

[0182] The formation process of the first sacrificial layer 221 can be referred to the above. Figures 5a-5e The process of forming the third sacrificial layer will not be elaborated here.

[0183] It should be noted that when the first sacrificial layer 221 is formed using the RTS process, a thicker first sacrificial layer 221 can also be deposited on the bottom sidewall of the first portion 1031 in the extension direction of the first portion 1031, and closer to the substrate 101. In this way, the thickness of the first sacrificial layer 221 in the extension direction of the first portion 1031 can avoid unevenness.

[0184] In practical applications, each of the first sacrificial layers 221 surrounds the sidewall of the first portion 1031. Furthermore, the multiple first sacrificial layers 221 are independent of each other.

[0185] Execute step S204, refer to Figures 19a-19e The second sacrificial layer 222 is filled at least in the gaps of the first sacrificial layer 221. For example, the second sacrificial layer 222 is filled in the gaps of the first sacrificial layer 221 and the gaps of the first support layer 211.

[0186] The material of the second sacrificial layer 222 is different from that of the first sacrificial layer 221. The material of the second sacrificial layer 222 may include, but is not limited to, polycrystalline silicon.

[0187] In practical applications, the second sacrificial layer 222 can be filled using processes such as PVD, CVD, and ALD.

[0188] Execute step S205, refer to Figures 20a-20e Remove the first support layer 211 (reference) Figures 19a-19e This exposes the sidewalls and top surface of the second part 1032.

[0189] Execute step S206, refer to Figures 21a-21e Remove the first sacrificial layer 221 (reference) Figures 20a-20e This forms a first filling region A1 surrounding the first portion 1031 and exposes the sidewalls of the first portion 1031.

[0190] Execute step S207, refer to Figures 22a-22e A first electrode layer 3151 is formed in the first filling region A1.

[0191] In practical applications, each of the first filling regions A1 surrounds the sidewall of the first portion 1031; and the plurality of first filling regions A1 are independent of each other. A self-aligned filling space for filling the first electrode layer 3151 is formed between the first portion 1031 and the second sacrificial layer 222.

[0192] Here, the first electrode layer 3151 can be filled using processes such as PVD, CVD, and ALD.

[0193] In some specific embodiments, the constituent materials of the first electrode layer 3151 may include, but are not limited to, ruthenium (Ru), ruthenium oxide (RuO), and titanium nitride (TiN).

[0194] Execute step S208, refer to Figures 23a-23e Remove the second sacrificial layer 222 (reference) Figures 22a-22e This forms a second filling region A2 surrounding the first electrode layer 3151;

[0195] Execute step S209, refer to Figures 24a-24e A dielectric layer 3152 and a second electrode layer 3153 are sequentially formed in the second filling region A2.

[0196] In practical applications, each of the second filling regions A2 surrounds the sidewall of the first electrode layer 3151; between the first electrode layers 3151, a self-aligned filling space is formed for filling the dielectric layer 3152 and the second electrode layer 3153.

[0197] Here, the dielectric layer 3152 and the second electrode layer 3153 can be filled by processes such as PVD, CVD, and ALD.

[0198] The dielectric layer 3152 is composed of high-k dielectric materials, which generally refer to materials with a dielectric constant higher than 3.9, and are typically significantly higher than this value. In some specific examples, the material of the dielectric layer may include, but is not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), strontium titanate (SrTiO3), etc.

[0199] In some specific embodiments, the constituent materials of the second electrode layer 3153 may include, but are not limited to, ruthenium, ruthenium oxide, and titanium nitride.

[0200] In this embodiment, a first sacrificial layer is formed covering the sidewalls of the first portion through the protection and support of the first support layer, and a second sacrificial layer is filled at least in the gaps between the first sacrificial layers. A self-isolating first electrode layer is formed from the double sacrificial layer consisting of the first and second sacrificial layers, resulting in a storage structure covering the sidewalls of the first portion, comprising a first electrode layer, a dielectric layer, and a second electrode layer. In this embodiment, the multiple first electrode layers formed using the sacrificial layer method are independent of each other, improving the mutual interference problem between the multiple first electrode layers. Simultaneously, the sidewalls of the electrode layers and dielectric layers obtained using the double sacrificial layer method have good conformal preservation, thereby improving the performance of the semiconductor structure.

[0201] Figure 25 This is a schematic diagram of a planar structure of a memory provided in an embodiment of this disclosure; Figure 25 This can be understood as being in Figure 24e The memory, further formed on this basis, includes a transistor structure as well as word lines and bit lines. To maintain consistency with the above-described behavior, Figure 25 The arrangement of semiconductor pillars (SPs) in the diagram can be referenced. Figure 24e The second part, 1032, is explained in the arrangement. Figure 25 The AA, BB, CC, and DD sections can also be referenced. Figure 24e To understand the cross-sectional position in the text; among them, Figure 25 The AA section in the diagram represents a plane along the YZ plane that passes through a row of transistors extending along the second direction; Figure 25The BB section in the diagram represents a plane along the YZ plane that does not pass through a row of transistors arranged along the second direction; Figure 25 The CC section in the figure represents a plane along the XZ plane that passes through a row of transistors arranged along the first direction; Figure 25 The DD profile in the diagram represents a plane along the XZ plane that does not pass through the first row of transistors.

[0202] It should be noted that, Figure 25 The image shows semiconductor pillars SP, word lines WL, and bit lines BL in the memory, projected onto an XY plane. The extension directions of word lines WL and BL are perpendicular to each other. Word lines WL extend along a first direction and are arranged along a second direction, while word lines BL extend along the second direction and are arranged along the first direction. The channel structure (not shown) in the semiconductor pillar SP, the source and drain (not shown) formed at both ends along the extension direction of the semiconductor pillar SP, and the gate structure (not shown) surrounding the sidewall of the semiconductor pillar SP constitute the transistors of the memory. It is understood that the gate structure (not shown) surrounding the sidewall of the semiconductor pillar SP electrically connects the gate of each transistor in each row of crystals arranged along the first direction.

[0203] Step S210 is performed to form a plurality of transistors, wherein the channel structure of the transistors is located within the second portion and the extension direction of the channel structure is the same as the extension direction of the second portion.

[0204] In some embodiments, forming a plurality of transistors includes:

[0205] A gate structure is formed covering at least one side of the second portion;

[0206] The source and drain are formed at the two opposite ends of the second part, respectively.

[0207] Here, the gate shape differs in different types of transistors; for example, refer to... Figure 25 In a columnar gate transistor, the gate is formed in a columnar shape on one side of the channel region; in a semi-around gate transistor, the gate partially surrounds the channel region; in a gate all around (GAA) transistor, the gate completely surrounds the channel region.

[0208] The transistor types in the embodiments of this disclosure may include, but are not limited to, the types described above. Preferably, refer to... Figure 25 The transistor is a fully surround gate transistor.

[0209] It should be noted that the gate structure here includes the gate (G) and the gate oxide layer; the gate oxide layer is located between the gate and the channel region, and is used to electrically isolate the channel region and the gate, thereby reducing the hot carrier effect of the transistor.

[0210] Here, the gate material may include metals and / or polysilicon, etc. The gate oxide layer material may include, but is not limited to, silicon oxide.

[0211] In some embodiments, the methods for forming the gate include, but are not limited to, PVD, CVD, ALD, etc. Methods for forming the gate oxide layer include, but are not limited to, in-situ oxidation.

[0212] The source and drain are formed at opposite ends of the second part, respectively.

[0213] In some specific embodiments, the methods for forming the source and drain include, but are not limited to, ion implantation and diffusion processes.

[0214] It should be noted that the positions of the source and drain at opposite ends of the second part can be interchanged; in practice, the selection and setting can be made according to actual needs.

[0215] It is understood that the memory in the above embodiment is a transistor-capacitor (TOC) structure, which further includes multiple bit lines located on the transistor and electrically contacting the top of the second part.

[0216] Therefore, in some embodiments, reference Figure 25 The method further includes forming a bit line BL on the transistor.

[0217] It is understood that the bit line BL is used to perform read or write operations on the transistor when the transistor is turned on.

[0218] Here, placing the bit line BL above the transistor and treating the bit line BL as a metal bit line can reduce resistance and simplify the manufacturing process; it is also more compatible with the circuit design of the memory.

[0219] Based on this, the present disclosure proposes a method for fabricating a semiconductor structure: a plurality of semiconductor pillars are formed on a substrate, each pillar comprising a first portion and a second portion located on the first portion; a first support layer is formed covering the sidewalls and top surface of the second portion; a first sacrificial layer is formed covering the sidewalls of the first portion through the protection and support of the first support layer; a second sacrificial layer is filled at least in the gaps between the first sacrificial layers; a self-isolating first electrode layer is formed from the double sacrificial layer composed of the first and second sacrificial layers, resulting in a memory structure including a first electrode layer, a dielectric layer, and a second electrode layer covering the sidewalls of the first portion; and a channel structure of the transistor located within the second portion is formed. In this disclosure, the plurality of first electrode layers formed using the sacrificial layer method are independent of each other, improving the mutual interference problem between the plurality of first electrode layers. Simultaneously, the sidewalls of the electrode layers and dielectric layers obtained using the double sacrificial layer method have good conformal preservation, thereby improving the performance of the semiconductor structure. Furthermore, forming the memory structure and transistor on the same active pillar reduces the difficulty of aligning the memory cell and the transistor, thereby reducing the complexity of the manufacturing process.

[0220] According to another aspect of this disclosure, embodiments of this disclosure provide a semiconductor structure, including: a substrate, a plurality of semiconductor pillars located above the substrate, a memory structure, and a plurality of transistors;

[0221] The plurality of semiconductor pillars are arranged in an array along a first direction and a second direction; each semiconductor pillar includes a first portion and a second portion located on the first portion; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;

[0222] The storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer; the first electrode layer covers the sidewall of the first portion, and the first electrode layer is located in spaced-apart first filling regions, each of the first filling regions surrounding the sidewall of each of the first portions; the dielectric layer at least covers the surface of the first electrode layer; the second electrode layer covers the surface of the dielectric layer.

[0223] The channel structure of each transistor is located within the second portion, and the channel structure extends in the same direction as the second portion.

[0224] In some embodiments, the cross-sectional shape of the channel structure includes an ellipse or a long strip.

[0225] In some embodiments, the material of the second part is different from the material of the first part.

[0226] In some embodiments, the material of the first part includes a metal compound, and the material of the second part includes a semiconductor material.

[0227] In some embodiments, the substrate includes an isolation structure on which a plurality of the active pillars are located.

[0228] In some embodiments, the transistor includes:

[0229] A gate structure covering at least one side of the second portion; and

[0230] The source and drain are respectively located at the two opposite ends of the second part.

[0231] In some embodiments, the semiconductor structure further includes:

[0232] Multiple bit lines are located on the transistor and electrically connected to the top of the second portion.

[0233] Figure 25 This is a schematic diagram of a planar structure of a memory provided in an embodiment of this disclosure. To maintain consistency with the above-described behavior, Figure 25 The arrangement of semiconductor pillars (SPs) in the diagram can be referenced. Figure 24e The second part, 1032, is explained in the arrangement. Figure 25 The AA, BB, CC, and DD sections can also be referenced. Figure 24e To understand the cross-sectional position in the text; among them, Figure 25 The AA section in the diagram represents a plane along the YZ plane that passes through a row of transistors extending along the second direction; Figure 25 The BB section in the diagram represents a plane along the YZ plane that does not pass through a row of transistors arranged along the second direction; Figure 25 The CC section in the figure represents a plane along the XZ plane that passes through a row of transistors arranged along the first direction; Figure 25 The DD profile in the diagram represents a plane along the XZ plane that does not pass through the first row of transistors.

[0234] It should be noted that, Figure 25The image shows semiconductor pillars SP, word lines WL, and bit lines BL in the memory, projected onto an XY plane. The extension directions of word lines WL and BL are perpendicular to each other. Word lines WL extend along a first direction and are arranged along a second direction, while word lines BL extend along the second direction and are arranged along the first direction. The channel structure (not shown) in the semiconductor pillar SP, the source and drain (not shown) formed at both ends along the extension direction of the semiconductor pillar SP, and the gate structure (not shown) surrounding the sidewall of the semiconductor pillar SP constitute the transistors of the memory. It is understood that the gate structure (not shown) surrounding the sidewall of the semiconductor pillar SP electrically connects the gate of each transistor in each row of crystals arranged along the first direction.

[0235] The semiconductor structure provided in this disclosure is similar to the semiconductor structure manufactured by the method described in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0236] According to another aspect of this disclosure, a memory is provided, comprising: one or more semiconductor structures as described in any of the embodiments of this disclosure above.

[0237] Based on this, in the embodiments of this disclosure, by providing a corresponding isolation structure between each active pillar and the substrate, the storage structure (e.g., capacitor) formed on a portion of the sidewall of the active pillar can be isolated, thereby reducing the leakage problem of the storage structure (e.g., capacitor) during use.

[0238] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0239] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided on which a plurality of semiconductor pillars are formed in an array along a first direction and a second direction; each semiconductor pillar includes a first portion and a second portion located on the first portion; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; A first support layer is formed covering the sidewalls and top surface of the second part; A first sacrificial layer is formed covering the sidewall of the first portion; The second sacrificial layer shall be filled at least in the gaps between the first sacrificial layers; Remove the first support layer to expose the sidewalls and top surface of the second portion; Remove the first sacrificial layer to form a first filling region surrounding the first portion and expose the sidewalls of the first portion; A first electrode layer is formed in the first filled region; Remove the second sacrificial layer to form a second filling region surrounding the first electrode layer; A dielectric layer and a second electrode layer are sequentially formed in the second filled region; Multiple transistors are formed, wherein the channel structure of the transistors is located within the second portion, and the extension direction of the channel structure is the same as the extension direction of the second portion.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, A plurality of semiconductor pillars are formed on the substrate in an array along a first direction and a second direction, including: Provide semiconductor substrates; Multiple first trenches spaced apart along a first direction and multiple second trenches spaced apart along a second direction are formed in the semiconductor substrate; the first trenches divide the semiconductor substrate into multiple semiconductor strips, and the second trenches divide each semiconductor strip into multiple semiconductor pillars; the width of each semiconductor pillar along the first direction is different from the width of the semiconductor pillar along the second direction.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The method further includes: Before the second trench is formed, a third sacrificial layer is formed on the sidewall of the first trench; The bottom of each of the first trenches is enlarged. Remove the third sacrificial layer; The semiconductor strip is subjected to an oxidation treatment so that the portion of the semiconductor strip corresponding to the enlarged first trench is completely oxidized into an oxide strip, and the remaining surface of the semiconductor strip is oxidized into an oxide layer. A first insulating material is filled into the gap between the oxide layer and the oxide strip.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The method further includes: After a third sacrificial layer is formed on the sidewall of the first trench, a first insulating material is filled into the first trench in which the third sacrificial layer is formed. Multiple second support layers are formed on the semiconductor strip and the first insulating material, spaced apart along the second direction; the first insulating material filling the first trench is removed, and the bottom of the first trench is enlarged.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, Forming the second trench includes: Using the second support layer as a mask, the semiconductor substrate is etched to form the second trench.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first support layer forming the sidewalls and top surface covering the second portion includes: The space between the plurality of semiconductor pillars is filled with a first insulating material; A portion of the first insulating material is removed along the first direction to form a plurality of first shallow trenches, the bottom surface of the first shallow trenches being flush with the bottom surface of the second portion; A first support material is deposited on the top surface of the semiconductor pillar and within the first shallow trench. A portion of the first insulating material is removed along the second direction to form a plurality of second shallow trenches, the bottom surface of each second shallow trench being flush with the bottom surface of the second portion; The first support material is filled into the second shallow trench to form the first support layer.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Before forming the first sacrificial layer covering the sidewall of the first portion, the method further includes: The first part is alloyed to reduce its resistance.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The first part is subjected to alloying treatment, including: A metal layer is formed covering the sidewalls of the first part; A rapid thermal annealing process is used to react the metal layer and the first part to form a metal compound.

9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of multiple transistors includes: A gate structure is formed covering at least one side of the second portion; The source and drain are formed at the two opposite ends of the second part, respectively.

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