Semiconductor structure and its fabrication method, memory

By employing a semiconductor structure fabrication method in dynamic random access memory, and utilizing a sacrificial layer to form independent electrode and dielectric layers, the problems of capacitor and transistor alignment difficulties and mutual interference are solved, thereby improving the performance and stability of the memory.

CN117320439BActive Publication Date: 2026-05-26CHANGXIN MEMORY TECH INC
2 Cites 0 Cited by

Patent Information

Application Number
CN202210709242.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-06-21
Publication Date
2026-05-26
Estimated Expiration
2042-06-21

AI Technical Summary

Technical Problem

As the size of dynamic random access memory (DRAM) shrinks, the size of capacitors also shrinks, which increases the difficulty of aligning capacitors with transistors and causes mutual interference between the capacitor's lower electrode plates.

Method used

The semiconductor structure fabrication method involves forming multiple semiconductor pillars on a substrate and using a sacrificial layer to form independent first electrode layers and dielectric layers, thereby improving mutual interference between electrode layers. At the same time, memory structures and transistors are formed on the same active pillar, reducing alignment difficulty.

Benefits of technology

This improves the performance of the semiconductor structure, reduces the difficulty of aligning memory cells and transistors, mitigates mutual interference between electrode layers, and enhances the stability and reliability of the memory.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory. The semiconductor structure includes: a substrate, a plurality of semiconductor pillars located above the substrate, a memory structure, and a plurality of transistors. The plurality of semiconductor pillars are arranged in an array along a first direction and a second direction. Each semiconductor pillar includes a first portion and a second portion located on the first portion. The first and second directions intersect and are both parallel to the top surface of the substrate. The memory structure includes a first electrode layer, a dielectric layer, and a second electrode layer. The first electrode layer covers the sidewalls of the first portion and is located in spaced-apart first filling regions, each first filling region surrounding the sidewalls of each first portion. The dielectric layer at least covers the surface of the first electrode layer. The second electrode layer covers the surface of the dielectric layer. The channel structure of each transistor is located within the second portion, and the extension direction of the channel structure is the same as the extension direction of the second portion.
Need to check novelty before this filing date? Find Prior Art