Driving circuit and driving method thereof, display device

Abstract

The application provides a driving circuit and a driving method thereof and a display device, and relates to the technical field of display. The driving circuit comprises an input module, an output module, a pull-up module, an adjusting module, a pull-down module and a reset module. After the pull-up module pulls up the voltage of a first node, and when the pull-up module has bootstrap effect, the voltage of the first node continuously rises. The adjusting module can discharge the scanning signal input end to pull down the voltage of the first node, so as to avoid the problem that the voltage of the first node is too large, and further avoid the problem that the service life of a device electrically connected to the first node is reduced or the performance of the device is unstable, thereby improving the stability of the driving circuit.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit and driving method thereof, and a display device. Background Technology

[0002] Gate Driver On Array (GOA) is a technology that integrates gate driving circuitry onto an array substrate. The gate driving circuitry includes multiple shift registers, each corresponding to a row of gate lines, and these shift registers sequentially output scan signals. With the rapid development of display technology, gate driving circuitry technology has matured, and the industry's performance requirements for the shift registers within the gate driving circuitry are becoming increasingly stringent. Summary of the Invention

[0003] The embodiments of this application adopt the following technical solutions:

[0004] In a first aspect, embodiments of this application provide a driving circuit including a plurality of cascaded shift registers, the shift registers including:

[0005] The input module is electrically connected to the scan signal input terminal of the shift register and the first node, respectively, and is configured to charge the first node when a scan signal is received from the scan signal input terminal;

[0006] The output module is electrically connected to the first clock signal input terminal of the shift register, the first node, and the signal output terminal of the shift register, respectively, and is configured to output a scan signal from the signal output terminal according to the first clock signal input terminal under the control of the voltage of the first node.

[0007] The pull-up module is electrically connected to the first node and the signal output terminal respectively, and is configured to pull up the voltage of the first node;

[0008] The adjustment module is electrically connected to the scan signal input terminal, the signal output terminal and the first node respectively, and is configured to pull down the voltage of the first node when the adjustment module performs a bootstrap action;

[0009] The pull-down module is electrically connected to the pull-down control signal input terminal of the shift register, the first power signal input terminal of the shift register, and the first node, and is configured to pull down the voltage of the first node.

[0010] The reset module is electrically connected to the pull-down module, the reset signal input terminal of the shift register, and the signal output terminal, and is configured to reset the drive circuit.

[0011] In some embodiments of this application, the input module includes a first transistor, the control electrode and the first electrode of the first transistor are both electrically connected to the scan signal input terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0012] In some embodiments of this application, the input module includes a first transistor, the control electrode of the first transistor is electrically connected to the scan signal input terminal, the first electrode of the first transistor is electrically connected to the second power supply signal input terminal of the shift register, and the second electrode of the first transistor is electrically connected to the first node.

[0013] In some embodiments of this application, the output module includes a third transistor, the control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first clock signal input terminal, and the second electrode of the third transistor is electrically connected to the signal output terminal.

[0014] In some embodiments of this application, the reset module includes a second transistor and a fourth transistor, wherein the control electrode of the second transistor and the control electrode of the fourth transistor are respectively electrically connected to the reset signal input terminal;

[0015] The first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first power signal input terminal; the first terminal of the fourth transistor is electrically connected to the signal output terminal, and the second terminal of the fourth transistor is electrically connected to the first power signal input terminal.

[0016] In some embodiments of this application, the pull-down module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0017] The first terminal of the fifth transistor, the first terminal of the eighth transistor, and the control terminal of the eighth transistor are all electrically connected to the pull-down control signal input terminal. The control terminal of the fifth transistor is electrically connected to the second terminal of the eighth transistor. The second terminal of the fifth transistor, the first terminal of the sixth transistor, the control terminal of the ninth transistor, and the control terminal of the tenth transistor are all electrically connected to the second node. The second terminals of the sixth transistor, the seventh transistor, the ninth transistor, and the tenth transistor are all electrically connected to the first power signal input terminal. The control terminals of the sixth transistor, the seventh transistor, and the ninth transistor are all electrically connected to the first node. The first terminal of the seventh transistor is electrically connected to the control terminal of the fifth transistor. The first terminal of the tenth transistor is electrically connected to the signal output terminal.

[0018] In some embodiments of this application, the pull-down control signal input terminal includes a second clock signal input terminal or a second power signal input terminal;

[0019] When the pull-down control signal input terminal includes a second clock signal input terminal, the second clock signal input to the second clock signal input terminal has the same period and opposite phase to the first clock signal input to the first clock signal input terminal;

[0020] When the pull-down control signal input terminal includes a second power signal input terminal, the polarities of the signals input to the first power signal input terminal and the second power signal input terminal are opposite.

[0021] In some embodiments of this application, the pull-up module includes a first capacitor, the first electrode of the first capacitor being electrically connected to the first node, and the second electrode of the first capacitor being electrically connected to the signal output terminal.

[0022] In some embodiments of this application, the adjustment module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a second capacitor;

[0023] The first electrode of the eleventh transistor, the first electrode of the twelfth transistor, and the control electrode of the twelfth transistor are all electrically connected to the scan signal input terminal. The control electrode of the eleventh transistor, the second electrode of the twelfth transistor, and the first electrode of the thirteenth transistor are all electrically connected to the third node. The second electrode of the eleventh transistor is electrically connected to the first electrode of the second capacitor. The second electrode of the second capacitor and the second electrode of the thirteenth transistor are both electrically connected to the first node. The control electrode of the thirteenth transistor is electrically connected to the signal output terminal.

[0024] In some embodiments of this application, the input module includes a first transistor, the output module includes a third transistor, the reset module includes a second transistor and a fourth transistor, the pull-up module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the adjustment module includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; each transistor is an N-type transistor.

[0025] The first clock signal includes a first level signal and a second level signal. The voltage of the first level signal is the same as the voltage of the first DC power supply signal input at the first power supply signal input terminal, and the voltage of the first level signal is less than the voltage of the second level signal.

[0026] In some embodiments of this application, when the driving circuit includes a second power signal input terminal, the voltage of the second DC power signal input to the second power signal input terminal is a positive voltage, and the voltage of the first DC power signal input to the first power signal input terminal is a negative voltage.

[0027] In some embodiments of this application, when the fifth transistor and the eighth transistor in the pull-down module are simultaneously turned on, the current value in the eighth transistor is greater than the current value in the fifth transistor.

[0028] Secondly, embodiments of this application provide a display device including the driving circuit described above.

[0029] Thirdly, embodiments of this application provide a driving method applied to drive the driving circuit described above, the method comprising:

[0030] In the first stage, the scan signal output by the shift register of the previous stage is input to the scan signal input terminal, the first clock signal is input to the first clock signal input terminal, the second level signal is input to the pull-down control signal input terminal, and the first DC power signal is input to the first power signal input terminal.

[0031] In the second stage, the second level signal is input to the first clock signal input terminal, the first level signal is input to the pull-down control signal input terminal, and the first DC power signal is input to the first power signal input terminal.

[0032] In the third stage, a reset signal is input to the reset signal input terminal, and a first DC power signal is input to the first power signal input terminal.

[0033] In some embodiments of this application, the input of a second-level signal to the pull-down control signal input terminal includes:

[0034] A second clock signal is input to the pull-down control signal input terminal, wherein the first clock signal and the second clock signal have the same period and opposite phase;

[0035] or,

[0036] A second DC power signal is input to the pull-down control signal input terminal, wherein the voltage of the second DC power signal is a positive voltage and the voltage of the first DC power signal is a negative voltage.

[0037] In some embodiments of this application, inputting a second level signal to the pull-down control signal input terminal includes inputting a second clock signal to the pull-down control signal input terminal, wherein the first clock signal and the second clock signal have the same period but opposite phase.

[0038] Both the first clock signal and the second clock signal include a first level signal and a second level signal. The voltage of the first level signal is the same as the voltage of the first DC power supply signal, and the voltage of the first level signal is less than the voltage of the second level signal.

[0039] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 , Figure 7 and Figure 8 These are schematic diagrams of the three driving circuits provided in the embodiments of this application;

[0042] Figure 2 This application provides a schematic diagram illustrating the cascading relationship between shift registers in an embodiment.

[0043] Figure 3 for Figure 1 The timing diagram of the driving circuit shown;

[0044] Figures 4-6 for Figure 1 The driving circuit in Figure 3 A schematic diagram of the driving principle under the driving timing;

[0045] Figure 9 A flowchart of a driving method for a driving circuit provided in an embodiment of this application. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0047] In embodiments of the present invention, since the source and drain of the transistor are symmetrical, their source and drain can be interchanged. In embodiments of this disclosure, one of the source and drain of the transistor is referred to as the first electrode, and the other of the source and drain is referred to as the second electrode.

[0048] In embodiments of the present invention, the term "electrical connection" may refer to a direct electrical connection between two components, or to an electrical connection between two components via one or more other components.

[0049] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0050] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0051] Liquid crystal display panels are composed of vertical and horizontal arrayed pixel matrices. During the display process, the gate drive circuit outputs gate scan signals to scan and access each pixel line by line. The gate drive circuit is used to generate the gate scan voltage of the pixel. GOA (Gate Driver On Array) is a technology that integrates the gate drive circuit on the array substrate. Each GOA unit acts as a shift register to pass the scan signal to the next GOA unit in sequence, turning on the transistor switch line by line to complete the data signal input of the pixel unit.

[0052] To fully activate the transistors in the pixels and ensure the charging rate of the pixel electrodes, the high level (Vgh) of the scan signal needs to reach a voltage of 25V or higher. Meanwhile, the capacitor boost module of the existing GOA circuit can make the voltage of some key nodes in the internal circuit of the GOA greater than or equal to twice the high level (Vgh), reaching more than 50V. When the transistors operate at such a high voltage, their characteristics are prone to change, resulting in threshold voltage (Vth) drift. This causes the stability of the GOA unit to deteriorate during long-term display on the panel, interferes with the output of normal scan signals, and shortens its lifespan.

[0053] Embodiments of this application provide a driving circuit, including as follows: Figure 2 The multiple cascaded shift registers (GOA units) shown are configured such that, for the first-stage shift register (GOA unit 1), a first scan signal G[1] can be output based on the STV signal and the clock signal (including CLK and CLKB); the first scan signal G[1] output by the first-stage shift register serves as the input signal of the second-stage shift register, and the output signal G[2] of the second-stage shift register serves as the reset signal of the first-stage shift register. Similarly, for the second-stage and subsequent shift registers, the scan signal output by the previous-stage shift register serves as the input signal of the next-stage shift register, and the scan signal output by the next-stage shift register serves as the reset signal of the previous-stage shift register. The second-stage and subsequent shift registers (GOA unit 2, GOA unit 3...GOA unit N) output the scan signal of their respective shift registers based on the scan signal output by the previous-stage shift register and the received clock signal. The output terminal of one shift register is electrically connected to a gate line to input the corresponding scan signal into the gate line.

[0054] In some embodiments of this application, reference is made to Figure 1 As shown, the shift register includes:

[0055] Input module 1 is electrically connected to the scan signal input terminal Input of the shift register and the first node PU, respectively, and is configured to charge the first node PU when it receives the scan signal from the scan signal input terminal Input.

[0056] Output module 2 is electrically connected to the first clock signal input terminal CLK of the shift register, the first node PU, and the signal output terminal Output of the shift register, respectively. It is configured to output a scan signal G[N] from the signal output terminal Output according to the first clock signal input at the first clock signal input terminal CLK under the control of the voltage of the first node PU.

[0057] Pull-up module 3 is electrically connected to the first node PU and the signal output terminal Output respectively, and is configured to pull up the voltage of the first node PU;

[0058] The adjustment module 4 is electrically connected to the scan signal input terminal Input, the signal output terminal Output, and the first node PU, respectively, and is configured to pull down the voltage of the first node PU when the adjustment module 4 performs a bootstrap action;

[0059] Pull-down module 5 is connected to the pull-down control signal input terminal of the shift register (e.g., including...). Figure 1 The second clock signal input terminal CLKB or Figure 7The second power signal input terminal VDD), the first power signal input terminal VSS of the shift register, and the first node PU are electrically connected and configured to pull down the voltage of the first node PU;

[0060] The reset module 6 is electrically connected to the pull-down module 5, the reset signal input terminal Reset, and the signal output terminal Output of the shift register, and is configured to reset the drive circuit.

[0061] The specific circuit structures included in the above-mentioned input module 1, output module 2, pull-up module 3, adjustment module 4, pull-down module 5, and reset module 6 are not limited here. As long as they meet the corresponding functions, they are all within the scope of protection of the drive circuit provided in the embodiments of this application.

[0062] The first node PU mentioned above, as well as the second node PD and the third node PB mentioned later, are defined only for the convenience of describing the circuit structure. The first node PU, the second node PD, and the third node PB are not actual circuit units.

[0063] In an exemplary embodiment, reference is made to Figure 1 As shown, input module 1 is electrically connected to the scan signal input terminal Input of the shift register and the first node PU, respectively.

[0064] In an exemplary embodiment, reference is made to Figure 8 The input module 1 is electrically connected to the scan signal input terminal Input of the shift register, the first node PU, and the second power signal input terminal VDD.

[0065] In an exemplary embodiment, reference is made to Figure 1 As shown, the pull-down module 5 is electrically connected to the second clock signal input terminal CLKB of the shift register, the first power signal input terminal VSS of the shift register, and the first node PU, respectively.

[0066] In an exemplary embodiment, reference is made to Figure 7 As shown, the pull-down module 5 is electrically connected to the second power signal input terminal VDD of the shift register, the first power signal input terminal VSS of the shift register, and the first node PU, respectively.

[0067] In the driving circuit provided in the embodiments of this application, through the cooperation of the input module 1, output module 2, pull-up module 3, adjustment module 4, pull-down module 5 and reset module 6, on the one hand, scanning signals can be output sequentially to control the pixel in the array substrate to scan line by line; on the other hand, during the driving process of the driving circuit, after the pull-up module 3 pulls up the voltage of the first node PU and the pull-up module 3 performs a bootstrap action, the voltage of the first node PU continues to rise. The adjustment module 4 can discharge the scanning signal input terminal Input to pull down the voltage of the first node PU, thereby avoiding the voltage of the first node PU from being too high, and thus avoiding the problem of reduced lifespan or unstable performance of devices electrically connected to the first node PU due to excessive voltage, thereby improving the stability of the driving circuit.

[0068] In some embodiments of this application, reference is made to Figure 1 As shown, the input module 1 includes a first transistor M1. The control electrode and the first electrode of the first transistor M1 are both electrically connected to the scan signal input terminal Input, and the second electrode of the first transistor M1 is electrically connected to the first node PU.

[0069] In some embodiments of this application, reference is made to Figure 8 As shown, the input module 1 includes a first transistor M1. The control electrode of the first transistor M1 is electrically connected to the scan signal input terminal Input. The first electrode of the first transistor M1 is electrically connected to the second power supply signal input terminal VDD of the shift register. The second electrode of the first transistor M1 is electrically connected to the first node PU.

[0070] In some embodiments of this application, reference is made to Figure 1 As shown, the output module 2 includes a third transistor M3. The control electrode of the third transistor M3 is electrically connected to the first node PU, the first electrode of the third transistor M3 is electrically connected to the first clock signal input terminal CLK, and the second electrode of the third transistor M3 is electrically connected to the signal output terminal Output.

[0071] In some embodiments of this application, the reset module 6 includes a second transistor M2 and a fourth transistor M4, wherein the control electrode of the second transistor M2 and the control electrode of the fourth transistor M4 are electrically connected to the reset signal input terminal Reset, respectively.

[0072] The first terminal of the second transistor M2 is electrically connected to the first node PU, and the second terminal of the second transistor M2 is electrically connected to the first power signal input terminal VSS; the first terminal of the fourth transistor M4 is electrically connected to the signal output terminal Output, and the second terminal of the fourth transistor M4 is electrically connected to the first power signal input terminal VSS.

[0073] In some embodiments of this application, reference is made to Figure 1 or Figure 7As shown, the drop-down module 5 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10;

[0074] The first terminal of the fifth transistor M5, the first terminal of the eighth transistor M8, and the control terminal of the eighth transistor M8 are all connected to the pull-down control signal input terminal (e.g., including...). Figure 1 The second clock signal input terminal CLKB or Figure 7 The second power signal input terminal (VDD) is electrically connected. The control electrode of the fifth transistor M5 is electrically connected to the second electrode of the eighth transistor M8. The second electrode of the fifth transistor M5, the first electrode of the sixth transistor M6, the control electrode of the ninth transistor M9, and the control electrode of the tenth transistor M10 are all electrically connected to the second node PD. The second electrode of the sixth transistor M6, the second electrode of the seventh transistor M7, the second electrode of the ninth transistor M9, and the second electrode of the tenth transistor M10 are all electrically connected to the first power signal input terminal (VSS). The control electrode of the sixth transistor M6, the control electrode of the seventh transistor M7, and the first electrode of the ninth transistor M9 are all electrically connected to the first node PU. The first electrode of the seventh transistor M7 is electrically connected to the control electrode of the fifth transistor M5. The first electrode of the tenth transistor M10 is electrically connected to the signal output terminal (Output).

[0075] In some embodiments of this application, the pull-down control signal input terminal includes Figure 1 The second clock signal input terminal CLKB or Figure 7 The second power signal input terminal VDD;

[0076] When the pull-down control signal input includes the second clock signal input CLKB, refer to Figure 3 As shown, the second clock signal CLKB input to the second clock signal input terminal has the same period and opposite phase to the first clock signal CLK input to the first clock signal input terminal;

[0077] When the pull-down control signal input terminal includes a second power signal input terminal VDD, the polarities of the signals input to the first power signal input terminal VSS and the second power signal input terminal VDD are opposite.

[0078] For example, the first power signal input terminal VSS receives a DC power signal with a negative voltage, and the second power signal input terminal VDD receives a DC power signal with a positive voltage.

[0079] In some embodiments of this application, reference is made to Figure 1 As shown, the pull-up module 3 includes a first capacitor C1, the first electrode of the first capacitor C1 is electrically connected to the first node PU, and the second electrode of the first capacitor C1 is electrically connected to the signal output terminal Output.

[0080] In some embodiments of this application, reference is made to Figure 1 As shown, the adjustment module 4 includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a second capacitor C2;

[0081] The first electrode of the eleventh transistor M11, the first electrode of the twelfth transistor M12, and the control electrode of the twelfth transistor M12 are all electrically connected to the scan signal input terminal Input. The control electrode of the eleventh transistor M11, the second electrode of the twelfth transistor M12, and the first electrode of the thirteenth transistor M13 are all electrically connected to the third node PB. The second electrode of the eleventh transistor M11 is electrically connected to the first electrode of the second capacitor C2. The second electrode of the second capacitor C2 and the second electrode of the thirteenth transistor M13 are both electrically connected to the first node PU. The control electrode of the thirteenth transistor M13 is electrically connected to the signal output terminal Output.

[0082] In an exemplary embodiment, the transistor described above may be a thin-film transistor or a metal-oxide-semiconductor field-effect transistor, and there is no limitation herein.

[0083] In the exemplary embodiments, in order to ensure uniformity in manufacturing processes and to simplify the driving method of subsequent circuits, the driving circuit provided in the embodiments of this application is described with the example of all the above-mentioned transistors being N-type transistors.

[0084] Of course, all of the above transistors can also be P-type transistors. In the case where the transistors are P-type transistors, the design principle is similar to that of this invention and they also fall within the scope of protection of this invention.

[0085] It should be noted that N-type transistors conduct when the voltage level is high and are cut off when the voltage level is low; P-type transistors conduct when the voltage level is low and are cut off when the voltage level is high.

[0086] In some embodiments of this application, the input module 1 includes a first transistor M1, the output module 2 includes a third transistor M3, the reset module 6 includes a second transistor M2 and a fourth transistor M4, the pull-up module 5 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10; the adjustment module 4 includes an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13; when all transistors are N-type transistors, the first clock signal CLK includes a first level signal and a second level signal, the voltage of the first level signal is the same as the voltage of the first DC power signal VSS input at the first power signal input terminal VSS, and the voltage of the first level signal is less than the voltage of the second level signal.

[0087] For example, the first level is a low level (e.g., voltage Vgl) and the second level is a high level (e.g., voltage Vgh).

[0088] For example, the low-level signal in the first clock signal CLK is the same as the voltage of the first DC power supply signal VSS.

[0089] In some embodiments of this application, reference is made to Figure 7 or Figure 8 As shown, when the driving circuit includes a second power signal input terminal VDD, the voltage of the second DC power signal VDD input at the second power signal input terminal VDD is a positive voltage, and the voltage of the first DC power signal VSS input at the first power signal input terminal VSS is a negative voltage.

[0090] For example, refer to Figure 7 The pull-down control signal input terminal includes the second power signal input terminal VDD.

[0091] For example, refer to Figure 8 As shown, the first terminal of the first transistor M1 in the input module 1 is electrically connected to the second power signal input terminal VDD.

[0092] In some embodiments of this application, the pull-down control signal input terminal includes a second power signal input terminal VDD or a second clock signal input terminal CLKB;

[0093] refer to Figure 8 As shown, when the pull-down control signal input terminal includes a second clock signal input terminal CLKB, the second clock signal CLKB input to the second clock signal input terminal CLKB has the same period and opposite phase to the first clock signal CLK input to the first clock signal input terminal CLK.

[0094] In some embodiments of this application, reference is made to Figure 4 As shown, when both the fifth transistor M5 and the eighth transistor M8 in the pull-down module 5 are turned on, the current value in the eighth transistor M8 is greater than the current value in the fifth transistor M5. At this time, because the seventh transistor M7 is turned on, the low-level signal input to the first power signal input terminal VSS controls the fifth transistor M5 to turn off through the seventh transistor M7, thereby preventing the voltage of the second node PD from being pulled high.

[0095] It should be noted that, in Figures 4-7In the diagram, "H" indicates that the input signal is a high-level signal, and "L" indicates that the input signal is a low-level signal. In addition, in the accompanying drawings provided in the embodiments of this application, G[N-1] indicates that the input is the scan signal G[N-1] output by the previous stage shift register. It can be understood that the ports that input the scan signal G[N-1] output by the previous stage shift register are all scan signal input terminals. G[N] indicates the output terminal of the current stage shift register, and the output scan signal is...

[0096] The following example uses transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, and M13, all of which are N-type transistors. Figure 1 Taking the structure of the driving circuit shown in the figure as an example, and combining it with the signal timing of each port input in this case, the working principle of the driving circuit provided in this embodiment will be described in detail. It should be noted that, Figures 4 to 6 In the diagram, transistors are marked with an "×" for cutoff and "√" for conduction.

[0097] Figure 3 The timing diagram of the signals at each port input (or input) is shown during one duty cycle.

[0098] In the first stage, such as Figure 3 The input stage T1 shown is referenced. Figure 4As shown, the scan signal input terminal Input receives a high-level signal H, the first clock signal input terminal CLK receives a low-level signal L, the second clock signal input terminal CLKB receives a high-level signal H, the reset signal input terminal Reset receives a low-level signal L, and the first power signal input terminal VSS receives a low-level signal L. At this time, the first transistor M1 is turned on, and the high-level signal H input to the scan signal input terminal Input charges the first node PU through the first transistor M1. The first node PU is at a high level with a voltage of Vgh. The third transistor M3 is turned on, and the first clock signal input terminal CLK transmits a low-level signal L to the signal output terminal Output through the third transistor M3. The signal output terminal Output outputs a low-level signal Low. The eleventh transistor M11 and the twelfth transistor M12 are turned on. When transistor M13 is turned off, the third node PB is at a high level with a voltage of Vgh. Transistors M5, M6, M7, and M8 are turned on, while transistors M2, M4, M9, and M10 are turned off. By designing the ratio of the values ​​of transistors M8 and M9, and then designing the ratio of the values ​​of transistors M8 and M5, the actual current flowing through transistor M8 is greater than the current flowing through transistor M5. Thus, the low-level signal L input to the first power supply signal input terminal VSS can control the fifth transistor M5 through transistor M7, preventing the voltage of the second node PD from being pulled high by the high-level signal H input to the second clock signal input terminal CLKB, and keeping it at a low level.

[0099] In the second stage, such as Figure 3 The output stage T2 shown in the figure, refer to Figure 5As shown, the scan signal input terminal Input is low-level signal L, the first clock signal input terminal CLK is high-level signal H, the second clock signal input terminal CLKB is low-level signal L, the reset signal input terminal Reset is low-level signal L, and the first power signal input terminal VSS is low-level signal L. At this time, the first node PU maintains the voltage Vgh of the previous stage, the first transistor M1 is off, and the second transistor M2, the ninth transistor M9, the fifth transistor M5, the eighth transistor M8, the fourth transistor M4, and the tenth transistor M10 are off. The third transistor M3 and the sixth transistor M10 are off. When transistors M6 and M7 are turned on, the first clock signal input terminal CLK transmits a high-level signal H to the signal output terminal Output through the third transistor M3. The voltage at the signal output terminal Output changes from a low level in the previous stage to a high level at this time, generating an induced voltage difference at the first node PU of the first storage capacitor C1. Due to the bootstrap effect of the first storage capacitor C1, the voltage at the first node PU continues to rise, and the voltage value tends to 2Vgh from Vgh. Under the control of the high-level signal at the signal output terminal Output (G[N] is at a high level at this time), the voltage at the first node PU continues to rise. When the thirteenth transistor M13 is turned on, under the control of the low-level signal input at the scan signal input terminal Input (G[N-1] is low at this time), the twelfth transistor M12 is quickly turned off. The third node PB discharges to the first power signal input terminal VSS through the thirteenth transistor M13, and the voltage of the third node PB is pulled down from high level to low level. The current passing through the eleventh transistor M11 gradually decreases until it is turned off. When there is current passing through the eleventh transistor M11, the low-level signal input at the scan signal input terminal Input (G[N-1] is low at this time) can pass through the thirteenth transistor M12. A transistor M11 transmits power to one electrode of the second capacitor C2, causing the second capacitor C2 to generate an induced voltage difference at the first node PU. Due to the bootstrap effect of the second capacitor C2, the voltage of the first node PU is pulled down. Finally, under the combined action of the first capacitor C1 and the second capacitor C2, the voltage value of the first node PU rises to about 1.5Vgh, avoiding the threshold voltage (Vth) drift problem caused by excessive voltage in the transistor whose gate is electrically connected to the first node PU. This improves the performance stability of the transistor in the driving circuit and extends the lifespan of the transistor.

[0100] In the third stage, such as Figure 3 The reset phase T3 shown in the figure refers to... Figure 6As shown, the scan signal input terminal Input is low-level signal L, the first clock signal input terminal CLK is low-level signal L, the second clock signal input terminal CLKB is high-level signal H, the reset signal input terminal Reset is high-level signal H, and the first power signal input terminal VSS is low-level signal L. At this time, the second transistor M2 and the fourth transistor M4 are turned on, the fifth transistor M5 and the eighth transistor M8 are turned on, and the ninth transistor M9 and the tenth transistor M10 are turned on. The voltage at the first node PU and the voltage at the signal output terminal Output are both pulled low to reset.

[0101] It should be noted that, for the sake of simplicity in driving timing, the driving timing provided in this embodiment is only based on... Figure 1 The circuit diagram shown is one example of a case where... Figure 7 and Figure 8 The timing of the circuit diagram shown can be adjusted accordingly, and no restrictions are imposed here.

[0102] It should be further noted that the transistors provided in this embodiment are not limited to N-type transistors; in practical applications, each transistor can also be a P-type transistor. When all transistors are P-type transistors, their specific timing is... Figure 3 The phases of the timing sequences are opposite.

[0103] An embodiment of this application provides a display device including the driving circuit described above.

[0104] The aforementioned display devices can be LCDs (Liquid Crystal Displays), as well as any product or component with display functionality, such as televisions, digital cameras, mobile phones, and tablet computers, that includes these display devices. These display devices are characterized by good screen brightness uniformity, excellent display effect, and high product quality.

[0105] Embodiments of this application provide a driving method for driving a driving circuit as described above, the method comprising:

[0106] S901, First stage T1 (i.e., input stage): Input the scan signal output from the previous stage shift register to the scan signal input terminal Input, input the first clock signal to the first clock signal input terminal CLK, and pull down the control signal input terminal (e.g., including...). Figure 1 The second clock signal input terminal CLKB or Figure 7 The second power signal input terminal VDD inputs a second level signal, and the first power signal input terminal VSS inputs a first DC power signal.

[0107] In an exemplary embodiment, the step of inputting a second level signal to the pull-down control signal input terminal includes: S9011, inputting a second clock signal CLKB signal to the pull-down control signal input terminal, wherein the first clock signal and the second clock signal have the same period and opposite phase;

[0108] Figure 1 The specific driving method of the driving circuit shown in the first stage T1 is as follows:

[0109] The scan signal input terminal Input is given a high-level signal H, the first clock signal input terminal CLK is given a low-level signal L, the second clock signal input terminal CLKB is given a high-level signal H, the reset signal input terminal Reset is given a low-level signal L, and the first power signal input terminal VSS is given a low-level signal L. At this time, the first transistor M1 is turned on, and the high-level signal H input to the scan signal input terminal Input charges the first node PU through the first transistor M1. The first node PU is at a high level with a voltage value of Vgh. The third transistor M3 is turned on, and the first clock signal input terminal CLK transmits the low-level signal L to the signal output terminal Output through the third transistor M3. The signal output terminal Output outputs a low-level signal Low. The eleventh transistor M11 and the twelfth transistor M12 are turned on, and the tenth... When transistor M13 is off, the third node PB is high and its voltage is Vgh. Transistors M5, M6, M7, and M8 are on, while transistors M2, M4, M9, and M10 are off. By designing the ratio of the values ​​of transistors M8 and M9, and then designing the ratio of the values ​​of transistors M8 and M5, the actual current through transistor M8 is greater than the current through transistor M5. Thus, the low-level signal L input to the first power supply signal input terminal VSS can control transistor M5 through transistor M7, preventing the voltage of the second node PD from being pulled high by the high-level signal H input to the second clock signal input terminal CLKB, and keeping it in a low-level state.

[0110] S902, Second stage T2 (i.e., output stage): Input a second level signal to the first clock signal input terminal CLK, input a first level signal to the pull-down control signal input terminal, and input a first DC power signal to the first power signal input terminal VSS;

[0111] In an exemplary embodiment, the step of inputting a second level signal to the pull-down control signal input terminal includes: S9011, inputting a second clock signal CLKB signal to the pull-down control signal input terminal, wherein the first clock signal and the second clock signal have the same period and opposite phase;

[0112] Figure 1 The specific driving method of the driving circuit shown in the second stage T2 is as follows:

[0113] The scan signal input terminal Input is low-level signal L, the first clock signal input terminal CLK is high-level signal H, the second clock signal input terminal CLKB is low-level signal L, the reset signal input terminal Reset is low-level signal L, and the first power signal input terminal VSS is low-level signal L. At this time, the first node PU maintains the voltage Vgh of the previous stage, the first transistor M1 is off, and the second transistor M2, the ninth transistor M9, the fifth transistor M5, the eighth transistor M8, the fourth transistor M4, and the tenth transistor M10 are off. The third transistor M3 and the sixth transistor M10 are off. When transistors 6 and 7 are turned on, the first clock signal input terminal CLK transmits a high-level signal H to the signal output terminal Output through the third transistor M3. The voltage at the signal output terminal Output jumps from a low level in the previous stage to a high level at this time, generating an induced voltage difference at the first node PU of the first storage capacitor C1. Due to the bootstrap effect of the first storage capacitor C1, the voltage at the first node PU continues to rise, and the voltage tends from Vgh to 2Vgh. Under the control of the high-level signal G[N] at the signal output terminal Output, the thirteenth transistor M13 is turned on. Under the control of the low-level signal input at the scan signal input terminal Input (G[N-1] is low at this time), the twelfth transistor M12 is quickly turned off, and the third node PB discharges to the first power signal input terminal VSS through the thirteenth transistor M13. The voltage of the third node PB is pulled low. At this time, the eleventh transistor M11 is pulled from high level to low level, and the current passing through the eleventh transistor M11 gradually decreases until it is turned off. When there is current passing through the eleventh transistor M11, the low-level signal input at the scan signal input terminal Input (G[N-1] is low at this time) can pass through the first power signal input terminal VSS. The eleventh transistor M11 transmits to one electrode of the second capacitor C2, causing the second capacitor C2 to generate an induced voltage difference at the first node PU. Due to the bootstrap effect of the second capacitor C2, the voltage of the first node PU is pulled down. Finally, under the combined action of the first capacitor C1 and the second capacitor C2, the voltage of the first node PU rises to about 1.5Vgh, avoiding the threshold voltage (Vth) drift problem caused by excessive voltage in the transistor whose gate is electrically connected to the first node PU. This improves the performance stability of the transistor in the driving circuit and extends the lifespan of the transistor.

[0114] S903, the third stage T3 (i.e., the reset stage) inputs a reset signal to the reset signal input terminal Reset and inputs a first DC power signal to the first power signal input terminal VSS.

[0115] Figure 1 The specific driving method of the driving circuit shown in the third stage T3 is as follows:

[0116] The scan signal input terminal Input is low-level signal L, the first clock signal input terminal CLK is low-level signal L, the second clock signal input terminal CLKB is high-level signal H, the reset signal input terminal Reset is high-level signal H, and the first power signal input terminal VSS is low-level signal L. At this time, the second transistor M2 and the fourth transistor M4 are turned on, the fifth transistor M5 and the eighth transistor M8 are turned on, the ninth transistor M9 and the tenth transistor M10 are turned on, and the voltage at the first node PU and the voltage at the signal output terminal Output are both pulled low to reset.

[0117] The embodiments of this application provide a driving method for a driving circuit. This method enables, on the one hand, the sequential output of scanning signals to control the row-by-row scanning of pixels in an array substrate; on the other hand, during the driving process, after the pull-up module 3 raises the voltage of the first node PU and the pull-up module 3 performs a bootstrap action, the voltage of the first node PU continues to rise. The adjustment module 4 can then discharge the scanning signal input terminal Input to lower the voltage of the first node PU, thereby preventing the voltage of the first node PU from becoming too high. This avoids the problem of reduced lifespan or unstable performance of devices electrically connected to the first node PU due to excessive voltage, thus improving the stability of the driving circuit. This driving method has a simple driving timing and is easy to implement.

[0118] In some embodiments of this application, the step of inputting a second-level signal at the pull-down control signal input terminal includes:

[0119] S9011, the pull-down control signal input terminal inputs the second clock signal CLKB, wherein the first clock signal and the second clock signal have the same period and opposite phase;

[0120] or,

[0121] S9012. Input the second DC power supply signal VDD signal to the pull-down control signal input terminal, wherein the voltage of the second DC power supply signal is a positive voltage and the voltage of the first DC power supply signal is a negative voltage.

[0122] In some embodiments of this application, inputting a second-level signal to the pull-down control signal input terminal includes inputting a second clock signal CLKB signal to the pull-down control signal input terminal, wherein the first clock signal CLK signal and the second clock signal CLKB signal have the same period but opposite phase.

[0123] The first clock signal CLK and the second clock signal CLKB both include a first level signal (low level signal) and a second level signal (high level signal). The voltage of the first level signal is the same as the voltage of the first DC power supply signal VSS, and the voltage of the first level signal is less than the voltage of the second level signal.

[0124] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A driving circuit, wherein, This includes multiple cascaded shift registers, wherein the shift registers include: The input module is electrically connected to the scan signal input terminal of the shift register and the first node, respectively, and is configured to charge the first node when a scan signal is received from the scan signal input terminal; The output module is electrically connected to the first clock signal input terminal of the shift register, the first node, and the signal output terminal of the shift register, respectively, and is configured to output a scan signal from the signal output terminal according to the first clock signal input terminal under the control of the voltage of the first node. The pull-up module is electrically connected to the first node and the signal output terminal respectively, and is configured to pull up the voltage of the first node; The adjustment module is electrically connected to the scan signal input terminal, the signal output terminal and the first node respectively, and is configured to pull down the voltage of the first node when the adjustment module performs a bootstrap action; The pull-down module is electrically connected to the pull-down control signal input terminal of the shift register, the first power signal input terminal of the shift register, and the first node, and is configured to pull down the voltage of the first node. The reset module is electrically connected to the pull-down module, the reset signal input terminal of the shift register, and the signal output terminal, and is configured to reset the drive circuit. The adjustment module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a second capacitor. The first electrode of the eleventh transistor, the first electrode of the twelfth transistor, and the control electrode of the twelfth transistor are all electrically connected to the scan signal input terminal. The control electrode of the eleventh transistor, the second electrode of the twelfth transistor, and the first electrode of the thirteenth transistor are all electrically connected to the third node. The second electrode of the eleventh transistor is electrically connected to the first electrode of the second capacitor. The second electrode of the second capacitor and the second electrode of the thirteenth transistor are both electrically connected to the first node. The control electrode of the thirteenth transistor is electrically connected to the signal output terminal.

2. The driving circuit according to claim 1, wherein, The input module includes a first transistor, the control electrode and the first electrode of the first transistor are both electrically connected to the scan signal input terminal, and the second electrode of the first transistor is electrically connected to the first node.

3. The driving circuit according to claim 1, wherein, The input module includes a first transistor, the control electrode of the first transistor is electrically connected to the scan signal input terminal, the first electrode of the first transistor is electrically connected to the second power supply signal input terminal of the shift register, and the second electrode of the first transistor is electrically connected to the first node.

4. The driving circuit according to claim 1, wherein, The output module includes a third transistor, the control electrode of which is electrically connected to the first node, the first electrode of which is electrically connected to the first clock signal input terminal, and the second electrode of which is electrically connected to the signal output terminal.

5. The driving circuit according to claim 1, wherein, The reset module includes a second transistor and a fourth transistor, and the control electrode of the second transistor and the control electrode of the fourth transistor are respectively electrically connected to the reset signal input terminal. The first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first power signal input terminal; the first terminal of the fourth transistor is electrically connected to the signal output terminal, and the second terminal of the fourth transistor is electrically connected to the first power signal input terminal.

6. The driving circuit according to claim 1, wherein, The pull-down module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The first terminal of the fifth transistor, the first terminal of the eighth transistor, and the control terminal of the eighth transistor are all electrically connected to the pull-down control signal input terminal. The control terminal of the fifth transistor is electrically connected to the second terminal of the eighth transistor. The second terminal of the fifth transistor, the first terminal of the sixth transistor, the control terminal of the ninth transistor, and the control terminal of the tenth transistor are all electrically connected to the second node. The second terminals of the sixth transistor, the seventh transistor, the ninth transistor, and the tenth transistor are all electrically connected to the first power signal input terminal. The control terminals of the sixth transistor, the seventh transistor, and the ninth transistor are all electrically connected to the first node. The first terminal of the seventh transistor is electrically connected to the control terminal of the fifth transistor. The first terminal of the tenth transistor is electrically connected to the signal output terminal.

7. The driving circuit according to claim 6, wherein, The pull-down control signal input terminal includes a second clock signal input terminal or a second power signal input terminal; When the pull-down control signal input terminal includes a second clock signal input terminal, the second clock signal input to the second clock signal input terminal has the same period and opposite phase to the first clock signal input to the first clock signal input terminal; When the pull-down control signal input terminal includes a second power signal input terminal, the polarities of the signals input to the first power signal input terminal and the second power signal input terminal are opposite.

8. The driving circuit according to claim 1, wherein, The pull-up module includes a first capacitor, the first electrode of the first capacitor is electrically connected to the first node, and the second electrode of the first capacitor is electrically connected to the signal output terminal.

9. The driving circuit according to any one of claims 1-8, wherein, The input module includes a first transistor, the output module includes a third transistor, the reset module includes a second transistor and a fourth transistor, the pull-up module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the adjustment module includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; all transistors are N-type transistors. The first clock signal includes a first level signal and a second level signal. The voltage of the first level signal is the same as the voltage of the first DC power supply signal input at the first power supply signal input terminal, and the voltage of the first level signal is less than the voltage of the second level signal.

10. The driving circuit according to claim 9, wherein, When the driving circuit includes a second power signal input terminal, the voltage of the second DC power signal input to the second power signal input terminal is a positive voltage, and the voltage of the first DC power signal input to the first power signal input terminal is a negative voltage.

11. The driving circuit according to claim 6, wherein, When the fifth transistor and the eighth transistor in the pull-down module are both turned on, the current value in the eighth transistor is greater than the current value in the fifth transistor.

12. A display device, wherein, Includes the drive circuit as described in any one of claims 1-11.

13. A driving method, wherein, The method, applied to a drive circuit as described in any one of claims 1-11, comprises: In the first stage, the scan signal output by the shift register of the previous stage is input to the scan signal input terminal, the first clock signal is input to the first clock signal input terminal, the second level signal is input to the pull-down control signal input terminal, and the first DC power signal is input to the first power signal input terminal. In the second stage, the second level signal is input to the first clock signal input terminal, the first level signal is input to the pull-down control signal input terminal, and the first DC power signal is input to the first power signal input terminal. In the third stage, a reset signal is input to the reset signal input terminal, and a first DC power signal is input to the first power signal input terminal.

14. The driving method according to claim 13, wherein, The input of the second-level signal at the pull-down control signal input terminal includes: A second clock signal is input to the pull-down control signal input terminal, wherein the first clock signal and the second clock signal have the same period and opposite phase; Alternatively, a second DC power signal can be input to the pull-down control signal input terminal, wherein the voltage of the second DC power signal is a positive voltage and the voltage of the first DC power signal is a negative voltage.

15. The driving method according to claim 14, wherein, The input of a second-level signal to the pull-down control signal input terminal includes inputting a second clock signal to the pull-down control signal input terminal, wherein the first clock signal and the second clock signal have the same period but opposite phase. Both the first clock signal and the second clock signal include a first level signal and a second level signal. The voltage of the first level signal is the same as the voltage of the first DC power supply signal, and the voltage of the first level signal is less than the voltage of the second level signal.

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