Step-down converter with quasi-fixed-frequency constant on-time architecture and on-time timing circuit

Abstract

The embodiment of the present disclosure provides a quasi-fixed frequency constant on-time architecture buck converter and an on-time timing circuit. The on-time timing circuit comprises a current generating module, a flip delay cancellation module, a capacitor and a comparator. The current generating module is configured to generate a charging current proportional to the voltage of a switching node after the upper power tube is turned on. The flip delay cancellation module is configured to generate a first delay for canceling the flip delay of the comparator according to a variable resistance unit and the capacitor. The resistance value of the variable resistance unit is controlled by an input voltage. The capacitor is configured to be charged by the charging current after the upper power tube is turned on. The comparator is configured to compare the size of the slope voltage corresponding to the slope voltage node and the first voltage, and generate an off signal. The first voltage is a reference voltage in proportional relationship with the output voltage. The problem of large variation of working frequency in the quasi-fixed frequency constant on-time architecture buck converter is solved.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more specifically, to a buck converter and a turn-on timing circuit with a quasi-fixed frequency constant on-time architecture. Background Technology

[0002] In a buck converter with a quasi-fixed frequency and constant on-time architecture, the on-time t is typically... on It is directly proportional to the output voltage Vo and inversely proportional to the input voltage Vi. For example... Figure 1 The diagram shows a circuit structure diagram of a commonly used turn-on timing circuit in a buck converter with a quasi-fixed frequency and constant on-time architecture. The negative input terminal of the comparator is coupled to the output voltage, and the positive input terminal is coupled to the voltage of capacitor Con. The charging current Ion is the ratio of the input voltage to Ron. According to the voltage-current relationship of the capacitor, we can obtain: (Vi / Ron)×Ton=Con×Vo. Theoretically, the on-time of the power transistor is obtained as Ton=(Con×Vo×Ron) / Vi. From the expression of Ton, we can see that it is directly proportional to Vo and inversely proportional to Vi. However, the actual calculation of Ton requires adding the comparator's switching delay Tcomp. The comparator's switching delay varies with the voltage Vi, and Tcomp affects Ton's linearity in following changes in Vi and Vo, especially when Vi and Vo vary over a wide range. If Vi is high and Vo is low (small duty cycle), Ton may be tens of ns, and the comparator's switching delay will also be tens of ns. If Vi is low and Vo and Vi are close (large duty cycle), the comparator's switching delay can reach hundreds of ns. The larger the comparator's switching delay is relative to the actual on-time, the more severe the Ton nonlinearity becomes. This leads to a significant variation in the operating frequency of the entire buck converter system with a quasi-fixed-frequency, constant-on-time architecture across all voltage levels, which is detrimental to peripheral applications. Therefore, according to... Figure 1 Using a turn-on timing circuit for turn-on timing will cause the operating frequency of the entire buck converter system with a quasi-fixed frequency and constant turn-on time architecture to vary significantly across the entire voltage range.

[0003] Furthermore, based on the volt-second balance principle of buck converters, the following equation is obtained in practical applications:

[0004] (V i -I load ·R hs -V o )·T on =V o ·T off ,

[0005] Among them I load For the output load current, R hs T is the on-resistance of the power transistor.off Let be the turn-off time of the power transistor. Transforming the above equation yields:

[0006] (V i -I load ·R hs )·T on =V o ·T off +V o ·T on =V o ·T S ,

[0007]

[0008] As can be seen, if I load When the change is large, the conduction loss I of the power transistor load ×R hs The change in cannot be ignored; that is, at this point, Ton and the input voltage Vi are not inversely proportional, but rather related to (Vi-I). load ×R hs It is inversely proportional, but due to Figure 1 The Ton obtained by the on-time timing circuit is still inversely proportional to Vi, without considering I. load The impact on Ton, therefore the actual Ton in I load Significant changes can lead to substantial variations in operating frequency.

[0009] In summary, the problem of large operating frequency variations in buck converters with quasi-fixed frequency and constant on-time architecture urgently needs to be addressed. Summary of the Invention

[0010] The embodiments described herein provide a buck converter and a turn-on timing circuit with a quasi-fixed frequency constant on-time architecture to solve the problem of large operating frequency variations in buck converters with a quasi-fixed frequency constant on-time architecture.

[0011] According to a first aspect of this disclosure, a turn-on timing circuit is provided for a buck converter with a quasi-fixed-frequency constant-on-time architecture, capable of outputting a turn-off signal to turn off the upper power transistor of the buck converter. The turn-on timing circuit includes: a current generation module, a flip-flop delay cancellation module, a capacitor, and a comparator. The input terminal of the current generation module is coupled to a switching node of the buck converter, and the output terminal of the current generation module is coupled to a ramp voltage node. The switching node is the node where the upper power transistor and the inductor are coupled in the buck converter. The current generation module is configured to generate a charging current proportional to the voltage of the switching node after the upper power transistor is turned on. The input terminal of the flip-flop delay cancellation module is coupled to the ramp voltage node, and the flip-flop delay... The output of the cancellation module is coupled to one end of the capacitor. The flip-delay cancellation module is configured to generate a first delay to cancel the flip-delay of the comparator based on the variable resistor unit and the capacitor. The resistance value of the variable resistor unit is controlled by the input voltage of the buck converter. The other end of the capacitor is coupled to ground. The capacitor is configured to be charged by the charging current after the upper power transistor is turned on. The positive input of the comparator is coupled to the ramp voltage node, and the negative input of the comparator is coupled to a first voltage. The comparator is configured to compare the magnitude of the ramp voltage corresponding to the ramp voltage node with the first voltage and generate the turn-off signal. The first voltage is a reference voltage that is proportional to the output voltage of the buck converter.

[0012] Optionally, the current generating module includes: a first current generating module and a second current generating module, wherein the first current generating module is configured to generate a first current based on the voltage of the switching node and the voltage of the ramp voltage node; the second current generating module is configured to generate a second current based on the voltage of the ramp voltage node, and the sum of the first current and the second current is the charging current.

[0013] Optionally, the flip-delay cancellation module includes: a decoder unit and a variable resistor unit, wherein the decoder unit is configured to generate a switch control signal according to the input voltage; and the variable resistor unit is configured to adjust the resistance value of the variable resistor unit according to the switch control signal.

[0014] Optionally, the first current generating module includes: a first resistor and a first switch, wherein one end of the first resistor is coupled to the switching node, the other end of the first resistor is coupled to one end of the first switch, and the other end of the first resistor generates the first current; the other end of the first switch is coupled to the ramp voltage node, and the first switch closes after the upper power transistor is turned on and opens after the upper power transistor is turned off.

[0015] Optionally, the second current generating module includes: a first to a sixth transistor, a first current source, and a second resistor, wherein the first transistor and the second transistor form a first current mirror, the source of the first transistor and the source of the second transistor are both coupled to a power supply voltage, the gate of the first transistor and the gate of the second transistor are both coupled to the drain of the first transistor, the drain of the second transistor is coupled to the ramp voltage node, and the drain of the second transistor generates the second current; the third transistor and the fourth transistor form a second current mirror, the gate of the third transistor and the gate of the fourth transistor are both coupled to the third current mirror. The drain of the third transistor is coupled to one end of the first current source, and the drain of the fourth transistor is coupled to the drain of the first transistor; the source of the fifth transistor is coupled to the source of the third transistor, the gate of the fifth transistor is coupled to the ramp voltage node, and the drain of the fifth transistor is coupled to ground; the source of the sixth transistor is coupled to the source of the fourth transistor, the gate of the sixth transistor is coupled to the drain of the sixth transistor, and the drain of the sixth transistor is coupled to one end of the second resistor; the other end of the second resistor is coupled to ground, and the other end of the first current source is coupled to the power supply voltage.

[0016] Optionally, the variable resistor unit includes N resistors and N switches, wherein the N resistors are connected in series and a switch is connected in parallel across each resistor.

[0017] Optionally, the decoder unit includes an N-bit decoder, and the switch control signal includes N switch signals. The input terminal of the N-bit decoder receives the input voltage, and the output terminal of the N-bit decoder outputs the N switch signals. The N switch signals control the opening and closing of the N switches, and each switch corresponds to one switch signal.

[0018] Optionally, the resistance value of the variable resistor unit is inversely proportional to the input voltage.

[0019] Optionally, the resistance value of the first resistor is equal to the resistance value of the second resistor.

[0020] Optionally, the conduction timing circuit further includes a second switch, wherein the second switch is coupled between the ramp voltage node and the ground terminal, and the second switch is opened after the first switch is closed, and closed after the first switch is opened.

[0021] Optionally, the current mirror ratio of both the first current mirror and the second current mirror is 1.

[0022] According to a second aspect of this disclosure, a buck converter with a quasi-fixed frequency constant on-time architecture is provided, including the on-time timing circuit described in any one of the first aspects.

[0023] In the conduction timing circuit of the embodiments of this disclosure, the first delay generated by the flip delay cancellation module is used to cancel the flip delay of the comparator, thereby eliminating the influence of the comparator's flip delay on the conduction time Ton; and since the voltage of the switching node is the input voltage minus the conduction loss of the upper power transistor (Vi-I) when the upper power transistor is turned on, the voltage of the switching node is the input voltage minus the conduction loss of the upper power transistor (Vi-I). load ×R hs Therefore, by generating a charging current proportional to the voltage of the switching node through the current generation module to charge the capacitor, the conduction time can be made inversely proportional to the voltage of the switching node, that is, the conduction time can be made proportional to (Vi-I). load ×R hs The on-time timing circuit is inversely proportional to the load current, unlike existing on-time timing circuits which consider the impact of load current on Ton. In summary, compared to existing on-time timing circuits, the on-time timing circuit of this disclosure can ensure minimal changes in system operating frequency across a wide range of input voltages, output voltages, and different loads, better meeting the needs of peripheral applications. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0025] Figure 1 A schematic block diagram of an existing on-time timing circuit is shown;

[0026] Figure 2 A schematic block diagram of a turn-on timing circuit according to an embodiment of the present disclosure is shown;

[0027] Figure 3 A schematic circuit diagram of another conduction timing circuit according to an embodiment of the present disclosure is shown;

[0028] Figure 4 An exemplary circuit diagram of a current generation module in a turn-on timing circuit according to an embodiment of the present disclosure is shown;

[0029] Figure 5 An exemplary circuit diagram of a flip delay cancellation module in a conduction timing circuit according to an embodiment of the present disclosure is shown;

[0030] Figure 6 A schematic circuit diagram of yet another conduction timing circuit according to an embodiment of the present disclosure is shown;

[0031] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the specification and in the related art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, statements that “connect” or “couple” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components. Furthermore, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0034] To address the issue of large frequency variations in buck converters with quasi-fixed frequency and constant on-time architectures caused by existing on-time timing circuits under wide input voltage, output voltage, and varying loads, a novel on-time timing circuit structure is proposed. The on-time timing circuit of this disclosure makes the on-time proportional to the output voltage and inversely proportional to the switching node voltage, thus reducing frequency variations caused by changes in power transistor conduction losses. Furthermore, a delay varying with the input voltage is added to the circuit to offset the comparator switching delay, ultimately resulting in a timing circuit that linearly follows changes in both the switching node voltage and the output voltage. This achieves smaller frequency variations across a wide range of Vi, Vo, and different loads, better meeting the requirements of peripheral applications. The on-time timing circuit of this disclosure will be described in detail below.

[0035] Figure 2 A schematic block diagram of a turn-on timing circuit 100 according to an embodiment of this disclosure is shown. The turn-on timing circuit 100 is used in a buck converter with a quasi-fixed frequency, constant on-time architecture and is capable of outputting a turn-off signal On_timer_out to turn off the upper power transistor of the buck converter. It should be noted that... Figure 2 The diagram also shows other structures of a buck converter (which can be a Buck converter), including the upper transistor hs, the lower transistor ls, the inductor L, the output capacitor Cload, and the load current I. load .like Figure 2As shown, the on-time timing circuit 100 includes: a current generation module 110, a flip-delay cancellation module 120, a capacitor C1, and a comparator comp.

[0036] The input terminal of the current generation module 110 is coupled to the switching node SW of the buck converter, and the output terminal of the current generation module 110 is coupled to the ramp voltage node Vramp. The switching node SW is the node where the upper power transistor hs and the inductor L are coupled in the buck converter. The current generation module 110 is configured to generate a charging current Ic1 proportional to the voltage of the switching node SW after the upper power transistor hs is turned on; this charging current Ic1 is used to charge the capacitor C1. This charging current Ic1 is proportional to... Figure 1 The function of Ion in both cases is the same: to charge the capacitor. Because when the upper power transistor hs is turned on, the voltage V at the switching node SW is... SW The input voltage Vi is calculated by subtracting the conduction loss of the upper power transistor hs, i.e., V SW =Vi-I load ×R hs , among which, I load R is the load current. hs Since the on-resistance of the power transistor is [value missing], a charging current Ic1 proportional to the voltage of the switching node SW is generated by the current generation module 110 to charge capacitor C1, so that the on-time Ton is proportional to the voltage V of the switching node SW. SW It is inversely proportional to (Vi-I), that is, the conduction time Ton is related to (Vi-I) load ×R hs The load current is inversely proportional to the on-time Ton. Therefore, compared to existing on-time timing circuits, this embodiment of the present disclosure takes into account the influence of the load current on the on-time Ton.

[0037] The input of the flip-delay cancellation module 120 is coupled to the ramp voltage node Vramp, and the output of the flip-delay cancellation module 120 is coupled to one end of the capacitor C1. The flip-delay cancellation module 120 is configured to generate a first delay to cancel the flip-delay of the comparator comp based on the variable resistor unit 122 and the capacitor C1. The resistance value of the variable resistor unit 122 is controlled by the input voltage Vi of the buck converter. The first delay is generated to eliminate the influence of the flip-delay of the comparator comp on the conduction time Ton.

[0038] The other end of capacitor C1 is coupled to the ground terminal. Capacitor C1 is configured to be charged by the charging current Ic1 after the upper power transistor hs is turned on.

[0039] The positive input of comparator comp is coupled to the ramp voltage node Vramp, and the negative input is coupled to the first voltage V1. Comparator comp is configured to compare the ramp voltage Vramp corresponding to the ramp voltage node Vramp with the first voltage V1 and generate a turn-off signal On_timer_out. The first voltage V1 is a reference voltage proportional to the output voltage Vo of the buck converter. Specifically, when the ramp voltage is greater than the first voltage V1, the turn-off signal On_timer_out is generated, causing the logic control unit in the buck converter to control the turn-off of the power transistor hs according to the turn-off signal On_timer_out. Setting the first voltage V1 to be proportional to the output voltage Vo ensures that the conduction time Ton is proportional to the output voltage Vo.

[0040] In the conduction timing circuit of the embodiments of this disclosure, the first delay generated by the flip delay cancellation module 120 is used to cancel the flip delay of the comparator comp, thereby eliminating the influence of the flip delay of the comparator comp on the conduction time Ton; and since when the upper power transistor hs is turned on, the voltage of the switching node SW is the input voltage Vi minus the conduction loss of the upper power transistor hs (Vi-I) load ×R hs Therefore, by generating a charging current Ic1 proportional to the voltage of the switching node SW through the current generation module 110 to charge the capacitor C1, the conduction time can be made inversely proportional to the voltage of the switching node SW, that is, the conduction time can be made proportional to (Vi-I) / (V1 - V2). load ×R hs The on-time is inversely proportional to the load current, unlike existing on-time timing circuits which consider the influence of load current on To. The final on-time is directly proportional to the voltage at the switching node SW and inversely proportional to the output voltage Vo. Compared to existing on-time timing circuits, the on-time timing circuit of this disclosure eliminates the influence of comparator comp switching delay and load current variations on the on-time. This allows the on-time timing circuit to maintain a small variation in system operating frequency under a wide range of input voltage Vi, output voltage Vo, and different loads, better meeting the needs of peripheral applications.

[0041] Furthermore, such as Figure 3 As shown, the current generating module 110 includes: a first current generating module 111 and a second current generating module 112, wherein the first current generating module 111 is configured to generate current based on the voltage V of the switching node SW. SW The voltage of the ramp voltage node Vramp generates a first current I1; the second current generation module 112 is configured to generate a second current I2 based on the voltage of the ramp voltage node Vramp, and the sum of the first current I1 and the second current I2 is the charging current Ic1.

[0042] Specifically, such as Figure 4 As shown, the first current generating module 111 includes: a first resistor Rs1 and a first switch T1, wherein one end of the first resistor Rs1 is coupled to the switch node SW, and the other end of the first resistor Rs1 is coupled to one end of the first switch T1, and the other end of the first resistor Rs1 generates a first current I1; the other end of the first switch T1 is coupled to the ramp voltage node Vramp, and the first switch T1 is closed after the upper power transistor hs is turned on, and is opened after the upper power transistor hs is turned off.

[0043] like Figure 4 As shown, the second current generating module 112 includes: first to sixth transistors, a first current source I3, and a second resistor Rs2. The first transistor Mp1 and the second transistor Mp2 form a first current mirror. The source of the first transistor Mp1 and the source of the second transistor Mp2 are both coupled to the power supply voltage Vdd. The gate of the first transistor Mp1 and the gate of the second transistor Mp2 are both coupled to the drain of the first transistor Mp1. The drain of the second transistor Mp2 is coupled to the ramp voltage node Vramp, and the drain of the second transistor Mp2 generates a second current I2. The third transistor Mn1 and the fourth transistor Mn2 form a second current mirror. The gate of the third transistor Mn1 and the gate of the fourth transistor Mn2 are both coupled to the first current mirror. The drain of the third transistor Mn1 is coupled to one end of the first current source I3; the drain of the fourth transistor Mn2 is coupled to the drain of the first transistor Mp1; the source of the fifth transistor Mp3 is coupled to the source of the third transistor Mn1; the gate of the fifth transistor Mp3 is coupled to the ramp voltage node Vramp; and the drain of the fifth transistor Mp3 is coupled to ground. The source of the sixth transistor Mp4 is coupled to the source of the fourth transistor Mn2; the gate of the sixth transistor Mp4 is coupled to the drain of the sixth transistor Mp4; and the drain of the sixth transistor Mp4 is coupled to one end of the second resistor Rs2. The other end of the second resistor Rs2 is coupled to ground, and the other end of the first current source I3 is coupled to the power supply voltage Vdd. It should be noted that the resistance of the first resistor Rs1 is equal to the resistance of the second resistor Rs2, and the current mirror ratio of the first current mirror and the second current mirror is 1. The fifth transistor Mp3 and the sixth transistor Mp4 are also the same transistor. In addition, the first transistor Mp1, the second transistor Mp2, the fifth transistor Mp3, and the sixth transistor Mp4 can be P-type transistors, and the third transistor Mn1 and the fourth transistor Mn2 can be N-type transistors.

[0044] Furthermore, such as Figure 3 As shown, the flip delay cancellation module 120 includes: a decoder unit 121 and a variable resistor unit 122, wherein the decoder unit 121 is configured to generate a switch control signal S according to the input voltage Vi; and the variable resistor unit 122 is configured to adjust the resistance value of the variable resistor unit 122 according to the switch control signal S.

[0045] Specifically, such as Figure 5 As shown, the variable resistor unit 122 includes N resistors (R1, R2, ..., Rn) and N switches (s10, s20, ..., sn0). The N resistors are connected in series, and a switch is connected in parallel across each resistor. The decoder unit 121 includes an N-bit decoder 1211. The switch control signal S includes N switch signals (s1, s2, ..., sn). The input terminal of the N-bit decoder 1211 receives the input voltage Vi, and the output terminal of the N-bit decoder 1211 outputs N switch signals (s1, s2, ..., sn). The N switch signals (s1, s2, ..., sn) control the opening and closing of the N switches (s10, s20, ..., sn0). Each switch corresponds to one switch signal; specifically, s1 controls s10, s2 controls s20, and so on, with sn controlling sn0. The resistance value R of the variable resistor unit 122 is... S The magnitude of R is inversely proportional to the input voltage Vi. That is, the larger Vi is, the larger R is. S The smaller the value, the smaller Vi is, and the smaller R is. S The larger.

[0046] Combination Figure 3-5 The principle of the conduction timing circuit in this embodiment is analyzed as follows: When the upper power transistor hs is turned on, the first switch T1 is closed, according to... Figure 4 From the circuit structure shown, we can obtain that the first current I1 is:

[0047]

[0048] according to Figure 4 The circuit structure in the diagram can also be obtained as follows:

[0049] Vramp+V Mp3 +V Mn1 = V Rs2 +V Mp4 +V Mn2 (2)

[0050] Among them, V Mn1 V Mn2 V Mp3 V Mp4 The voltages V of the third transistor Mn1, the fourth transistor Mn2, the fifth transistor Mp3, and the sixth transistor Mp4 are respectively. Rs2 The voltage across the second resistor;

[0051] Since the current mirror ratios of the first and second current mirrors are both 1, and the fifth transistor Mp3 and the sixth transistor Mp4 are the same transistor, we can obtain:

[0052] V Mp3 =VMp4 V Mn1 =V Mn2 (3)

[0053] Substituting the two equations in equation (3) into equation (2) yields:

[0054] Vramp = V Rs2 (4)

[0055] Therefore, the second current I2 can be obtained as:

[0056] I2 = I MP1 =V Rs2 / Rs2= Vramp / Rs2 (5)

[0057] According to equations (1) and (5), the charging current Ic1 is:

[0058]

[0059] When the upper power transistor hs is turned on, according to Figure 3 From the circuit diagram, we can see that the voltage V at the switching node SW is... SW =Vi-I load ×R hs , where I load R is the load current. hs is the on-resistance of the power transistor hs.

[0060] according to Figure 3-5 From the circuit diagram, we can obtain the following equation that is satisfied at the end of the conduction timing:

[0061]

[0062] Among them, R S Vc1 is the equivalent resistance of variable resistor unit 122, and Vc1 is the voltage across capacitor C1. Based on the relationship between capacitor current and voltage, we can obtain:

[0063]

[0064] Substituting equation (8) into equation (7) yields:

[0065]

[0066] Transforming equation (9) yields:

[0067]

[0068] The actual conduction time also needs to be added to the comparator's flip-over delay Tcomp, so equation (10) becomes:

[0069]

[0070] In the formula, Tcomp changes with Vi, and R S *C1 also varies with Vi. If the two are equal, i.e., R S *C1 = Tcomp, which can cancel out the effect of Tcomp on Ton. Assuming V1 = k·Vo, equation (11) becomes:

[0071]

[0072] Furthermore, the general expression for Ton, derived from the volt-second balance principle of buck converters, is as follows:

[0073]

[0074] Where T S For the switching cycle of the buck converter, equation (12) is transformed into equation (13) to obtain:

[0075]

[0076] Comparing equation (14) with equation (13), we obtain T in the embodiments of this disclosure. S for:

[0077] T S =k·Rs1·C1, (15)

[0078] According to equation (15), T in the embodiments of this disclosure can be seen. S Don't follow me load The change, when the values ​​of k, Rs1, and C1 are constant, is related to T. S Since it is a constant, the operating frequency can remain unchanged. It should be noted that this "unchanged operating frequency" is not absolute, but rather considered constant relative to changes in the background technology. However, in practice, it may still be affected by the non-ideal properties of components such as inductors. The embodiments disclosed in this disclosure primarily address eliminating the influence of switching delay time and load current on Ton.

[0079] Additionally, for the R of the variable resistor unit 122 S The determination of R and the setting of the resistor in the variable resistor unit 122 are explained: S *C1 = Tcomp, which determines R S = Tcomp / C1, where C1 is a constant, and Tcomp changes with Vi, with larger Vi resulting in smaller Tcomp. R S It is also larger. After Tcomp and C1 are determined, R can be obtained. S R S It also changes with Vi, therefore according to RS The values ​​of R1, R2, ..., Rn can be set. An example is given where Vi has 10 possible values, resulting in 10 values ​​for Tcomp. These 10 values ​​can then be calculated to obtain 10 values ​​for R. S The value, then based on 10 R S The number of resistors in the variable resistor unit 122 and the value of each resistor can be set. For example, it can be set to 10 resistors, and the value of each resistor can be set to one of the resistors, R. S The value of R is required when the circuit is working. S The value determines which resistor's switch is turned on, and the switches of the other resistors are turned off. Alternatively, it can be done according to each R... S The value is set in a manner equal to the sum of two or more resistors. This disclosure does not limit the method of setting the number and value of resistors in the variable resistor unit 122.

[0080] Furthermore, such as Figure 6 As shown, the conduction timing circuit 100 also includes a second switch T2, which is coupled between the ramp voltage node Vramp and the ground terminal. The second switch T2 opens after the first switch T1 is closed and closes after the first switch T1 is open. Since the conduction timing ends after the upper power transistor hs is turned off, the first switch T1 needs to be open and the second switch T2 needs to be closed.

[0081] Embodiments of this disclosure also provide a buck converter with a quasi-fixed-frequency constant on-time architecture, including the on-time timing circuit described in the foregoing embodiments. After the upper power transistor of the buck converter is turned on, the on-time timing circuit begins timing. The on-time timing ends when the on-time timing circuit outputs a turn-off signal, and the buck converter turns off the upper power transistor according to the turn-off signal. In applications with a wide range of input voltage Vi, output voltage Vo, and different loads, the buck converter with a quasi-fixed-frequency constant on-time architecture of this disclosure can also ensure small variations in the system operating frequency, better meeting the needs of peripheral applications.

[0082] In summary, the on-time timing circuit in the embodiments of this disclosure can obtain a timer that varies with Vi, Vo, and I. load The effect of a very small change in operating frequency.

[0083] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0084] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0085] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0086] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A turn-on timing circuit for a buck converter with a quasi-fixed frequency and constant on-time architecture, capable of outputting a turn-off signal to turn off the upper power transistor of the buck converter, characterized in that, The conduction timing circuit includes: a current generation module, a flip delay cancellation module, a capacitor, and a comparator. The input terminal of the current generation module is coupled to the switching node of the buck converter, and the output terminal of the current generation module is coupled to the ramp voltage node. The switching node is the node where the upper power transistor and the inductor are coupled in the buck converter. The current generation module is configured to generate a charging current proportional to the voltage of the switching node after the upper power transistor is turned on. The input terminal of the flip delay cancellation module is coupled to the ramp voltage node, and the output terminal of the flip delay cancellation module is coupled to one end of the capacitor. The flip delay cancellation module is configured to generate a first delay to cancel the flip delay of the comparator based on the variable resistor unit and the capacitor. The resistance value of the variable resistor unit is controlled by the input voltage of the buck converter. The other end of the capacitor is coupled to the ground terminal, and the capacitor is configured to be charged by the charging current after the upper power transistor is turned on. The positive input of the comparator is coupled to the ramp voltage node, and the negative input of the comparator is coupled to a first voltage. The comparator is configured to compare the magnitude of the ramp voltage corresponding to the ramp voltage node with the first voltage and generate the turn-off signal. The first voltage is a reference voltage that is proportional to the output voltage of the buck converter.

2. The conduction timing circuit according to claim 1, characterized in that, The current generating module includes: a first current generating module and a second current generating module. The first current generating module is configured to generate a first current based on the voltage of the switching node and the voltage of the ramp voltage node. The second current generating module is configured to generate a second current based on the voltage of the ramp voltage node, wherein the sum of the first current and the second current is the charging current.

3. The conduction timing circuit according to claim 1, characterized in that, The flip delay cancellation module includes: a decoder unit and a variable resistor unit. The decoder unit is configured to generate a switching control signal based on the input voltage. The variable resistor unit is configured to adjust its resistance value according to the switch control signal.

4. The conduction timing circuit according to claim 2, characterized in that, The first current generating module includes: a first resistor and a first switch. Wherein, one end of the first resistor is coupled to the switch node, the other end of the first resistor is coupled to one end of the first switch, and the other end of the first resistor generates the first current; The other end of the first switch is coupled to the ramp voltage node. The first switch closes when the upper power transistor is turned on and opens when the upper power transistor is turned off.

5. The conduction timing circuit according to claim 4, characterized in that, The second current generating module includes: first to sixth transistors, a first current source, and a second resistor. In this configuration, the first transistor and the second transistor form a first current mirror. The source of the first transistor and the source of the second transistor are both coupled to the power supply voltage. The gate of the first transistor and the gate of the second transistor are both coupled to the drain of the first transistor. The drain of the second transistor is coupled to the ramp voltage node. The drain of the second transistor generates the second current. The third transistor and the fourth transistor form a second current mirror. The gate of the third transistor and the gate of the fourth transistor are both coupled to the drain of the third transistor. The drain of the third transistor is coupled to one end of the first current source, and the drain of the fourth transistor is coupled to the drain of the first transistor. The source of the fifth transistor is coupled to the source of the third transistor, the gate of the fifth transistor is coupled to the ramp voltage node, and the drain of the fifth transistor is coupled to ground. The source of the sixth transistor is coupled to the source of the fourth transistor, the gate of the sixth transistor is coupled to the drain of the sixth transistor, and the drain of the sixth transistor is coupled to one end of the second resistor. The other end of the second resistor is coupled to the ground terminal, and the other end of the first current source is coupled to the power supply voltage.

6. The conduction timing circuit according to claim 3, characterized in that, The variable resistor unit includes N resistors and N switches. In this configuration, N resistors are connected in series, and a switch is connected in parallel across each resistor.

7. The conduction timing circuit according to claim 6, characterized in that, The decoder unit includes an N-bit decoder, and the switch control signal includes N switch signals. The input terminal of the N-bit decoder receives the input voltage, and the output terminal of the N-bit decoder outputs the N switch signals. The N switch signals control the opening and closing of the N switches, and each switch corresponds to one switch signal.

8. The conduction timing circuit according to claim 1, characterized in that, The resistance value of the variable resistor unit is inversely proportional to the input voltage.

9. The conduction timing circuit according to claim 5, characterized in that, The resistance value of the first resistor is equal to the resistance value of the second resistor.

10. A buck converter with a quasi-fixed-frequency, constant-on-time architecture, characterized in that, Includes the conduction timing circuit according to any one of claims 1 to 9.

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