Bus wiring method and device, computing device and storage medium

Abstract

The present invention discloses a bus wiring method and device, a computing device and a storage medium. The bus wiring method according to an embodiment of the present invention includes obtaining a bus connection point to be connected; establishing a first connection end, the first connection end includes at least two of the bus connection points; establishing a second connection end, the second connection end includes at least two of the bus connection points, wherein the bus connection points in the second connection end are different from the bus connection points in the first connection end; wiring between the first connection end and the second connection end to obtain an intermediate wiring; and wiring between the corresponding bus connection points of the first connection end and the bus connection points of the second connection end according to the intermediate wiring. The bus wiring method and device, the computing device and the storage medium according to the embodiment of the present invention can quickly complete bus wiring.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit simulation, and in particular to a bus wiring method and device, a computing device and a storage medium. Background Art

[0002] The size of integrated circuit layout data is growing with the advancement of process nodes and the increase in design complexity. If layout design still relies solely on manual labor, the integrated circuit R&D cycle will be excessively long. To further improve the efficiency of layout design, computer-aided design technology is indispensable.

[0003] During analog integrated circuit layout design, numerous buses (hereinafter referred to as "buses") must be connected. Bus connections must meet numerous requirements, such as ensuring the presence of obstacles within the bus connection area, ensuring matching between bus ports, and maintaining consistent routing behavior, such as turning together and jumping layers together. Furthermore, bus routing typically requires meeting certain constraints, such as connection relationships and design rule constraints.

[0004] In the existing technology, analog integrated circuit layout still relies heavily on manual design. At present, wiring technology cannot maintain matching between the connections between wire nets during bus wiring of integrated circuits, and the wiring results cannot meet DRC (Design Rules Checking). The ease of use of the router is poor.

[0005] Therefore, it is hoped that there will be a new bus wiring method and device, computing device and storage medium that can overcome the above problems. Summary of the Invention

[0006] In view of the above problems, an object of the present invention is to provide a bus wiring method and device, a computing device and a storage medium, so as to improve the efficiency of wiring.

[0007] According to one aspect of the present invention, a bus routing method is provided, which is applied to integrated circuit simulation design. The bus routing method comprises:

[0008] Get the bus connection point to be connected;

[0009] Establishing a first connection end, wherein the first connection end includes at least two of the bus connection points;

[0010] Establishing a second connection end, the second connection end including at least two of the bus connection points, wherein the bus connection point in the second connection end is different from the bus connection point in the first connection end;

[0011] wiring between the first connection end and the second connection end to obtain an intermediate wiring; and

[0012] According to the intermediate wiring, wiring is performed between the corresponding bus connection point of the first connection end and the bus connection point of the second connection end.

[0013] Optionally, at the first connection end, the distances between any two adjacent bus connection points are the same;

[0014] The bus connection points in the first connection end are located in the same wiring layer;

[0015] The bus connection points in the first connection end and the bus connection points in the second connection end that are connected to each other are located at the same relative positions in the first connection end and the second connection end.

[0016] Optionally, the bus connection point includes a pin;

[0017] The bus wiring method further includes:

[0018] Obtaining a corresponding bus connection point to be connected according to the bus connection point in the first connection end; and

[0019] The second connection end is established according to the bus connection point to be connected.

[0020] Optionally, wiring between the first connection end and the second connection end to obtain an intermediate wiring includes:

[0021] Obtaining intermediate wiring parameters based on wiring parameters of the bus connection point in the first connection end and wiring parameters of the bus connection point in the second connection end; and

[0022] The intermediate wiring is obtained by wiring according to the intermediate wiring parameters.

[0023] Optionally, the intermediate wiring parameters include intermediate line width parameters and intermediate hole parameters;

[0024] The intermediate line width parameter is determined according to at least one of the number of corresponding bus connection points, minimum line width, minimum interval and topology mode;

[0025] The intermediate hole parameters are divided into inflection intermediate hole parameters and same-direction intermediate hole parameters according to different topological modes.

[0026] The inflection middle hole parameter is determined according to at least one of the middle line width parameter in the outgoing line direction, the wiring parameter of the bus connection point in the incoming line direction, the wiring parameter of the corresponding bus connection point, the number of corresponding bus connection points, and the minimum interval;

[0027] The parameters of the same-direction intermediate holes are determined according to at least one of wiring parameters of corresponding bus connection points, the number of corresponding bus connection points, and a minimum interval.

[0028] Optionally, the bus wiring method further includes:

[0029] In the routing area, get the obstacles;

[0030] According to the intermediate wiring parameters and the obstacles, a prohibited wiring area is obtained.

[0031] Wherein, wiring is prohibited in the prohibited wiring area.

[0032] Optionally, wiring is performed between corresponding bus connection points in the first connection end and bus connection points in the second connection end to obtain multiple bus wirings,

[0033] The bus wiring is located in the region of the intermediate wiring, and the bus wiring has the same direction as that of the intermediate wiring.

[0034] Optionally, wiring between the first connection end and the second connection end to obtain an intermediate wiring includes:

[0035] According to the intermediate routing parameters and the single-source Dijkstra algorithm, the routing point chain is obtained.

[0036] The wiring point chain is used to obtain the intermediate wiring.

[0037] Optionally, wiring between the corresponding bus connection point of the first connection end and the bus connection point of the second connection end according to the intermediate wiring includes:

[0038] Splitting the routing point chain into multiple parallel sub-point chains; and

[0039] Obtaining the bus connection point wiring according to the sub-point chain; and / or

[0040] Determining the direction of the wiring hole according to the outgoing and incoming directions of the middle hole in the middle wiring;

[0041] The wiring between the bus connection points is obtained according to the middle hole, and the intersection of at least two of the wiring between the bus connection points is used as a punching point of the wiring hole.

[0042] According to another aspect of the present invention, a bus wiring device is provided for use in integrated circuit simulation design. The bus wiring device comprises:

[0043] An acquisition unit, used for acquiring a bus connection point to be connected;

[0044] an establishing unit, configured to establish a first connection end and a second connection end, wherein the first connection end includes at least two of the bus connection points, the second connection end includes at least two of the bus connection points, and the bus connection points in the second connection end are different from the bus connection points in the first connection end;

[0045] an intermediate wiring unit, configured to wire between the first connection end and the second connection end to obtain an intermediate wiring; and

[0046] A wiring unit is used to lay wiring between the corresponding bus connection point of the first connection end and the bus connection point of the second connection end according to the intermediate wiring.

[0047] According to another aspect of the present invention, a computing device is provided, comprising a processor; and a memory for storing one or more programs, wherein when the one or more programs are executed by the processor, the processor implements the bus wiring method as described above.

[0048] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, wherein when the program is executed by a processor, the bus wiring method described above is implemented.

[0049] According to the bus routing method and device, computing device, and storage medium of the embodiments of the present invention, multiple bus connection points to be routed are merged into connection ends for preliminary intermediate routing, and then the routing of each bus connection point is obtained based on the splitting of the intermediate routing. This eliminates the need to route each bus connection point individually, and allows for rapid completion of bus routing.

[0050] Furthermore, determining the intermediate wiring parameters based on the wiring parameters of the bus connection points can ensure that the bus wiring remains matched.

[0051] Furthermore, the intermediate wiring parameters include intermediate line width parameters and intermediate hole parameters, which support multi-through-hole wiring and help improve chip manufacturing yield.

[0052] Furthermore, different bus wirings are reasonably divided into corresponding connection terminals, which can avoid violating design rules while ensuring wiring accuracy and improve wiring efficiency.

[0053] Furthermore, obstacle avoidance routing is performed during the intermediate routing, ensuring that the final routing can avoid obstacles and effectively reduce DRC.

[0054] Furthermore, the single-source Dijkstra algorithm is used to obtain the BusNet point chain, and then the bus connection points are routed according to the point chain, which can effectively reduce the violation of design rules during routing. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0056] Figure 1 A method flow chart of a bus wiring method according to an embodiment of the present invention is shown.

[0057] Figure 2 A schematic diagram showing a generalized pin combination of Bus lines into a BusNet according to an embodiment of the present invention is shown.

[0058] Figure 3 A schematic diagram showing a topology pattern of a BusNet generalized line according to an embodiment of the present invention is shown.

[0059] Figure 4 A schematic diagram showing a topological pattern of a BusNet generalized hole according to an embodiment of the present invention is shown.

[0060] Figure 5 A schematic diagram illustrating a topological pattern of an inflection hole in a BusNet generalized hole according to an embodiment of the present invention is shown.

[0061] Figure 6 A schematic diagram illustrating a topological pattern of unidirectional holes in a BusNet generalized hole according to an embodiment of the present invention is shown.

[0062] Figure 7 A schematic diagram is shown with BusNet as a marker according to an embodiment of the present invention.

[0063] Figure 8 A schematic diagram of BusNet point chain generation according to an embodiment of the present invention is shown.

[0064] Figure 9 A schematic diagram of restoring a Path in Bus wiring according to an embodiment of the present invention is shown.

[0065] Figure 10 A schematic diagram of restoring Via in Bus wiring according to an embodiment of the present invention is shown.

[0066] Figure 11 A schematic diagram of a wiring window according to an embodiment of the present invention is shown.

[0067] Figure 12 A schematic diagram of wiring results according to an embodiment of the present invention is shown.

[0068] Figure 13 FIG. 4 is a schematic diagram showing a wiring result according to another embodiment of the present invention.

[0069] Figure 14 A schematic diagram of a selection mode of a wiring window according to an embodiment of the present invention is shown.

[0070] Figure 15 A schematic structural diagram of a bus wiring device according to an embodiment of the present invention is shown.

[0071] Figure 16 A schematic structural diagram of a server according to an embodiment of the invention is shown. DETAILED DESCRIPTION

[0072] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown in the drawings.

[0073] Specific embodiments of the present invention are described in further detail below with reference to the accompanying drawings and examples. Numerous specific details of the present invention, such as component structures, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present invention. However, as those skilled in the art will appreciate, the present invention may be practiced without these specific details.

[0074] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0075] Figure 1 FIG2 shows a flow chart of a bus wiring method according to an embodiment of the present invention. Figure 1 As shown, the bus routing method according to an embodiment of the present invention is applied to integrated circuit simulation design, comprising the following steps:

[0076] In step S101, a bus connection point to be connected is obtained;

[0077] Obtain a bus connection point to be connected. The bus connection point is, for example, a point that needs to be connected during a bus connection process, and the bus connection point may include a pin to be connected.

[0078] In step S102, a first connection end is established, wherein the first connection end includes at least two of the bus connection points;

[0079] A first connection terminal is established, the first connection terminal including at least two bus connection points. The first connection terminal can be used as a whole to perform wiring operations in subsequent steps.

[0080] In step S103, a second connection end is established, wherein the second connection end includes at least two of the bus connection points, wherein the bus connection point in the second connection end is different from the bus connection point in the first connection end;

[0081] A second connection terminal is established, the second connection terminal including at least two bus connection points. The second connection terminal can be used as a whole for wiring operations in subsequent steps. The bus connection points in the second connection terminal are different from the bus connection points in the first connection terminal.

[0082] Optionally, a corresponding bus connection point to be connected is obtained based on the bus connection point in the first connection end. A second connection end is established based on the bus connection point to be connected. Optionally, the corresponding bus connection point to be connected is the bus connection point in the second connection end.

[0083] In step S104, wiring is performed between the first connection end and the second connection end to obtain an intermediate wiring;

[0084] A wiring is formed between the first connection terminal and the second connection terminal to obtain an intermediate wiring. Optionally, when performing the intermediate wiring, the first connection terminal and the second connection terminal are respectively wired as a whole connection terminal. The intermediate wiring is not the final wiring, but an intermediate product in the process of obtaining the final wiring.

[0085] In step S105 , wiring is performed between the corresponding bus connection point of the first connection end and the bus connection point of the second connection end according to the intermediate wiring.

[0086] Based on the intermediate wiring, wiring is generated between the corresponding bus connection points of the first connection end and the bus connection points of the second connection end. Optionally, based on the obtained intermediate wiring and in accordance with the correspondence between the bus connection points in the first connection end and the second connection end, the bus connection points in the first connection end and the second connection end are correspondingly connected. Optionally, wiring is generated between the corresponding bus connection points in the first connection end and the bus connection points in the second connection end to obtain multiple bus wiring lines. The bus wiring lines are located in the region of the intermediate wiring lines, and the bus wiring lines have the same orientation as the intermediate wiring lines.

[0087] The bus wiring method of the present application (including a bus wiring method based on a maze algorithm) is described in detail below with reference to the accompanying drawings and some specific embodiments.

[0088] In an optional embodiment of the present invention, the bus wiring method (a bus wiring method based on a maze algorithm) includes the following steps:

[0089] Step 1: Divide the pins of the bus network to be connected into two groups (i.e., a first connection end and a second connection end). These two groups can be considered as the generalized routing pins of two bus wirings, thereby converting the bus wiring into a two-terminal network. The network to which these two generalized pins belong is hereinafter referred to as the BusNet. Optionally, in the first connection end / second connection end, the spacing between any two adjacent bus connection points is the same; the bus connection points in the first connection end are located on the same wiring layer; and the bus connection points in the first connection end and the second connection end of the corresponding connection are in the same relative position within the first connection end and the second connection end.

[0090] Figure 2 FIG. 1 shows a schematic diagram of a Bus line network combined into a generalized pin of a BusNet according to an embodiment of the present invention. Figure 2 As shown, a group of pins that need to be wired for Bus are combined into a pin for "BusNet" wiring (i.e., combined into a first connection end / a second connection end). Optionally, the spacing between two adjacent Pins in the same group (first connection end / a second connection end) is the same, and the width and spacing between Pins in different groups may be different; the relative positions of the two Pins to be connected are the same in each group; the Pin layers in the same group are the same, and the Pin sizes are the same. Furthermore, the size of the pins of the Bus network in the same group is the same, the spacing between the pins is the same, and they are located on the same metal layer. The size of a generalized pin of BusNet is equal to the circumscribed rectangle of all Bus network pins in the same group, and the metal layer where the generalized pin is located is equal to the metal layer where the Bus network pins in the same group are located.

[0091] Step 2: Obtain intermediate wiring parameters based on the wiring parameters of the bus connection point in the first connection end and the wiring parameters of the bus connection point in the second connection end. The intermediate wiring parameters include intermediate line width parameters and intermediate hole parameters;

[0092] Specifically, based on the user-defined Bus routing parameters, BusNet routing parameters are established, namely, BusNet's generalized lines and generalized holes. The paths generated by BusNet's generalized lines can completely replace the paths created by BusNet routing. The paths generated by BusNet's generalized holes can completely replace the holes created by BusNet routing. Routing parameters include, for example, at least one of minWidth, minSpacing, and hole-related parameters.

[0093] In an optional embodiment of the present invention, the intermediate line width parameter is determined based on at least one of the number of corresponding bus connection points, the minimum line width, the minimum spacing, and the topological mode. The intermediate hole parameters are divided into inflection intermediate hole parameters and same-direction intermediate hole parameters based on different topological modes. The inflection intermediate hole parameters are determined based on at least one of the intermediate line width parameter in the outgoing direction, the wiring parameters of the bus connection points in the incoming direction, the wiring parameters of the corresponding bus connection points, the number of corresponding bus connection points, and the minimum spacing; the same-direction intermediate hole parameters are determined based on at least one of the wiring parameters of the corresponding bus connection points, the number of corresponding bus connection points, and the minimum spacing.

[0094] Figure 3 A schematic diagram showing a topology pattern of a BusNet generalized line according to an embodiment of the present invention is shown.

[0095] Figure 4 A schematic diagram showing a topological pattern of a BusNet generalized hole according to an embodiment of the present invention is shown.

[0096] Figure 5 A schematic diagram illustrating a topological pattern of an inflection hole in a BusNet generalized hole according to an embodiment of the present invention is shown. Figure 6 A schematic diagram illustrating a topological pattern of unidirectional holes in a BusNet generalized hole according to an embodiment of the present invention is shown.

[0097] Combine Figures 3 to 6 As shown, the generalized line width of BusNet is BusWire.

[0098] BusWire=minWidth×n+(n-1)×minSpacing.

[0099] Where n is the number of bus nets, min Width is the minimum width, and min Spacing is the minimum spacing.

[0100] There are two topological modes of BusNet generalized holes: "inflection hole" and "same-direction hole".

[0101] For inflection holes:

[0102]

[0103] For the same direction holes:

[0104]

[0105] Among them, w2 is the BusWire line width in the generalized hole exit direction, wire1 is the line width of the Bus wire net in the generalized hole entry direction, wire2 is the line width of the Bus wire net in the generalized hole entry direction, via_height and via_width are the sizes of the holes in the Bus wire net, n is the number of Bus wire nets, and min Spacing is the minimum spacing.

[0106] Step 3: routing according to the intermediate routing parameters to obtain the intermediate routing;

[0107] According to the generalized lines and generalized holes of BusNet, a grid map based on Bus routing is constructed.

[0108] Optionally, the bus routing method further includes: obtaining obstacles in the routing area; and obtaining a prohibited routing area based on the intermediate routing parameters and the obstacles, wherein routing is prohibited in the prohibited routing area.

[0109] According to the bus wiring method of an embodiment of the present invention, a set of topological patterns and calculation formulas for generalized lines are established. Generalized lines can replace the routing during the bus wiring process and can also be restored to the lines of the bus network wiring. A set of topological patterns and calculation formulas for generalized holes are established. Generalized holes can replace the punching during the bus network wiring process and can also be restored to the holes of the bus network wiring.

[0110] Figure 7 FIG2 shows a schematic diagram of a BusNet according to an embodiment of the present invention. Figure 7 As shown, generalized lines and generalized holes mark objects in the routing space. Marking means that routing or drilling is prohibited within this area. Marking areas are marked on obstacles; during the routing process, routing is prohibited within the marked area. Marking is divided into line marking and hole marking. Line marking is performed by expanding the obstacle to an area equal to half the generalized line width plus the minSpacing value. Hole marking is performed on the metal layer where the obstacle is located, the two metal layers above and below it, and the cut layer. This area is expanded in both the x and y directions to half the size of the generalized hole plus the minSpacing value.

[0111] Step 4: Obtain the routing point chain based on the intermediate routing parameters and the single-source Dijkstra algorithm;

[0112] A routing point chain is obtained based on the intermediate routing parameters and the single-source Dijkstra algorithm, wherein the routing point chain is used to obtain the intermediate routing.

[0113] Figure 8 FIG2 shows a schematic diagram of BusNet point chain generation according to an embodiment of the present invention. Figure 8As shown in Figure 2, the BusNet point chain can be obtained by using the single-source Dijkstra algorithm.

[0114] Step 5: wiring between the corresponding bus connection point of the first connection end and the bus connection point of the second connection end according to the intermediate wiring.

[0115] Based on the intermediate wiring, wiring is routed between the corresponding bus connection points of the first connection end and the bus connection points of the second connection end. Optionally, this includes: splitting a wiring point chain into multiple parallel sub-point chains; obtaining wiring between bus connection points based on the sub-point chains; and / or determining the direction of the wiring hole based on the outgoing and incoming directions of the intermediate holes in the intermediate wiring; obtaining wiring between bus connection points based on the intermediate holes, and using the intersection of at least two bus connection point wirings as the punching point for the wiring hole.

[0116] Specifically, Figure 9 A schematic diagram of restoring a Path (line / wiring) in a Bus wiring according to an embodiment of the present invention is shown. Figure 10 A schematic diagram of restoring a Via (hole) in Bus wiring according to an embodiment of the present invention is shown.

[0117] Combine Figure 9 and Figure 10 As shown in the figure, the BusNet node chain is used to restore the Bus routing results. Based on the topological patterns of generalized lines and generalized holes, the restoration is divided into path restoration and via restoration. By combining the path and via restoration results, the routing results of each network cable in the Bus can be obtained.

[0118] Path restoration involves splitting a bus line into multiple parallel lines (if the number of bus lines is odd, the original line is retained; if the number of bus lines is even, the original line is discarded). Paths are then generated for each line segment. Via restoration involves first determining the hole direction based on the incoming and outgoing lines, then creating a path using a generalized hole calculation method. Finally, the intersection of the paths is calculated, and these intersections serve as the punch points.

[0119] In the above embodiment of the present invention, the data of generalized lines and generalized holes are used to mark in the wiring space, and a wiring point chain can be obtained using the single-source Dijkstra algorithm.

[0120] The technical solution of this application is described below with reference to a specific embodiment.

[0121] Figure 11 A schematic diagram of a wiring window according to an embodiment of the present invention is shown. Figure 11 The Automatic RouterBus wiring window shown is displayed on a display interface of a computer, for example, for wiring operations. After the wiring operations are performed in the wiring window, the final wiring is obtained. Figure 12 FIG. 4 shows a schematic diagram of wiring results according to an embodiment of the present invention. Figure 13 FIG. 1 shows a schematic diagram of wiring results according to another embodiment of the present invention. The final wiring obtained can be referred to Figure 12 and Figure 13 shown.

[0122] Optionally, Figure 14 FIG. 1 shows a schematic diagram of a selection mode of a wiring window according to an embodiment of the present invention. Figure 14 As shown, select Bus mode in the Automatic Router interface; select Use Pin Width in Bus mode; for path generation, select A <1> ,A <2> ,A <3> , click the Apply button in the Automatic Router wiring window to get the wiring result as follows Figure 13 shown.

[0123] According to another aspect of the present invention, a bus wiring device is provided. Figure 15 FIG2 shows a schematic diagram of the structure of a bus wiring device according to an embodiment of the present invention. Figure 15 As shown, the bus routing device is applied to integrated circuit simulation design and is used to implement the above bus routing method. The bus routing device includes an acquisition unit 810, an establishment unit 820, an intermediate routing unit 830 and a routing unit 840.

[0124] Specifically, the acquiring unit 810 is used to acquire a bus connection point to be connected.

[0125] The establishing unit 820 is configured to establish a first connection end and a second connection end, wherein the first connection end includes at least two bus connection points, and the second connection end includes at least two bus connection points; the bus connection points in the second connection end are different from the bus connection points in the first connection end.

[0126] The intermediate wiring unit 830 is used to connect wiring between the first connection end and the second connection end to obtain intermediate wiring.

[0127] The wiring unit 840 is used to connect wiring between the corresponding bus connection point of the first connection end and the bus connection point of the second connection end according to the intermediate wiring.

[0128] Figure 16 A schematic structural diagram of a server according to an embodiment of the invention is shown.

[0129] refer to Figure 16 , the present disclosure also provides a block diagram of an exemplary server (computing device) suitable for implementing the embodiments of the present disclosure. It should be understood that, Figure 16 The server shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0130] like Figure 16 As shown, server 900 is a general-purpose computing device. Components of server 900 may include, but are not limited to, one or more processors or processing units 910, memory 920, and a bus 901 connecting various system components (including memory 920 and processing unit 910).

[0131] Bus 901 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. Examples of these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0132] The server 900 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the server 900, including volatile and non-volatile media, removable and non-removable media.

[0133] The system memory 920 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 921 and / or cache memory 922. The server 900 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 923 may be used to read and write non-removable, non-volatile magnetic media ( Figure 16 Not shown, often called a "hard drive"). Although Figure 16 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 901 via one or more data medium interfaces. Memory 920 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of each embodiment of the present disclosure.

[0134] A program / utility 924 having a set (at least one) of program modules 9241 may be stored, for example, in memory 920. Such program modules 9241 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may include an implementation of a network environment. Program modules 9241 generally implement the functions and / or methods described in the embodiments of the present disclosure.

[0135] Furthermore, the server 900 may also be in communication with a display 990 for displaying the results of the screening and sorting. The display 990 may include, but is not limited to, a liquid crystal display (LCD), a light emitting diode (LED) display, and a plasma display. In some embodiments, the display 990 may also be a touch screen.

[0136] Furthermore, the server 900 may also communicate with one or more devices that enable users to interact with the server 900, and / or with any device that enables the server 900 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may occur via an input / output (I / O) interface 930. Furthermore, the server 900 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 940. As shown, the network adapter 940 communicates with other modules of the server 900 via a bus 901. It should be understood that, although not shown, other hardware and / or software modules may be used in conjunction with the server 900, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0137] The processing unit 910 executes various functional applications and data processing by running programs stored in the system memory 920, such as implementing the methods described in the above embodiments of the present disclosure.

[0138] The present disclosure further provides a computer-readable storage medium having a computer program (or computer-executable instructions) stored thereon. When the program is executed by a processor, it is used to execute the method described in the above embodiments of the present disclosure. The specific method can be referred to in the claims.

[0139] The computer storage medium of the embodiment of the present disclosure can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0140] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0141] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0142] Computer program code for performing the operations of the disclosed embodiments may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​(such as Java, Smalltalk, C++), and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0143] According to the bus routing method and device, computing device and storage medium of the embodiments of the present invention, a bus routing based on a maze algorithm is proposed, which converts the routing of a bus port network into a two-end routing of a network (BusNet) (the bus network cables to be connected are divided into two groups, and the bus routing is converted into the routing of a two-end network). The routing parameters (lines and holes) and the routing topology of the BusNet are determined by the routing parameters and topology of the bus network. By establishing a set of generalized lines and generalized line topology patterns and calculation formulas, and creating a routing grid, obstacles in the routing space are marked using generalized lines and generalized holes, and a single-source Dijkstra algorithm is used to obtain a routing point chain. Finally, the point chain is restored to the routing result of the bus network. The technical solution provided by the present application can avoid obstacles during routing and maintain matching between bus network lines, while meeting design rule checks and improving layout design efficiency and ease of use.

[0144] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0145] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A bus routing method, applied to integrated circuit simulation design, comprising: Get the bus connection point to be connected; Establishing a first connection end, wherein the first connection end includes at least two of the bus connection points; Establishing a second connection end, the second connection end including at least two of the bus connection points, wherein the bus connection point in the second connection end is different from the bus connection point in the first connection end; wiring between the first connection end and the second connection end to obtain an intermediate wiring; and According to the intermediate wiring, wiring is performed between the corresponding bus connection point of the first connection end and the bus connection point of the second connection end, The wiring between the first connection end and the second connection end to obtain the intermediate wiring includes: Obtaining intermediate wiring parameters based on wiring parameters of the bus connection point in the first connection end and wiring parameters of the bus connection point in the second connection end; and routing according to the intermediate routing parameters to obtain the intermediate routing; The intermediate wiring parameters include intermediate line width parameters and intermediate hole parameters; The intermediate line width parameter is determined according to at least one of the number of corresponding bus connection points, minimum line width, minimum interval and topology mode; The intermediate hole parameters are divided into inflection intermediate hole parameters and same-direction intermediate hole parameters according to different topological modes. The inflection middle hole parameter is determined according to at least one of the middle line width parameter in the outgoing line direction, the wiring parameter of the bus connection point in the incoming line direction, the wiring parameter of the corresponding bus connection point, the number of corresponding bus connection points, and the minimum interval; The parameters of the same-direction intermediate holes are determined according to at least one of the wiring parameters of the corresponding bus connection points, the number of the corresponding bus connection points, and the minimum spacing; The bus wiring method further includes: In the routing area, get the obstacles; According to the intermediate wiring parameters and the obstacles, a prohibited wiring area is obtained. Wherein, wiring is prohibited in the prohibited wiring area.

2. The bus wiring method according to claim 1, wherein: At the first connection end, the distance between any two adjacent bus connection points is the same; The bus connection points in the first connection end are located in the same wiring layer; The bus connection points in the first connection end and the bus connection points in the second connection end that are connected to each other are located at the same relative positions in the first connection end and the second connection end.

3. The bus wiring method according to claim 1, wherein: The bus connection point includes a pin; The bus wiring method further includes: Obtaining a corresponding bus connection point to be connected according to the bus connection point in the first connection end; and The second connection end is established according to the bus connection point to be connected.

4. The bus wiring method according to claim 1, wherein: Routing between the corresponding bus connection points in the first connection end and the bus connection points in the second connection end to obtain a plurality of bus wirings, The bus wiring is located in the region of the intermediate wiring, and the bus wiring has the same direction as that of the intermediate wiring.

5. The bus wiring method according to claim 1, wherein: The wiring between the first connection end and the second connection end to obtain the intermediate wiring includes: According to the intermediate routing parameters and the single-source Dijkstra algorithm, the routing point chain is obtained. The wiring point chain is used to obtain the intermediate wiring.

6. The bus wiring method according to claim 5, wherein: The wiring between the corresponding bus connection point of the first connection end and the bus connection point of the second connection end according to the intermediate wiring includes: Splitting the routing point chain into multiple parallel sub-point chains; and Obtaining the bus connection point wiring according to the sub-point chain; and / or Determining the direction of the wiring hole according to the outgoing and incoming directions of the middle hole in the middle wiring; The wiring between the bus connection points is obtained according to the middle hole, and the intersection of at least two of the wiring between the bus connection points is used as a punching point of the wiring hole.

7. A bus wiring device, applied to integrated circuit simulation design, comprising: An acquisition unit, used for acquiring a bus connection point to be connected; an establishing unit, configured to establish a first connection end and a second connection end, wherein the first connection end includes at least two of the bus connection points, the second connection end includes at least two of the bus connection points, and the bus connection points in the second connection end are different from the bus connection points in the first connection end; an intermediate wiring unit, configured to wire between the first connection end and the second connection end to obtain an intermediate wiring; and a wiring unit, configured to connect wiring between the corresponding bus connection point of the first connection end and the bus connection point of the second connection end according to the intermediate wiring; The wiring between the first connection end and the second connection end to obtain the intermediate wiring includes: Obtaining intermediate wiring parameters based on wiring parameters of the bus connection point in the first connection end and wiring parameters of the bus connection point in the second connection end; and routing according to the intermediate routing parameters to obtain the intermediate routing; The intermediate wiring parameters include intermediate line width parameters and intermediate hole parameters; The intermediate line width parameter is determined according to at least one of the number of corresponding bus connection points, minimum line width, minimum interval and topology mode; The intermediate hole parameters are divided into inflection intermediate hole parameters and same-direction intermediate hole parameters according to different topological modes. The inflection middle hole parameter is determined according to at least one of the middle line width parameter in the outgoing line direction, the wiring parameter of the bus connection point in the incoming line direction, the wiring parameter of the corresponding bus connection point, the number of corresponding bus connection points, and the minimum interval; The parameters of the same-direction intermediate holes are determined according to at least one of the wiring parameters of the corresponding bus connection points, the number of the corresponding bus connection points, and the minimum spacing; wherein, in the wiring area, obstacles are obtained; According to the intermediate wiring parameters and the obstacles, a prohibited wiring area is obtained. Wherein, wiring is prohibited in the prohibited wiring area.

8. A computing device comprising: processor; a memory for storing one or more programs, When the one or more programs are executed by the processor, the processor implements the bus wiring method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, wherein: When the program is executed by a processor, the bus wiring method according to any one of claims 1 to 6 is implemented.

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