Display substrate, preparation method thereof and display device

Abstract

A display substrate includes a substrate and a first active layer, a first functional layer, a second active layer, a second functional layer and an interlayer dielectric layer which are sequentially arranged on the substrate. The display substrate further includes a first via, a second via and a third via. The first via penetrates at least part of the second functional layer and at least part of the first functional layer and exposes part of the surface of the first active layer. The second via penetrates the interlayer dielectric layer and communicates with the first via. The third via penetrates the interlayer dielectric layer and at least part of the second functional layer and exposes part of the surface of the second active layer. In the display substrate, the first via is formed earlier than the interlayer dielectric layer and the third via is formed later than the interlayer dielectric layer. The aperture of the first via is smaller than the aperture of the second via and the aperture of the first via is smaller than the aperture of the third via.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate, a manufacturing method thereof, and a display device. BACKGROUND

[0002] An OLED (Organic Light Emitting Diode) display device is a display device made of an organic electroluminescent diode. The OLED display device has excellent characteristics such as no need for a backlight, high contrast, thin thickness, wide viewing angle, fast response speed, use in a flexible panel, wide temperature range of use, simple structure and process, and the like, and is widely used at present. SUMMARY

[0003] In one aspect, a display substrate is provided. The display substrate includes a substrate, and a first active layer, a first functional layer, a second active layer, a second functional layer, and an interlayer dielectric layer which are sequentially arranged on the substrate. The display substrate further includes a first via, a second via, and a third via. The first via penetrates at least part of the second functional layer and at least part of the first functional layer, and exposes a part of a surface of the first active layer. The second via penetrates the interlayer dielectric layer, and communicates with the first via. The third via penetrates the interlayer dielectric layer and at least part of the second functional layer, and exposes a part of a surface of the second active layer. The aperture of the first via is smaller than the aperture of the second via, and the aperture of the first via is smaller than the aperture of the third via.

[0004] In some embodiments, the display substrate has a display area and a non-display area. The display area includes a pixel circuit area, and the display substrate further includes a fifth recess and a first recess. The fifth recess penetrates at least part of the second functional layer and at least part of the first functional layer, and the fifth recess is located between two adjacent pixel circuit areas. The first recess penetrates at least part of the second functional layer and at least part of the first functional layer. The depth of the second via is less than or equal to the depth of the third via. The depth of the third via is less than the depth of the first via. The depth of the first via is less than the depth of the fifth recess. The depth of the fifth recess is equal to the depth of the first recess.

[0005] In another aspect, a method for manufacturing a display substrate is provided. The method includes providing a substrate. A first active layer, a first functional layer, a second active layer, and a second functional layer are sequentially formed on the substrate. A first via is formed through at least part of the second functional layer and at least part of the first functional layer, the first via exposing a part of a surface of the first active layer. An interlayer dielectric layer is formed on the second functional layer, a part of the interlayer dielectric layer filling the first via. The part of the interlayer dielectric layer filling the first via is removed, forming a second via in the interlayer dielectric layer in communication with the first via. A third via is formed through the interlayer dielectric layer and at least part of the second functional layer, the third via exposing a part of a surface of the second active layer.

[0006] In some embodiments, during the removing the part of the interlayer dielectric layer filling the first via and forming the second via in the interlayer dielectric layer in communication with the first via, the method further includes forming a fourth via through the interlayer dielectric layer, a footprint of the fourth via on the substrate being within a footprint of the second active layer on the substrate. The forming the third via through the interlayer dielectric layer and at least part of the second functional layer includes patterning the second functional layer through the fourth via to form a fifth via through at least part of the second functional layer. The third via includes the fourth via and the fifth via.

[0007] In some embodiments, the substrate has a display area and a non-display area, the non-display area including a bending area, the first active layer and the second active layer being located in the display area. Before the sequentially forming the first active layer, the first functional layer, the second active layer, and the second functional layer on the substrate, the method further includes forming an inorganic layer on the substrate. During the forming the first via through at least part of the second functional layer and at least part of the first functional layer, the method further includes forming a first recess through at least part of the second functional layer and the at least part of the first functional layer, the first recess being located in the bending area and exposing a part of a surface of the inorganic layer.

[0008] In some embodiments, the method further includes forming a first conductive film on the interlayer dielectric layer, the first conductive film covering a surface of the interlayer dielectric layer and being located in the first via, the second via, the third via, and the first recess. The first conductive film is patterned to retain a part of the first conductive film located in the first via and the second via to obtain a first conductive pattern, and to retain a part of the first conductive film located in the third via to obtain a second conductive pattern.

[0009] In some embodiments, the contact resistance of the first conductive pattern and the first active layer ranges from 969Ω to 1747Ω.

[0010] In some embodiments, the preparation method further comprises forming a passivation layer on the first conductive pattern and the second conductive pattern, a portion of the passivation layer being located in the first recess and in contact with the exposed portion of the inorganic layer. The passivation layer is patterned to remove at least the portion of the passivation layer located in the first recess.

[0011] In some embodiments, the preparation method further comprises patterning the inorganic layer through the first recess to form a second recess in communication with the first recess, the second recess exposing a portion of the substrate. A first planar layer is formed, a portion of the first planar layer filling the first recess and the second recess and being in contact with the exposed portion of the substrate.

[0012] In some embodiments, the non-display region further comprises a cutting region located on a side of the bending region away from the display region. In the process of forming the first recess penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the preparation method further comprises forming a third recess penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the third recess being located in the cutting region and exposing a portion of the inorganic layer.

[0013] In some embodiments, the preparation method further comprises patterning the inorganic layer through the third recess to form a fourth recess in communication with the third recess, the fourth recess exposing a portion of the substrate. A first planar layer is formed, a portion of the first planar layer filling the third recess and the fourth recess and being in contact with the exposed portion of the substrate.

[0014] In some embodiments, the step of forming the first functional layer comprises sequentially forming a first gate insulating layer, a first gate electrode, a second gate insulating layer, a second gate electrode, and a third gate insulating layer, a projection of the first gate electrode on the substrate partially overlapping a projection of the first active layer on the substrate, and a projection of the second gate electrode on the substrate partially overlapping a projection of the second active layer on the substrate. The step of forming the second functional layer comprises sequentially forming a fourth gate insulating layer, a third gate electrode, and a fifth gate insulating layer, a projection of the third gate electrode on the substrate partially overlapping a projection of the second active layer on the substrate.

[0015] In some embodiments, the substrate has a display area including a plurality of pixel circuit areas. In the process of forming the first via penetrating through at least part of the second functional layer and at least part of the first functional layer, the preparation method further includes: forming a fifth groove penetrating through at least part of the second functional layer and at least part of the first functional layer, the fifth groove being located between two adjacent pixel circuit areas. In the process of forming the interlayer dielectric layer on the second functional layer, the interlayer dielectric layer also fills the fifth groove.

[0016] In some embodiments, the forming the fifth groove penetrating through at least part of the second functional layer and at least part of the first functional layer includes: before the forming the first via penetrating through at least part of the second functional layer and at least part of the first functional layer, forming a sixth groove penetrating through at least part of the second functional layer and the third gate insulating layer, the sixth groove being located between two adjacent pixel circuit areas. In the process of forming the first via penetrating through at least part of the second functional layer and at least part of the first functional layer, a seventh groove penetrating through the second gate insulating layer and the first gate insulating layer and communicating with the sixth groove is formed through the sixth groove, and the fifth groove includes the sixth groove and the seventh groove.

[0017] In some embodiments, the fourth gate insulating layer has a projection on the substrate that overlaps a projection of the third gate electrode on the substrate.

[0018] In some embodiments, the material of the first active layer includes polysilicon, and the material of the second active layer includes metal oxide.

[0019] In another aspect, a display device is provided. The display device includes a display substrate as described in any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, etc. of the product related to the embodiments of the present disclosure.

[0021] Figure 1 is a sectional view of a display substrate to be formed in an implementation;

[0022] Figure 2 is a sectional view of another display substrate to be formed in an implementation;

[0023] Figure 3 A flow chart of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0024] Figures 4a to 4o A manufacturing step diagram of a display substrate according to some embodiments of the present disclosure;

[0025] Figure 5 A Figure 4g A partial enlarged view of the X region;

[0026] Figure 6a A principle diagram of water vapor release in a substrate in an implementation;

[0027] Figure 6b An optical detection diagram of a structure of a first conductive film formation in an implementation;

[0028] Figure 6c An optical detection diagram of another structure of a first conductive film formation in an implementation;

[0029] Figure 6d An optical detection diagram of a first conductive pattern and a second conductive pattern formed according to some embodiments of the present disclosure;

[0030] Figure 7 A sectional view of yet another display substrate to be formed in an implementation;

[0031] Figures 8a to 8d A top view of a display substrate to be formed according to some embodiments of the present disclosure;

[0032] Figure 9 A structure diagram of a display substrate according to some embodiments of the present disclosure;

[0033] Figure 10 A circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0034] Figure 11 A structure diagram of another display substrate according to some embodiments of the present disclosure;

[0035] Figure 12 A structure diagram of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present disclosure.

[0037] Unless otherwise required by context, as used herein and throughout this specification, the term "comprise" and variations of the term, such as "comprises" and "comprising," will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps. In describing some embodiments, it will be understood that terms such as "first", "second", "third", etc., are used only to describe one implementation and do not imply an order or a sequence unless otherwise required by context. Similarly, terms such as "top", "bottom", "front", "back", "leading", "trailing", etc., are used only on a relative basis to describe one implementation and do not imply an absolute

[0038] Hereinafter, the terms "first", "second", etc., are used only for the purpose of description and are not to be interpreted as implying relative importance or a specified number thereof. Thus, the features defined with "first", "second" can include one or more of the features explicitly or implicitly. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0039] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. For example, these terms can be used to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, these terms can be used to mean that two or more elements are not in direct contact with each other, but yet can still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited in terms of the particular examples described herein.

[0040] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0041] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0042] The use of "configured to" herein means open and inclusive language that does not exclude additional devices or steps not mentioned.

[0043] Additionally, the use of "based on" means open and inclusive language that does not exclude additional conditions or values not mentioned.

[0044] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0045] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layers of elements of the devices are shown in the drawings. Thus, the drawings represent examples of the devices as described herein. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0046] In one implementation, during the preparation of the display substrate, see Figure 1 , the first active layer 2', the first functional layer 3', the second active layer 4', and the second functional layer 5' are sequentially formed on the substrate 1' in order, wherein the material of the second active layer 4' includes metal oxide; and then the first connecting hole 6' exposing the first active layer 2' and the second connecting hole 7' exposing the second active layer 4' are synchronously formed at the corresponding positions of the second functional layer 5'. Figure 2Then, an interlayer dielectric layer 8' is formed on the second functional layer 5', and the interlayer dielectric layer 8' is located in regions other than the first connecting hole 6' and the second connecting hole 7'. During the formation of the interlayer dielectric layer 8', the material of the interlayer dielectric layer 8' is located in the first connecting hole 6' and the second connecting hole 7', and thus the material of the interlayer dielectric layer 8' located in the first connecting hole 6' and the second connecting hole 7' needs to be removed to obtain the interlayer dielectric layer 8'. This easily causes the material of the interlayer dielectric layer 8' to remain on the first active layer 2' in the first connecting hole 6', and the cleaning agent that can remove the material of the interlayer dielectric layer 8' will corrode the exposed second active layer 4', which will result in the material of the interlayer dielectric layer 8' remaining on the first active layer 2' being unable to be effectively removed. Therefore, after the source and the drain are respectively formed in the first connecting hole 6' to form the transistor, the above-mentioned remaining material of the interlayer dielectric layer 8' will cause the contact resistance between the source and the first active layer 2' and the contact resistance between the drain and the first active layer 2' to increase, which will affect the electrical characteristics of the formed transistor and affect the display effect of the display substrate.

[0047] Based on this, some embodiments of the present disclosure provide a preparation method of a display substrate, as shown in the following Figure 3 The preparation method comprises S100-S600.

[0048] S100, as shown in the following Figure 4a The substrate 1 is provided.

[0049] Exemplarily, the structure and material of the substrate 1 include various structures and materials, which can be selected and arranged according to actual needs.

[0050] Exemplarily, the substrate 1 can be a single-layer structure.

[0051] For example, the substrate 1 can be a rigid substrate. The rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate. In this case, the above-mentioned display substrate 100 can be a rigid display substrate.

[0052] For another example, the substrate 1 can be a flexible substrate. The flexible substrate can be, for example, a PET (Polyethyleneterephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate or a PI (Polyimide) substrate. In this case, the above-mentioned display substrate 100 can be a flexible display substrate.

[0053] Exemplarily, the substrate 1 can be a multi-layer structure, i.e., the substrate 1 comprises a plurality of sub-film layers, and the material of each sub-film layer can be the same or different.

[0054] For example, referring to Figure 4a The substrate 1 comprises three sub-film layers stacked in sequence, and the materials of the three sub-film layers of the substrate 1 can comprise, in sequence, polyimide (PI), silicon oxide (SiO), and polyimide (PI).

[0055] The drawings of the present disclosure illustrate the substrate 1 as a three-layer structure, i.e., the substrate 1 comprises three sub-film layers stacked in sequence.

[0056] S200, referring to Figure 4b The first active layer 2, the first functional layer 3, the second active layer 4, and the second functional layer 5 are sequentially formed on the substrate 1.

[0057] Exemplarily, in S200, the step of forming the first active layer 2 on the substrate 1 can comprise: forming a first active thin film on the substrate 1, and patterning the first active thin film by a patterning process to form the first active layer 2.

[0058] Exemplarily, the patterning process can comprise plasma etching, photolithography, etc.

[0059] Exemplarily, the number of the formed first active layer 2 is a plurality. The specific number of the first active layer 2 can be determined according to the number of transistors to be formed, and the present disclosure does not limit the number.

[0060] In some examples, the material of the first active layer 2 comprises polysilicon.

[0061] It can be understood that the transistor containing polysilicon has the characteristic of high mobility. This is conducive to improving the mobility of the transistor prepared and formed by the present disclosure.

[0062] Exemplarily, the first functional layer 3 comprises a plurality of sub-film layers with different functions, and the present disclosure does not limit the number.

[0063] Exemplarily, the first functional layer 3 comprises a first gate insulating layer 6, a first gate 7, a second gate insulating layer 8, a second gate 9, and a third gate insulating layer 10 stacked in sequence in a direction away from the substrate 1.

[0064] In some examples, referring to Figure 4b In the above S200, the method of forming the first functional layer 3 comprises S210.

[0065] S210, sequentially forming a first gate insulating layer 6, a first gate 7, a second gate insulating layer 8, a second gate 9 and a third gate insulating layer 10. The first gate 7 has a projection on the substrate 1 partially overlapping a projection of the first active layer 2 on the substrate 1. The second gate 9 has a projection on the substrate 1 partially overlapping a projection of the second active layer 4 on the substrate 1.

[0066] Exemplarily, the first gate insulating layer 6 is made of inorganic material. For example, the material of the first gate insulating layer 6 includes at least one of silicon oxide (SiO), silicon nitride (SiN) and silicon oxynitride (SiON). The first gate insulating layer 6 can provide insulation protection between the first active layer 2 and the first gate 26.

[0067] Exemplarily, the method of forming the first gate insulating layer 6 includes a deposition process.

[0068] Optionally, the present disclosure can use a method such as PVD (Physical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) to deposit the first gate insulating layer 6 with a certain thickness on the side of the first active layer 2 away from the substrate 1.

[0069] Exemplarily, the material of the first gate 7 is conductive material. For example, the material of the first gate 7 includes metal or alloy such as molybdenum (Mo), aluminum (AL) and copper (Cu). The method of forming the first gate 7 includes forming a first gate conductive film on the side of the first gate insulating layer 6 away from the substrate 1, and then using a photolithography process to pattern the first gate conductive film to obtain the first gate 7.

[0070] Exemplarily, the method of patterning the first gate conductive film using a photolithography process includes coating photoresist on the first gate conductive film, then setting a mask plate on the side of the photoresist away from the substrate 1, exposing and developing the photoresist through the mask plate, removing the exposed part of the photoresist and retaining the part of the photoresist not exposed, thereby forming the patterned photoresist; then etching the first gate conductive film with the patterned photoresist as a mask to remove the part of the first gate conductive film not shielded by the patterned photoresist, thereby forming the first gate 7. Finally, the display substrate to be formed can be placed in a stripping solution to dissolve and strip off the patterned photoresist.

[0071] Exemplarily, the material of the second gate insulating layer 8 is inorganic material. For example, the material of the second gate insulating layer 8 includes at least one of silicon nitride (SiN), silicon oxide (SiO) and silicon oxynitride (SiON). The second gate insulating layer 8 can provide insulation protection between the first gate 7 and the second gate 9.

[0072] Exemplarily, the method of forming the second gate insulating layer 8 comprises a deposition process.

[0073] Optionally, the method of forming the second gate insulating layer 8 can refer to the method of forming the first gate insulating layer 6, which will not be repeated here.

[0074] Exemplarily, the material of the second gate 9 is a conductive material. For example, the material of the second gate 9 comprises a metal or an alloy such as molybdenum (Mo), aluminum (AL), copper (Cu), etc. The method of forming the second gate 9 can comprise: forming a second gate conductive film on the side of the second gate insulating layer 8 away from the substrate 1, and then patterning the second gate conductive film by using a photolithography process to obtain the second gate 9.

[0075] Exemplarily, the material of the third gate insulating layer 10 comprises an inorganic material. For example, the material of the third gate insulating layer 10 comprises at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The third gate insulating layer 10 can provide insulation protection between the second gate 9 and the second active layer 4.

[0076] Exemplarily, the method of forming the third gate insulating layer 10 comprises a deposition process.

[0077] Optionally, the method of forming the third gate insulating layer 10 can refer to the method of forming the first gate insulating layer 6, which will not be repeated here.

[0078] Exemplarily, by setting the orthogonal projection of the first gate 7 on the substrate 1 to partially overlap with the orthogonal projection of the first active layer 2 on the substrate 1, it is beneficial to realize the control of the transistor comprising the first active layer 2 by the first gate 7.

[0079] It can be understood that after patterning the first gate conductive film, a plurality of first plates can be obtained synchronously. After patterning the second gate conductive film, a plurality of second plates can be obtained synchronously. For example, one first plate and one second plate are arranged oppositely to constitute a storage capacitor Cst.

[0080] In addition, after patterning any one of the first gate conductive film and the second gate conductive film, a plurality of signal lines can also be obtained synchronously. The plurality of signal lines, for example, comprise at least one of the first gate line GateP, the second gate line GateN, the enable signal line EM and the reset signal line ResetN, and the initial signal line.

[0081] For example, in the case that the first gate conductive film forms the first gate line GateP, the first gate line GateP has an overlap with the first active layer 2, and the overlapped part forms the first gate electrode 7, for example. In the case that the first gate conductive film forms the enable signal line EM, the enable signal line EM has an overlap with the first active layer 2, and the overlapped part also forms the first gate electrode 7, for example. In the case that the second gate conductive film forms the second gate line GateN, the second gate line GateN has an overlap with the second active layer 4, and the overlapped part forms the second gate electrode 9, for example. In the case that the second gate conductive film forms the reset signal line ResetN, the reset signal line ResetN has an overlap with the second active layer 4, and the overlapped part forms the second gate electrode 9, for example.

[0082] The first gate line GateP, the second gate line GateN, the enable signal line EM and the reset signal line ResetN will be described below, and thus will not be described here.

[0083] For example, in the step S200, the step of forming the second active layer 4 can include: forming a second active layer film on the first functional layer 3, and patterning the second active layer film by a patterning process to form the second active layer 4.

[0084] For example, the patterning process can include plasma etching, photolithography, etc.

[0085] For example, the number of the second active layer 4 can be multiple. The specific number of the second active layer 4 can be determined according to the number of transistors to be formed, and the present disclosure does not limit the number of the second active layer 4.

[0086] In some examples, the material of the second active layer 4 includes metal oxide. For example, the material of the second active layer 4 includes indium gallium zinc oxide (IGZO).

[0087] It can be understood that the transistor containing metal oxide has the characteristic of low leakage current. This is conducive to reducing the leakage current of the transistor prepared by the present disclosure.

[0088] For example, the second functional layer 5 includes multiple sub-film layers with different functions, and the present disclosure does not limit the number and material of the sub-film layers.

[0089] For example, referring to Figure 4b , the second functional layer 5 includes a fourth gate insulating layer 11, a third gate electrode 12 and a fifth gate insulating layer 13 which are sequentially stacked.

[0090] In some examples, referring to Figure 4b In the step S200, the method of forming the second functional layer 5 includes: S220.

[0091] S220, a fourth gate insulating layer 11, a third gate 12 and a fifth gate insulating layer 13 are formed in sequence, and the orthogonal projection of the third gate 12 on the substrate 1 overlaps with the orthogonal projection of the second active layer 4 on the substrate 1.

[0092] For example, the material of the fourth gate insulating layer 11 is an inorganic material. For instance, the material of the fourth gate insulating layer 11 includes at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The fourth gate insulating layer 11 can provide insulating protection between the third gate 12 and the second active layer 4.

[0093] For example, the method of forming the fourth gate insulating layer 11 includes a deposition process and a photolithography process.

[0094] For example, the material of the third gate 12 is a metallic conductive material. For example, the material of the third gate 12 includes molybdenum (Mo) and titanium nitride (TiN) stacked sequentially. The method of forming the third gate 12 may include: forming a third gate conductive film including the third gate 12 on the side of the fourth gate insulating layer 11, the second active layer 4 and the third insulating layer 10 away from the substrate 1, and then patterning the third gate conductive film to obtain the third gate 12.

[0095] For example, a method for patterning the third gate conductive film includes a photolithography process.

[0096] It is understandable that multiple signal lines can be obtained after patterning the third gate conductive film. These multiple signal lines may include, for example, at least one of the second gate line GateN and the reset signal line ResetN.

[0097] In the case where the second gate line GateN is obtained from the third gate conductive film, the second gate line GateN overlaps with the second active layer 4, and the overlapping portion constitutes, for example, the third gate 12. In the case where the reset signal line ResetN is obtained from the third gate conductive film, the reset signal line ResetN overlaps with the second active layer 4, and the overlapping portion constitutes, for example, the third gate 12.

[0098] For example, the second gate line GateN obtained from the second gate conductive film and the second gate line GateN obtained from the third gate conductive film partially overlap, and the reset signal line ResetN obtained from the second gate conductive film and the reset signal line ResetN obtained from the third gate conductive film partially overlap.

[0099] Furthermore, after patterning the third gate conductive film, a first initial signal line Vinit1 or a second initial signal line Vinit2 can also be obtained. For details regarding the first initial signal line Vinit1 or the second initial signal line Vinit2, please refer to the explanation below; it will not be repeated here.

[0100] In some examples, the fourth gate insulating layer 11 is provided as a whole layer, and the orthogonal projection of the fourth gate insulating layer 11 on the substrate 1 is not identical to the orthogonal projection of the third gate 12 on the substrate 1. Therefore, after the fourth gate insulating layer 11 and the third gate conductive thin film are formed, the third gate conductive thin film needs to be patterned to form the third gate 12.

[0101] In other examples, referring to Figure 4c , the fourth gate insulating layer 11 is not provided as a whole layer, and the orthogonal projection of the fourth gate insulating layer 11 on the substrate 1 is identical to the orthogonal projection of the third gate 12 on the substrate 1.

[0102] Exemplarily, after the thin film containing the fourth gate insulating layer 11 and the third gate conductive thin film are formed, the thin film containing the fourth gate insulating layer 11 and the third gate conductive thin film can be patterned synchronously to obtain the fourth gate insulating layer 11 and the third gate 12, and make the orthogonal projection of the fourth gate insulating layer 11 on the substrate 1 identical to the orthogonal projection of the third gate 12 on the substrate 1. In this way, on the basis of guaranteeing the insulation protection function of the fourth gate insulating layer 11, the number of film layers of the display substrate in the area outside the third gate 12 can be reduced, and the thickness of the display substrate can be reduced to a certain extent.

[0103] Exemplarily, the material of the fifth gate insulating layer 13 includes inorganic material. For example, the material of the fifth gate insulating layer 13 includes at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The fifth gate insulating layer 13 can provide insulation protection for the third gate 12 and the second active layer 4.

[0104] Exemplarily, the method for forming the fifth gate insulating layer 13 includes a deposition process.

[0105] Optionally, the method for forming the fifth gate insulating layer 13 can refer to the method for forming the first gate insulating layer 6 described above, which will not be described herein again.

[0106] Exemplarily, by setting the orthogonal projection of the second gate 9 on the substrate 1 to partially overlap with the orthogonal projection of the second active layer 4 on the substrate 1, and by setting the orthogonal projection of the third gate 12 on the substrate 1 to partially overlap with the orthogonal projection of the second active layer 4 on the substrate 1, a transistor with a top-bottom gate structure can be obtained. Moreover, it is beneficial to realize the control of the second gate 9 and the third gate 12 on the transistor containing the second active layer 4.

[0107] Exemplarily, the orthographic projection of the first active layer 2 on the substrate 1 and the orthographic projection of the second active layer 4 on the substrate 1 do not overlap, that is, in the direction perpendicular to the substrate 1, the first active layer 2 and the second active layer 4 have no overlapping part. In this way, in the subsequent step of forming the via hole on the first active layer 2 and the second active layer 4, the second active layer 4 can be avoided from interfering with the via hole.

[0108] S300, referring to Figure 4d forming a first via hole 14 penetrating at least part of the second functional layer 5 and at least part of the first functional layer 3, the first via hole 14 exposing part of the surface of the first active layer 2.

[0109] Exemplarily, the first functional layer 3 and the second functional layer 5 can be etched by a photolithography process to form the first via hole 14.

[0110] It should be noted that, referring to Figure 4d The first via hole 14 can penetrate the first gate insulating layer 6, the second gate insulating layer 8 and the third gate insulating layer 10 of at least part of the first functional layer 3, and the fifth gate insulating layer 13 of the second functional layer 5.

[0111] By exposing part of the surface of the first active layer 2 by the first via hole 14, the source and the drain of the transistor can be respectively formed in each first via hole 14 in the later stage, and the source and the drain are respectively in contact with part of the surface of the first active layer 2 to form an electrical connection.

[0112] Exemplarily, the number of the first via hole 14 is correspondingly arranged with the number of the first active layer 2.

[0113] Optionally, the number of the first via hole 14 is twice, three times or four times of the number of the first active layer 2. For example, the number of the first active layer 2 is two, and the number of the first via hole 14 is four, six or eight. For another example, the number of the first active layer 2 is six, and the number of the first via hole 14 is twelve, eighteen or twenty-four.

[0114] S400, referring to Figure 4e forming an interlayer dielectric layer 15 on the second functional layer 5, part of the interlayer dielectric layer 15 filling the first via hole 14.

[0115] Exemplarily, the material of the interlayer dielectric layer 15 includes an organic material. For example, the material of the interlayer dielectric layer 15 includes polyimide (PI).

[0116] Exemplarily, the method of forming the interlayer dielectric layer 15 includes a coating process.

[0117] It should be noted that the organic material has fluidity, and thus, in the process of forming the interlayer medium layer 15 on the second functional layer 5, a portion of the interlayer medium layer 15 will fill the first via hole 14, and the upper surface of the interlayer medium layer 15 is a flat surface.

[0118] S500, refer to Figure 4f-1 and Figure 4f-2 , remove the portion of the interlayer medium layer 15 that fills the first via hole 14, and form a second via hole 16 in the interlayer medium layer 15 that communicates with the first via hole 14.

[0119] For example, the method of removing the portion of the interlayer medium layer 15 that fills the first via hole 14, and forming the second via hole 16 in the interlayer medium layer 15 that communicates with the first via hole 14 can include a photolithography process.

[0120] Further, the removal of the portion of the interlayer medium layer 15 that fills the first via hole 14, and the formation of the second via hole 16 in the interlayer medium layer 15 that communicates with the first via hole 14 can be formed in one process, which can simplify the manufacturing process of the display substrate 100.

[0121] For example, the aperture of the second via hole 16 is larger than the aperture of the first via hole 14. The aperture here refers to, for example, the average aperture of the via hole, or the aperture of the via hole away from the substrate 1 end.

[0122] By making the first via hole 14 communicate with the second via hole 16, a portion of the surface of the first active layer 2 is exposed, which facilitates the formation of the source and drain of the transistor in the first via hole 14 and the second via hole 16 later, and makes the first active layer 2 and the source and drain formed in the first via hole 14 and the second via hole 16 contact each other to form an electrical connection.

[0123] It should be noted that after S500, in combination with Figure 4e , Figure 4f-1 and Figure 4f-2 , the portion of the surface of the first active layer 2 exposed through the first via hole 14 and the second via hole 16 can have residual material of the interlayer medium layer 15, so that the display substrate can be cleaned using a cleaning agent to remove the residual material of the interlayer medium layer 15 on the portion of the surface of the first active layer 2 exposed, and thus, after the formation of the source and drain of the transistor on the first active layer 2, the contact resistance between the source of the transistor and the first active layer 2 can be reduced, the contact resistance between the drain of the transistor and the first active layer 2 can be reduced, and the electrical properties of the transistor containing the first active layer 2 formed finally can be avoided from being affected, and the display effect of the display substrate can be improved.

[0124] S600, refer to Figure 4gThe third via hole 17 exposes part of the surface of the second active layer 4.

[0125] The method of forming the third via hole 17 through the interlayer dielectric layer 15 and at least part of the second functional layer 5 includes a photolithography process.

[0126] It should be noted that, referring to Figure 4g The third via hole 17 penetrates the fifth gate insulating layer 13 in at least part of the second functional layer 5.

[0127] The aperture of the first via hole 14 is smaller than the aperture of the third via hole 17.

[0128] By exposing part of the surface of the second active layer 4 through the third via hole 17, the source and the drain of the transistor can be formed in the third via hole 17 in the subsequent step, and the source and the drain are in contact with part of the surface of the second active layer 4 to form an electrical connection.

[0129] Since the third via hole 17 is formed after the first via hole 14 and the second via hole 16, referring to Figure 4g In the process of removing the material of the interlayer dielectric layer 15 remaining on part of the surface of the first active layer 2 through the first via hole 14 and the second via hole 16 by using a cleaning agent, the second functional layer 5 on the second active layer 4 can protect the second active layer 4 from being exposed to the cleaning agent to cause corrosion.

[0130] Therefore, the preparation method of the display substrate provided by some embodiments of the present disclosure can form the first via hole 14 through at least part of the second functional layer 5 and at least part of the first functional layer 3 and exposing part of the surface of the first active layer 2 first, then form the interlayer dielectric layer 15 on the second functional layer 5, and then form the third via hole 17 through the interlayer dielectric layer 15 and at least part of the second functional layer 5. In this way, the display substrate can be cleaned by using a cleaning agent to remove the material of the interlayer dielectric layer 15 remaining on part of the surface of the first active layer 2 before forming the third via hole 17. In this way, not only can the second functional layer 5 protect the second active layer 4 from being exposed to the cleaning agent to cause corrosion, but also can avoid increasing the contact resistance between the source and the first active layer 2 and the contact resistance between the drain and the first active layer 2 after forming the source and the drain on the first active layer 2, so as to avoid affecting the electrical properties of the finally formed transistor and the display effect of the display substrate.

[0131] The inventors of this disclosure have verified the fabrication method of the display substrate disclosed herein. The verification method includes: ① fabricating a display substrate using the fabrication method of this disclosure, and testing the electrical characteristics of the transistor (taking a driving transistor as an example) formed in the display substrate containing a first active layer 2. ② fabricating a display substrate using one of the implementation methods mentioned above, and testing the electrical characteristics of the transistor (taking a driving transistor as an example) formed in the display substrate containing a first active layer 2'. The aspect ratio of the channel of the thin-film transistor formed in both fabrication methods is, for example, 3 / 23.

[0132] Table 1

[0133]

[0134] Referring to Table 1 above, the standard requirement for mobility in the electrical characteristic standards of transistors is 80 cm⁻¹. 2 / Vs~130cm 2 / Vs, the standard requirement for the contact resistance of a transistor (i.e., the contact resistance between the active layer and the source of the transistor, and the contact resistance between the active layer and the drain of the transistor) is less than 2000Ω.

[0135] In the display substrate fabricated using one of the implementation methods mentioned above, the transistor mobility is 5 cm⁻¹. 2 / Vs, compared to the standard requirement for mobility (80cm) 2 / Vs~130cm 2 Compared to the standard requirement of 603662Ω ( / Vs), the transistor's mobility does not meet the standard. The contact resistance of the transistor is also below the standard requirement (<2000Ω), meaning it does not meet the standard.

[0136] In the display substrate prepared using the method disclosed herein, the transistor mobility is 135 cm⁻¹. 2 / Vs, compared to the standard requirement for mobility (80cm) 2 / Vs~130cm 2 Compared to the standard requirement for mobility ( / Vs), the mobility of the transistor in this disclosure is within the standard requirement range, meaning that the mobility of the transistor in this disclosure basically meets the standard. The contact resistance of the transistor is 1358±389Ω, which is within the standard requirement range for contact resistance (<2000Ω), meaning that the contact resistance of the transistor in this disclosure meets the standard.

[0137] Therefore, it can be proved that the preparation method of the display substrate can effectively increase the mobility of the transistor formed, and effectively reduce the contact resistance between the active layer and the source electrode in the transistor, and the contact resistance between the active layer and the drain electrode in the transistor.

[0138] In some embodiments, in combination with Figure 4e 、 Figure 4f-1 and Figure 4f-2 , in the above S500, in the process of removing the part of the interlayer dielectric layer 15 filling the first via hole 14 and forming the second via hole 16 communicating with the first via hole 14 in the interlayer dielectric layer 15, the preparation method of the display substrate further comprises: S510.

[0139] S510, forming a fourth via hole 18 penetrating the interlayer dielectric layer 15. The orthographic projection of the fourth via hole 18 on the substrate 1 is located in the orthographic projection range of the second active layer 4 on the substrate 1.

[0140] Exemplarily, the fourth via hole 18 can be formed by etching the interlayer dielectric layer 15 by using a photolithography process.

[0141] By locating the orthographic projection of the fourth via hole 18 on the substrate 1 in the orthographic projection range of the second active layer 4 on the substrate 1, it is convenient to form the fifth via hole 19 penetrating at least part of the second functional layer 5 through the fourth via hole 18 later.

[0142] Exemplarily, the number of the fourth via hole 18 corresponds to the number of the second active layer 4.

[0143] Optionally, the number of the fourth via hole 18 is twice the number of the second active layer 4. For example, the number of the second active layer 4 is two, and the number of the fourth via hole 18 is four. For another example, the number of the second active layer 4 is six, and the number of the fourth via hole 18 is twelve.

[0144] At this time, in the above S600, in combination with Figure 4g and Figure 5 , the step of forming the third via hole 17 penetrating the interlayer dielectric layer 15 and at least part of the second functional layer 5 comprises: S610.

[0145] S610, see Figure 5 , the second functional layer 5 is patterned through the fourth via hole 18 to form the fifth via hole 19 penetrating at least part of the second functional layer 5. The third via hole 17 comprises the fourth via hole 18 and the fifth via hole 19.

[0146] Exemplarily, the process of forming the fourth via hole 18 penetrating the interlayer dielectric layer 15 can comprise a photolithography process.

[0147] By forming the fourth via 18 penetrating the interlayer dielectric layer 15, the film layer thickness of the display substrate at the fourth via 18 can be reduced, which is beneficial for the film layer thickness to be etched when the second functional layer 5 is patterned through the fourth via 18 later.

[0148] In combination Figure 4e and Figure 5 , the second functional layer 5 is patterned through the fourth via 18 penetrating the interlayer dielectric layer 15, and the fifth via 19 penetrating at least part of the second functional layer 5 is formed, so that the fourth via 18 and the fifth via 19 are in communication with each other, thereby forming the third via 17 including the fourth via 18 and the fifth via 19 to expose part of the surface of the second active layer 4, which is beneficial for the first conductive film to be formed in the third via 17 in the subsequent process and coupled with part of the surface of the second active layer 4.

[0149] For example, the method of patterning the second functional layer 5 includes a photolithography process. The aperture of the fourth via 18 is greater than the aperture of the fifth via 19, for example.

[0150] In other examples, in combination Figure 4e and Figure 4f-1 , the fourth via 18 can also not be formed during the process of removing the part of the interlayer dielectric layer 15 filled with the first via 14. At this time, in the process of forming the third via 17 penetrating the interlayer dielectric layer 15 and at least part of the second functional layer 5 in S600, the interlayer dielectric layer 15 and the second functional layer 5 need to be etched at the same time.

[0151] In some examples, referring to Figure 4b Before the first active layer 2, the first functional layer 3, the second active layer 4 and the second functional layer 5 are sequentially formed on the substrate 1, the method for manufacturing the display substrate further includes: forming an inorganic layer 20 on the substrate 1. The first active layer 2 is formed on the inorganic layer 20.

[0152] For example, the inorganic layer 20 includes a barrier layer 21 and a first buffer layer 22. The inorganic layer 20 is used to protect the display substrate.

[0153] For example, the method of forming the inorganic layer 20 can include: sequentially forming the barrier layer 21 and the first buffer layer 22 on the substrate 1.

[0154] For example, the materials of the barrier layer 21 and the first buffer layer 22 are both inorganic materials.

[0155] Exemplarily, the structure of the barrier layer 21 can be a single-layer structure, and the material of the barrier layer 21 can include silicon oxide (SiO), for example.

[0156] Exemplarily, in the process of sequentially forming the barrier layer 21 and the first buffer layer 22 on the substrate 1, the preparation method of the display substrate further includes: forming a light-blocking layer 23 between the barrier layer 21 and the first buffer layer 22. The orthographic projection of the first active layer 2 on the substrate 1 is located in the range of the orthographic projection of the light-blocking layer 23 on the substrate 1.

[0157] Exemplarily, the light-blocking layer 23 is used to block the light rays from the side of the display substrate close to the substrate 1 to the display substrate. The material of the light-blocking layer 23 can include metal or black organic material, for example.

[0158] It can be understood that the electrical properties of the first active layer 2 are greatly affected by the light rays. By setting the orthographic projection of the first active layer 2 on the substrate 1 in the range of the orthographic projection of the light-blocking layer 23 on the substrate 1, the light rays from the side of the substrate 1 away from the first active layer to the first active layer can be blocked by the light-blocking layer 23, so as to avoid the influence of the above-mentioned light rays on the electrical properties of the first active layer 2.

[0159] In some embodiments, referring to Figure 4b , the substrate 1 has a display area A and a non-display area B, the non-display area includes a bending area (also referred to as a Pad Bending area) B1, and the first active layer 2 and the second active layer 4 are located in the display area A.

[0160] Exemplarily, the display area A is an area for displaying images. The non-display area B is an area other than the display area A.

[0161] The bending area B1 is an area that can be bent in the display substrate prepared and formed. By bending the display substrate in the bending area, a part of the display substrate can be bent to the side of the display substrate close to the substrate 1. In this way, in the plane where the display substrate is located, the space occupied by the display substrate can be reduced.

[0162] In some examples, in the process of forming the first via hole 14 penetrating through at least part of the second functional layer 5 and at least part of the first functional layer 3 in the above S300, the preparation method of the display substrate further includes: S310a.

[0163] S310a, referring to Figure 4d , a first recess 24 penetrating through at least part of the second functional layer 5 and at least part of the first functional layer 3 is formed, and the first recess 24 is located in the bending area and exposes part of the surface of the inorganic layer 20.

[0164] For example, referring to Figure 4c and Figure 4d , the portions of the first functional layer 3 and the second functional layer 5 located in the first via hole 14 need to be removed in the process of forming the first via hole 14, and the portions of the first functional layer 3 and the second functional layer 5 located in the first groove 24 need to be removed in the process of forming the first groove 24, and the film layers removed by the two are the same. By forming the first groove 24 in the process of forming the first via hole 14, the first via hole 14 and the first groove 24 can be formed in one patterning process, thereby simplifying the preparation process of the display substrate 100.

[0165] Further, by forming the first groove 24, the thickness of the display substrate located in the bending area B1 can be reduced, which is beneficial to the subsequent step of continuously removing the portion of the inorganic layer 20 located in the bending area B1.

[0166] It can be understood that after the display substrate forms the first groove 24, in the process of forming the interlayer dielectric layer 15 on the second functional layer 5 in the above S400, in combination with Figure 4d and Figure 4e , a part of the interlayer dielectric layer 15 will also be filled in the first groove 24. In the subsequent S500, referring to Figure 4f-1 and Figure 4f-2 , in the process of removing the portion of the interlayer dielectric layer 15 filled in the first via hole 14, the portion of the interlayer dielectric layer 15 filled in the first groove 24 will also be removed synchronously.

[0167] In some embodiments, the preparation method of the display substrate further includes S700-S800.

[0168] S700, referring to Figure 4h , forming a first conductive film 25 on the interlayer dielectric layer 15, the first conductive film 25 covers the surface of the interlayer dielectric layer 15 and is located in the first via hole 14, the second via hole 16, the third via hole 17 and the first groove 24.

[0169] S800, in combination with Figure 4h and Figure 4i , patterning the first conductive film 25, retaining the portion of the first conductive film 25 located in the first via hole 14 and the second via hole 16 to obtain a first conductive pattern 26, and retaining the portion of the first conductive film 25 located in the third via hole 17 to obtain a second conductive pattern 27.

[0170] For example, the material of the first conductive film 25 may, for example, include titanium (Ti), aluminum (Al), and titanium (Ti) which are sequentially stacked.

[0171] For example, the process of forming the first conductive film 25 on the interlayer dielectric layer 15 may, for example, include a metal sputtering process.

[0172] It should be noted that the metal sputtering process is a process in which high-energy particles (ions or neutral atoms, molecules) bombard the surface of a metal target, so that the atoms or molecules near the surface of the metal target obtain sufficient energy and finally escape from the surface of the metal target. Sputtering can only be carried out in a certain vacuum state.

[0173] Referring to Figure 4h , by placing the display substrate to be formed in the sputtering chamber, the material of the first conductive film 25 is formed on the interlayer dielectric layer 15 and in the first via hole 14, the second via hole 16, the third via hole 17 and the first groove 24 by the sputtering process.

[0174] Exemplarily, the method of patterning the first conductive film 25 includes a photolithography process.

[0175] It should be noted that in combination with Figure 4g , Figure 4h and Figure 4i , the first conductive pattern 26 is in contact with the first active layer 2, and different first conductive patterns 26 respectively constitute the source and drain of a transistor.

[0176] The second conductive pattern 27 is in contact with the second active layer 4, and different second conductive patterns 27 respectively constitute the source and drain of a transistor.

[0177] In an implementation manner, referring to Figure 1 , in the process of forming the first connection hole 6' exposing the first active layer 2' and the second connection hole 7' exposing the second active layer 4' at the corresponding positions of the second insulating layer 5', a bending groove 9' located in the bending area B1' is formed. The bending groove 9' penetrates the second insulating layer 5' and the first insulating layer 3', and exposes part of the surface of the substrate 1'. The material of the substrate 1' includes polyimide (PI), and the substrate 1' is easy to absorb water vapor in the process of manufacturing the display substrate.

[0178] Therefore, in combination with Figure 2 and Figure 6a , the water vapor absorbed by the substrate 1' is easy to diffuse into the sputtering chamber in the process of forming the first conductive film 10' on the interlayer dielectric layer 8' by the sputtering process, and the water vapor released will affect the bombardment and deposition of high-energy particles on the metal target in the sputtering process, referring to Figure 6b , resulting in the formation of small protrusions on the finally formed first conductive film 10', affecting the film forming quality of the finally formed first conductive film 10', and finally affecting the quality of the structure obtained by etching the first conductive film 10'. Referring to Figure 6b and Figure 6cBecause there are too many small protrusions in the structure etched by the first conductive film 10', the structure etched by the first conductive film 10' presents a plurality of "small black spots" in optical detection.

[0179] To solve the above problem, in a related solution, before forming the first conductive film 10' on the surface of the second insulating layer 5', the display substrate to be formed is preheated in a chemical vapor deposition (CVD) chamber. The preheating condition is that the preheating temperature is 150°C and the preheating time is 30 minutes. The purpose of preheating is to remove the absorbed water vapor in the substrate 1'. However, this solution needs to increase the preparation process of the display substrate, and will increase the preparation time of the display substrate, and also will increase the preparation cost of the display substrate.

[0180] In the present disclosure, referring to Figure 4f-1 , Figure 4f-2 and Figure 4g , before forming the first conductive film 25 by the sputtering process, the first groove 24 located in the bending area B1 only penetrates at least part of the second functional layer 5 and at least part of the first functional layer 3, and exposes the inorganic layer 20, and the inorganic layer 20 covers the substrate 1. During the process of forming the first conductive film 25 by the sputtering process, even if the substrate 1 absorbs water vapor, the inorganic layer 20 can block the water vapor in the substrate 1, avoiding the release of the water vapor in the substrate 1 into the sputtering chamber, so as to ensure the film forming quality of the first conductive film 25. Referring to Figure 6d , the first conductive pattern 26 and the second conductive pattern 27 formed by the preparation method of the present disclosure do not present "small black spots" on the surface.

[0181] In some embodiments, the contact resistance of the first conductive pattern 26 and the first active layer 2 ranges from 969Ω to 1747Ω.

[0182] For example, the contact resistance of the first conductive pattern 26 and the first active layer 2 can be 969Ω, 1100Ω, 1300Ω, 1358Ω, 1747Ω, etc.

[0183] In some embodiments, the preparation method of the display substrate further comprises: S900-S1000.

[0184] S900, in combination with Figure 4i and Figure 4j , a passivation layer 28 is formed on the first conductive pattern 26 and the second conductive pattern 27, and part of the passivation layer 28 is located in the first groove 24 and in contact with the exposed part of the surface of the inorganic layer 20.

[0185] S1000, referring to Figure 4k , the passivation layer 28 is patterned, and at least the part of the passivation layer 28 located in the first groove 24 is removed.

[0186] For example, the passivation layer 28 is used to insulate and protect the first conductive pattern 26 and the second conductive pattern 27. The material of the passivation layer 28 can include inorganic material, for example, the material of the passivation layer 28 includes silicon oxide (SiO).

[0187] For example, the method of forming the passivation layer 28 on the first conductive pattern 26 and the second conductive pattern 27 includes a deposition process.

[0188] It can be understood that, in combination with Figure 4i and Figure 4j Since the first recess 24 has been formed before the passivation layer 28 is formed, the passivation layer 28 is also formed in the first recess 24 during the process of forming the passivation layer 28, and the passivation layer 28 formed in the first recess 24 is in contact with the exposed part of the surface of the inorganic layer 20.

[0189] For example, the method of patterning the passivation layer 28 includes a photolithography process.

[0190] In an implementation, as described above, during the process of forming the first connection hole 6' exposing the first active layer 2' and the second connection hole 7' exposing the second active layer 4' in the corresponding positions of the second insulating layer 5', see Figure 2 , the bending groove 9' located in the bending area B1' is formed. The bending groove 9' penetrates the second insulating layer 5' and the first insulating layer 3', and exposes part of the surface of the substrate 1'. In combination with Figure 1 and Figure 7 , then the first conductive pattern 10' is formed in the first connection hole 6' and the second connection hole 7', and then the passivation layer 11' is formed, so see Figure 7 , the passivation layer 11' is formed on the exposed part of the surface of the substrate 1'. And in an implementation, during the process of patterning the passivation layer 11', the part of the passivation layer 11' located in the bending groove 9' is not removed. Since the photoresist needs to be removed as a mask during the process of patterning the passivation layer 11', and the material of the passivation layer 11' includes inorganic material, and the material of the substrate 1' includes organic material, resulting in weak adhesion between the passivation layer 11' and the substrate 1', therefore, the part of the passivation layer 11' located in the bending groove 9' can be peeled off from the substrate 1' along with the removal of the photoresist, and the peeled-off passivation layer fragments can enter the display area A' of the display substrate, causing display defects of the display substrate.

[0191] And in the present disclosure, see Figure 4kIn the process of patterning the passivation layer 28, the portion of the passivation layer 28 in the first groove 24 has been removed, thus the preparation method of the display substrate of the present disclosure can avoid the peeling of the passivation layer 28 as in the above-mentioned implementation manner, and thus avoid causing display defects of the display substrate.

[0192] Further, before forming the passivation layer 28 in the present disclosure, the substrate 1 in the first groove 24 is covered with the inorganic layer 20, and the material of the passivation layer 28 comprises inorganic material, thus the adhesion between the passivation layer 28 and the inorganic layer 20 is strong. Even if the present disclosure does not remove the portion of the passivation layer 28 in the first groove 24 in S1000, the passivation layer 28 can also be prevented from falling off from the inorganic layer 20 into the display area A of the display substrate in the subsequent cleaning step after patterning the passivation layer 28, thus the display defects of the display substrate can be avoided.

[0193] On the other hand, by removing at least the portion of the passivation layer 28 in the first groove 24, it is beneficial for subsequent patterning of the inorganic layer 20 exposed by the first groove 24. It can be understood that the more inorganic layers in the display substrate, the greater the rigidity of the display substrate, and the smaller the deformation resistance. Therefore, by removing at least the portion of the passivation layer 28 in the first groove 24 in the process of patterning the passivation layer 28, the inorganic layer in the display substrate can be maximized to be removed, and the rigidity of the display substrate can be reduced, thus increasing the deformation resistance of the display substrate.

[0194] In some embodiments, in combination with Figure 4k , Figure 4l and Figure 4m , the preparation method of the display substrate further comprises S1100a-S1200a.

[0195] S1100a, the inorganic layer 20 is patterned through the first groove 24 to form a second groove 29 in communication with the first groove 24, and the second groove 29 exposes a portion of the surface of the substrate 1.

[0196] S1200a, a first planar layer 33 is formed, and a portion of the first planar layer 33 fills the first groove 24 and the second groove 29 and is in contact with the exposed portion of the surface of the substrate 1.

[0197] For example, the method of patterning the inorganic layer 20 comprises a photolithography process.

[0198] By forming the second groove 29 in communication with the first groove 24, and the second groove 29 exposing a portion of the surface of the substrate 1, the film layers in the first groove 24 and the second groove 29 can be completely removed, the film layer thickness of the inorganic layer in the bending area B1 is reduced, and thus more organic material can be filled in the bending area B1 in the subsequent step, and the deformation resistance of the display substrate 100 is increased.

[0199] The first planar layer 33 is used to form a planar surface, which is beneficial for forming other film layers on the first planar layer 33.

[0200] The material of the first planar layer 33 can include an organic material. For example, the material of the first planar layer 33 includes polyimide (PI).

[0201] The method of forming the first planar layer 33 can include a coating process.

[0202] By filling the first groove 24 and the second groove 29 with a portion of the first planar layer 33 and contacting the exposed surface of the substrate 1, the material of the first planar layer 33 can be filled as much as possible in the bending area B1, and the bending performance of the bending area B1 in the area of the first groove 24 and the second groove 29 can be enhanced.

[0203] In some embodiments, referring to Figure 4d The non-display area B further includes a cutting area B2 located on the side of the bending area B1 away from the display area A. In the process of forming the first groove 24 penetrating through at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3 in S310a, the method of manufacturing the display substrate further includes S310b.

[0204] S310b, referring to Figure 4d forming a third groove 31 penetrating through at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3. The third groove 31 is located in the cutting area B2 and exposes a portion of the surface of the inorganic layer 20.

[0205] The cutting area B2 is used to cut the display substrate.

[0206] The above-mentioned substrate can be used to form a display mother board, which includes a plurality of display areas A and non-display areas B arranged correspondingly. By cutting the display mother board, the display mother board can be divided into a plurality of display substrates, and each display substrate has one display area A and one non-display area B.

[0207] For example, referring to Figure 4d In the process of forming the first groove 24 penetrating through at least a portion of the first functional layer 3 and at least a portion of the second functional layer 5, forming the third groove 31 penetrating through at least a portion of the first functional layer 3 and at least a portion of the second functional layer 5 can form the first groove 24 and the third groove 31 in one patterning process, thereby simplifying the manufacturing process of the display substrate.

[0208] Exemplarily, by exposing part of the surface of the inorganic layer 20 through the third groove 31, the thickness of the display substrate 100 at the cutting area B2 can be reduced, which is beneficial for the subsequent processing of the inorganic layer 20 at the cutting area B2.

[0209] It can be understood that, after the display substrate forms the third groove 31, in the process of forming the interlayer dielectric layer 15 on the second functional layer 5 in S400, in combination with Figure 4d and Figure 4e , part of the interlayer dielectric layer 15 will also be filled in the third groove 31.

[0210] In S500, in combination with Figure 4f-1 and Figure 4f-2 , in the process of removing the part of the interlayer dielectric layer 15 filled in the first via hole 14, the part of the interlayer dielectric layer 15 filled in the third groove 31 will also be removed.

[0211] Then, in combination with Figure 4g and Figure 4h , in the process of forming the first conductive film 25 on the interlayer dielectric layer 15, i.e. in S700, part of the first conductive film 25 will also be formed in the third groove 31. In combination with Figure 4g , Figure 4h and Figure 4i , in the process of patterning the first conductive film 25, i.e. in S700, the part of the first conductive film 25 located in the third groove 31 will also be removed.

[0212] Then, in combination with Figure 4j and 4k , in the process of forming the passivation layer 28 on the first conductive pattern 26 and the second conductive pattern 27, i.e. in S900, part of the passivation layer 28 will be formed in the third groove 31 and will be in contact with the part of the surface of the inorganic layer 20 exposed. In the process of patterning the passivation layer 28, i.e. in S1000, the part of the passivation layer 28 located in the third groove 31 will also be removed.

[0213] In some embodiments, in combination with Figure 4k , Figure 4l and Figure 4m , the method for manufacturing the display substrate further comprises: S1100b-S1200b.

[0214] S1100b, the inorganic layer 20 is patterned through the third groove 31 to form a fourth groove 32 in communication with the third groove 31, and the fourth groove 32 exposes part of the surface of the substrate 1.

[0215] S1200b, a first planar layer 33 is formed, and part of the first planar layer 33 fills the third groove 31 and the fourth groove 32 and is in contact with the part of the surface of the substrate 1 exposed.

[0216] Exemplarily, the method for patterning the inorganic layer 20 comprises a photolithography process.

[0217] Exemplarily, S1100a and S1100b can be performed in one patterning process; S1200a and S1200b can be performed in one patterning process; thus, the preparation process of the display substrate can be simplified.

[0218] By forming the fourth groove 32 in communication with the third groove 31, and the fourth groove 32 exposing part of the surface of the substrate 1, the part of each film layer in the area of the third groove 31 and the fourth groove 32 can be completely removed, thereby reducing the film layer thickness of the inorganic layer in the cutting area B2, and then in the subsequent step, the cutting area B2 can be filled with organic material.

[0219] It should be noted that in the case of fracture, the inorganic material is prone to crack and conduct to other areas through the inorganic layer. However, the organic material has good flexibility, and can avoid crack conduction to other areas in the case of fracture.

[0220] By filling part of the first planar layer 33 in the third groove 31 and the fourth groove 32, and contacting the exposed part of the surface of the substrate 1, in the subsequent cutting of the cutting area B2, it can be avoided that cracks are generated in the cutting area B2 and conducted to other areas (such as the display area A).

[0221] In some embodiments, in combination Figure 4d , the display area A of the display substrate comprises a plurality of pixel circuit areas A1( Figure 4c only one pixel circuit area A1 is shown in the figure). In the process of forming the first via 14 penetrating through at least part of the first functional layer 3 and at least part of the second functional layer 5, that is, in S300, the preparation method of the display substrate further comprises: S310c.

[0222] S310c, forming a fifth groove 34 penetrating through at least part of the second functional layer 5 and at least part of the first functional layer 3, the fifth groove 34 being located between two adjacent pixel circuit areas A1.

[0223] In combination Figure 4d and Figure 4e , in the process of forming the interlayer dielectric layer 15 on the second functional layer 5, that is, in S400, part of the interlayer dielectric layer 15 also fills the fifth groove 34.

[0224] Exemplarily, the pixel circuit area A1 represents an area in which a pixel circuit is arranged in the display substrate. For example, in combination Figure 4c and Figure 4i , an area in which the first active layer 2, the second active layer 4, the first conductive pattern 26 and the second conductive pattern 27 are arranged.

[0225] It can be understood that the display substrate is provided with a plurality of pixel driving circuits, and one pixel driving circuit is arranged in one pixel circuit area A1.

[0226] It should be noted that, referring to Figure 4c , the fifth groove 34 penetrates the fifth gate insulating layer 13, the third gate insulating layer 10, the second gate insulating layer 8 and the first gate insulating layer 6 in the at least partial second functional layer 5 and the at least partial first functional layer 3.

[0227] Exemplarily, referring to Figure 4c , the method of forming the fifth groove 34 penetrating the at least partial second functional layer 5 and the at least partial first functional layer 3 includes a photoetching process.

[0228] By forming the fifth groove 34 between the adjacent two pixel circuit areas A1, the portions of the first functional layer 3 and the second functional layer 5 between the adjacent two pixel circuit areas A1 can be removed.

[0229] It can be understood that the more inorganic layers in the display substrate, the greater the rigidity of the display substrate, and the smaller the deformation bearing capacity. Therefore, by removing the inorganic film layer between the adjacent two pixel circuit areas, the rigidity of the portion of the display substrate between the adjacent two pixel circuit areas can be reduced, thereby increasing the deformation bearing capacity of the display substrate.

[0230] Further, the interlayer medium layer 15 includes an organic material and has good toughness. By filling a portion of the interlayer medium layer 15 into the fifth groove 34, the toughness between the adjacent two pixel circuit areas A1 can be increased, and the deformation bearing capacity of the display substrate can be further increased.

[0231] In some embodiments, the above-mentioned step of forming the fifth groove 34 penetrating the at least partial second functional layer 5 and the at least partial first functional layer 3 includes: referring to Figure 4c , before the first via hole 14 penetrating the at least partial first functional layer 3 and the at least partial second functional layer 5 is formed in S300: a sixth groove 35 penetrating the at least partial second functional layer 5 and the third gate insulating layer 10 is formed, and the sixth groove 35 is located between the adjacent two pixel circuit areas. Then, in the process of forming the first via hole 14 penetrating the at least partial second functional layer 5 and the at least partial first functional layer 3 in S300, referring to Figure 4d , the sixth groove 35 is used to form a seventh groove 36 penetrating the second gate insulating layer 27 and the first gate insulating layer 25 and communicating with the sixth groove 35, and the fifth groove 34 includes the sixth groove 35 and the seventh groove 36.

[0232] Exemplarily, referring to Figure 4c , the method of forming the sixth groove 35 penetrating the at least partial second functional layer 5 and the third gate insulating layer 10 includes a photoetching process.

[0233] For example, by forming the sixth groove 35, the thickness of the display substrate in the part of the sixth groove 35 can be reduced, which is beneficial for forming the seventh groove 34 through the sixth groove 35 subsequently.

[0234] For example, by forming the sixth groove 35, the thickness of the display substrate in the part of the sixth groove 35 can be reduced, which is beneficial for forming the seventh groove 34 through the sixth groove 35 subsequently. Figure 4c The method for forming the seventh groove 36 penetrating through the second gate insulating layer 27 and the first gate insulating layer 25 and communicating with the sixth groove 35 includes a photolithography process.

[0235] Further, the first via hole 14 and the seventh groove 36 can be formed in the same process, which can simplify the preparation process of the display substrate.

[0236] It can be understood that after the first planar layer 33 is formed, the preparation method of the display substrate further includes S1300 and S1400.

[0237] S1300, referring to Figure 4n The via hole is formed on the first planar layer 33, and the third conductive pattern 36 is formed. The second planar layer 37 is formed on the third conductive pattern 36.

[0238] S1400, referring to Figure 4o The anode 38, the pixel defining layer 39, the barrier portion 40, the light emitting layer 41, the cathode 42, the encapsulation layer 43, and the cover plate 44 are sequentially formed on the second planar layer 37.

[0239] For example, the third conductive pattern 36 is used to transfer the signal of the first conductive pattern 36. The second planar layer 37 is used to provide a flat surface for subsequent film layers. The anode 38 is used to receive the signal in the third conductive pattern 36 and transmit it to the light emitting layer 41. The pixel defining layer 39 is used to form an opening. The barrier portion 40 is used to support the display substrate to be formed in the process of forming the light emitting layer 41 by using the evaporation process. The anode 38, the light emitting layer 41, and the cathode 42 form a light emitting device, which is used to display an image in the display area A of the display substrate. The encapsulation layer 43 is used to protect the light emitting device. The cover plate 44 is used to protect the formed display substrate.

[0240] The following will be described in combination with Figures 8a to 8d The area formed by the part of the preparation method of the display substrate will be described.

[0241] As described above, in combination with Figure 4c and Figure 8a Before forming the first via hole 14 penetrating through at least part of the second functional layer 5 and at least part of the first functional layer 3 in S300, the preparation method of the display substrate of the present disclosure forms the sixth groove 35 penetrating through at least part of the second functional layer 5 and the third gate insulating layer 10, and the sixth groove 35 is located between two adjacent pixel circuit areas A1.

[0242] It should be noted that Figure 8a Region A in the text refers to the region where the sixth groove 35 is located. That is, before the first via 14 penetrating at least part of the second functional layer 5 and at least part of the first functional layer 3 is formed in S300, the portion of the second functional layer 5 and the third gate insulating layer 10 located in this region is removed.

[0243] Combination Figure 4c and Figure 8b After S300 forms the first through hole 14, S310a forms the first groove 24, S310b forms the third groove 31, and S310c forms the fifth groove 34, Figure 8a Become Figure 8b .

[0244] It should be noted that, Figure 8b Region B in the diagram refers to the area containing the first through-hole 14, the first groove 24, and the third groove 31. (See also...) Figure 4d It is understandable that the area where the fifth groove 34 formed by S310c is located coincides with area A.

[0245] Combination Figure 4e and Figure 8c In S400, an interlayer dielectric layer 15 is formed. In S500, the portion of the interlayer dielectric layer 15 that filled the first via 14, the first groove 24, and the third groove 31 is removed. In S510, a fourth via 18 penetrating the interlayer dielectric layer 15 is formed. Figure 8b Become Figure 8c .

[0246] It should be noted that, in combination Figure 4d to 4f-2 , Figure 8c Region C in the diagram refers to the area where the interlayer dielectric layer 15 remains after the portion of the interlayer dielectric layer 15 that was used to fill the first via 14, the first groove 24, and the third groove 31 has been removed. (See also...) Figure 4f-1 and Figure 4f-2 It is understandable that the remaining part of the interlayer dielectric layer 15 is located in the same region as... Figure 8c The regions A in the diagram overlap. (Combined) Figure 4f-2 , Figure 8c The D region in the diagram refers to the region where the fourth via 18, which forms a through-layer dielectric layer 15, is located in S510.

[0247] Combination Figure 4f-1 , Figure 4f-2 , Figure 4g and Figure 8c After the third via 17, which penetrates the interlayer dielectric layer 15 and at least part of the second functional layer 5, is formed in S600, the region where the third via 17 is located coincides with the region where the fourth via 18 is located. Therefore, after S600, Figure 8cNo change occurs.

[0248] In combination Figure 4h , Figure 4i and Figure 8d , S700 forms a first conductive film 25 on the interlayer dielectric layer 15, patterns the first conductive film 25 to obtain a first conductive pattern 26 and a second conductive pattern 27, and Figure 8c becomes Figure 8d .

[0249] It should be noted that in combination Figure 4i , the area where the first conductive pattern 26 and the second conductive pattern 27 are located is the E area in Figure 8d .

[0250] On the other hand, some embodiments of the present disclosure provide a display substrate 100 formed by, for example, the preparation method of the display substrate provided in some embodiments described above.

[0251] Referring to Figure 9 , the display substrate 100 includes a substrate 1, and a first active layer 2, a first functional layer 3, a second active layer 4, a second functional layer 5 and an interlayer dielectric layer 15 sequentially stacked on the substrate 1. The display substrate 100 further includes a first via hole 14, a second via hole 16 and a third via hole 17. The first via hole 14 penetrates at least part of the second functional layer 5 and at least part of the first functional layer 3, and exposes part of the surface of the first active layer 2. The second via hole 16 penetrates the interlayer dielectric layer 15, and communicates with the first via hole 14. The third via hole 17 exposes part of the surface of the second active layer 4. Compared with the interlayer dielectric layer, the first via hole 14 is formed first, and the third via hole 17 is formed later. The aperture of the first via hole 14 is smaller than the aperture of the second via hole 16, and the aperture of the first via hole 14 is smaller than the aperture of the third via hole 17.

[0252] For example, by making the aperture of the first via hole 14 smaller than the aperture of the second via hole 16, in the process of removing the interlayer dielectric layer 15 formed in the first via hole 14 through the second via hole 16, interference caused by the second via hole 16 being too small to the process of removing the interlayer dielectric layer 15 formed in the first via hole 14 can be avoided.

[0253] In the above implementation, as described above, the first connecting hole 6' and the second connecting hole 7' are formed at the same time, so the apertures of the first connecting hole 6' and the second connecting hole 7' are substantially the same.

[0254] Since in the present disclosure, the first via hole 14 is formed first and the third via hole 17 is formed later than the interlayer dielectric layer 15, it means that the first via hole 14 and the third via hole 17 are not formed at the same time, but after the first via hole 14 is formed, the interlayer dielectric layer 15 with the second via hole 16 is formed first, and then the third via hole 17 is formed.

[0255] It should be noted that the forming process of the first via hole 14 in the present disclosure is the same as that of the first connection hole 6' in the above-mentioned one implementation, so the aperture of the first via hole 14 in the present disclosure is the same as that of the first connection hole 6' in the above-mentioned one implementation.

[0256] Therefore, in the present disclosure, the aperture of the third via hole 17 is larger than that of the second connection hole 7' in the above-mentioned one implementation, so that the area of the second active layer 4 exposed by the third via hole 17 in the present disclosure is also increased, thereby increasing the contact area between the source, the drain and the second active layer 4, and further reducing the contact resistance between the source, the drain and the second active layer 4.

[0257] In addition, in the present disclosure, the step of cleaning the display substrate using the cleaning agent is performed before the formation of the third via hole 17, so that the cleaning agent can avoid corroding the second active layer 4 exposed by the subsequently formed third via hole 17.

[0258] The display substrate 100 provided by some embodiments of the present disclosure can achieve the same beneficial effects as the display substrate preparation method provided by some embodiments described above, which will not be repeated here.

[0259] In some embodiments, referring to Figure 9 , the display substrate 100 has a display area A and a non-display area B. The display area A includes a pixel circuit area A1, and the display substrate 100 further includes a fifth groove 34 and a first groove 24. The fifth groove 34 penetrates at least part of the second functional layer 5 and at least part of the first functional layer 3, and the fifth groove 34 is located between two adjacent pixel circuit areas A1. The first groove 24 penetrates at least part of the second functional layer 5 and at least part of the first functional layer 3. The depth of the second via hole 16 is less than or equal to the depth of the third via hole 17. The depth of the third via hole 17 is less than the depth of the first via hole 14. The depth of the first via hole 14 is less than the depth of the fifth groove 34. The depth of the fifth groove 34 is equal to the depth of the first groove 24.

[0260] For example, at least one pixel circuit area A1 is provided with a pixel driving circuit P (as shown in Figure 10 ).

[0261] The structure of the pixel driving circuit P can include various structures, which can be selected and arranged according to actual needs. For example, the structure of the pixel driving circuit P can include a "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C" structure. Here, "T" represents a thin-film transistor, the number before "T" represents the number of thin-film transistors, and "C" represents a storage capacitor, and the number before "C" represents the number of storage capacitors.

[0262] Referring to Figure 10 , the structure of the pixel driving circuit P is taken as an example of a 7T1C structure.

[0263] It should be noted that the pixel driving circuit P can include a plurality of transistors. The plurality of transistors can include a driving transistor T1, a compensation transistor T2, a first reset transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a switching transistor T6, and a second reset transistor T7.

[0264] In some examples, the control electrode of the first reset transistor T3 is electrically connected to the reset signal line ResetN, the first electrode of the first reset transistor T3 is electrically connected to the first initial signal line Vinit1, and the second electrode of the first reset transistor T3 is electrically connected to the fourth node N4. The first reset transistor T3 is configured to transmit the first initial signal provided by the first initial signal line Vinit1 to the fourth node N4 under the control of the reset signal provided by the reset signal line ResetN.

[0265] In some examples, the control electrode of the second reset transistor T7 is electrically connected to the first gate line GateP, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the first node N1. The second reset transistor T7 is configured to transmit the second initial signal provided by the second initial signal line Vinit2 to the fourth node N4 under the control of the first gate signal provided by the first gate line GateP.

[0266] In some examples, the control electrode of the switching transistor T6 is electrically connected to the first gate line GateP, the first electrode of the switching transistor T6 is electrically connected to the data signal line Data, and the second electrode of the switching transistor T6 is electrically connected to the second node N2. The switching transistor T6 is configured to transmit the data signal provided by the data signal line Data to the second node N2 under the control of the first gate signal provided by the first gate line GateP.

[0267] In some examples, a control electrode of the driving transistor T1 is electrically connected with the fourth node N4, a first electrode of the driving transistor T1 is electrically connected with the second node N2, and a second electrode of the driving transistor T1 is electrically connected with the third node N3. The driving transistor T1 is configured to transmit an electrical signal (e.g. a data signal) from the second node N2 to the third node N3 under the control of a voltage of the fourth node N4.

[0268] In some examples, a control electrode of the compensation transistor T2 is electrically connected with the second gate line GateN, a first electrode of the compensation transistor T2 is electrically connected with the third node N3, and a second electrode of the compensation transistor T2 is electrically connected with the fourth node N4. The compensation transistor T2 is configured to transmit an electrical signal (e.g. a data signal) from the third node N3 to the fourth node N4 under the control of a second gate signal provided by the second gate line GateN.

[0269] In some examples, a control electrode of the first light-emitting control transistor T4 is electrically connected with the enable signal line EM, a first electrode of the first light-emitting control transistor T4 is electrically connected with the first power supply line VDD, and a second electrode of the first light-emitting control transistor T4 is electrically connected with the second node N2. The first light-emitting control transistor T4 is configured to transmit a first power supply signal provided by the first power supply line VDD to the second node N2 under the control of an enable signal provided by the enable signal line EM. The driving transistor T1 can transmit an electrical signal (e.g. the first power supply signal) from the second node to the third node N3.

[0270] In some examples, a control electrode of the second light-emitting control transistor T5 is electrically connected with the enable signal line EM, a first electrode of the second light-emitting control transistor T5 is electrically connected with the third node N3, and a second electrode of the second light-emitting control transistor T5 is electrically connected with the first node N1. The second light-emitting control transistor T5 is configured to transmit an electrical signal (e.g. the first power supply signal) from the third node N3 to the first node N1 under the control of an enable signal provided by the enable signal line EM.

[0271] It can be understood that the control electrode of each of the above-mentioned transistors is a gate (e.g. the first gate 7, the second gate 9 or the third gate 12 mentioned in some of the above-mentioned embodiments), one of the first electrode and the second electrode of each of the transistors is a source (e.g. the first conductive pattern 26 or the second conductive pattern 27 mentioned in some of the above-mentioned embodiments), and the other of the first electrode and the second electrode of each of the transistors is a drain (e.g. the first conductive pattern 26 or the second conductive pattern 27 mentioned in some of the above-mentioned embodiments).

[0272] For example, referring to Figure 11 , three transistors 38-1, 38-2 and 38-3 are shown in the figure.

[0273] For example, the active layer of the transistor 38-1 and the transistor 38-3 includes polysilicon, and thus the transistors 38-1 and 38-3 have high mobility and can accelerate the charging speed of the storage capacitor in the pixel driving circuit P.

[0274] Optionally, the transistor 38-1 can include the second light emitting control transistor T5 or the second reset transistor T7. The transistor 38-3 can include the driving transistor T1 or the first light emitting control transistor T4.

[0275] For example, the active layer of the transistor 38-2 includes metal oxide, and thus the transistor 38-2 has lower leakage current.

[0276] Optionally, the transistor 38-2 can include the compensation transistor T2 or the first reset transistor T3.

[0277] For example, in combination with Figure 10 and Figure 11 , an initial signal line 39 (which can be the first initial signal line Vinit1 or the second initial signal line Vinit2 mentioned in the above examples) is schematically shown in the figure. Referring to Figure 10 , the initial signal line 39 is configured to provide an initial signal, and the initial signal provided in the initial signal line 39 can reset the corresponding capacitor Cst and / or light emitting diode L when the first reset transistor T3 and / or the second reset transistor T7 is turned on.

[0278] For example, the interlayer dielectric layer 15 includes an organic material and has good toughness, and a portion of the interlayer dielectric layer 15 can fill the fifth groove 34, thereby increasing the toughness between the adjacent two pixel circuit areas A1 and increasing the deformation bearing capacity of the display substrate 100.

[0279] It should be noted that the depth mentioned above represents the distance between the upper and lower surfaces of the via hole or groove in the direction perpendicular to the plane in which the display substrate 100 is located.

[0280] By setting the depth of the fifth groove 34 to be equal to the depth of the first groove 24, the thickness of the film layer removed in the process of forming the fifth groove 34 and the first groove 24 is the same, and thus the process parameters for forming the fifth groove 34 and the first groove 24 are the same, thereby simplifying the manufacturing process of the display substrate.

[0281] On the other hand, referring to Figure 12 , some embodiments of the present disclosure provide a display device 1000 including the display substrate 100 as described in any one of the above examples.

[0282] For example, the display device 1000 further includes a housing configured to protect the display substrate 100.

[0283] The display substrate 100 included in the display device 1000 has the same structure and advantageous effects as the display substrate 100 provided in some of the examples described above, and thus a detailed description thereof will not be repeated here.

[0284] In some examples, the display device 1000 can be any device that displays either motion (e.g., video) or fixed (e.g., still image) and either text or graphics. More particularly, it is contemplated that the embodiments can be implemented in or in association with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, display of camera views (e.g., in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry) and the like.

[0285] The above description is merely that of a specific implementation of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art who conceives of changes or substitutions within the scope of the technology disclosed in the present disclosure should be covered within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a display substrate, characterized in that, The preparation method comprises: providing a substrate; forming a first active layer, a first functional layer, a second active layer and a second functional layer on the substrate in sequence; forming a first via hole penetrating through at least part of the second functional layer and at least part of the first functional layer, the first via hole exposing part of the surface of the first active layer; forming an interlayer dielectric layer on the second functional layer, part of the interlayer dielectric layer filling the first via hole; removing the part of the interlayer dielectric layer filling the first via hole and forming a second via hole in the interlayer dielectric layer in communication with the first via hole; forming a third via hole penetrating through the interlayer dielectric layer and at least part of the second functional layer, the third via hole exposing part of the surface of the second active layer.

2. The production method according to claim 1, characterized by, The aperture of the first via hole is smaller than the aperture of the second via hole, and the aperture of the first via hole is smaller than the aperture of the third via hole.

3. The preparation method according to claim 1, wherein in the process of removing the part of the interlayer dielectric layer filling the first via hole and forming a second via hole in the interlayer dielectric layer in communication with the first via hole, the preparation method further comprises: forming a fourth via hole penetrating through the interlayer dielectric layer; the orthographic projection of the fourth via hole on the substrate is located within the orthographic projection range of the second active layer on the substrate; the forming of the third via hole penetrating through the interlayer dielectric layer and at least part of the second functional layer comprises: patterning the second functional layer through the fourth via hole to form a fifth via hole penetrating through at least part of the second functional layer; the third via hole comprises the fourth via hole and the fifth via hole.

4. The method of claim 1, wherein, The substrate has a display area and a non-display area, the non-display area comprises a bending area, and the first active layer and the second active layer are located in the display area; before the forming of the first active layer, the first functional layer, the second active layer and the second functional layer on the substrate in sequence, the preparation method further comprises: forming an inorganic layer on the substrate; in the process of forming the first via hole penetrating through at least part of the second functional layer and at least part of the first functional layer, the preparation method further comprises: forming a first groove penetrating through at least part of the second functional layer and at least part of the first functional layer, the first groove being located in the bending area and exposing part of the surface of the inorganic layer.

5. The preparation method according to claim 4, characterized in that, The display substrate has a display area and a non-display area; the display area comprises a pixel circuit area; in the process of forming the first via hole penetrating through at least part of the second functional layer and at least part of the first functional layer, the preparation method further comprises: forming a fifth groove penetrating through at least part of the second functional layer and at least part of the first functional layer, the fifth groove being located between two adjacent pixel circuit areas; wherein the depth of the second via hole is less than or equal to the depth of the third via hole, the depth of the third via hole is less than the depth of the first via hole, the depth of the first via hole is less than the depth of the fifth groove, and the depth of the fifth groove is equal to the depth of the first groove.

6. The preparation method according to claim 4, characterized in that, The preparation method further comprises: forming a first conductive film on the interlayer dielectric layer, the first conductive film covering a surface of the interlayer dielectric layer and being located in the first via, the second via, the third via and the first recess; patterning the first conductive film to retain a portion of the first conductive film located in the first via and the second via to obtain a first conductive pattern, and to retain a portion of the first conductive film located in the third via to obtain a second conductive pattern.

7. The production method according to claim 6, characterized by, The contact resistance of the first conductive pattern and the first active layer ranges from 969Ω to 1747Ω.

8. The preparation method according to claim 6, characterized in that, The preparation method further comprises: forming a passivation layer on the first conductive pattern and the second conductive pattern, a portion of the passivation layer being located in the first recess and being in contact with a portion of the surface of the inorganic layer exposed; patterning the passivation layer to remove at least the portion of the passivation layer located in the first recess.

9. The preparation method according to claim 6, characterized in that, The preparation method further comprises: patterning the inorganic layer through the first recess to form a second recess in communication with the first recess, the second recess exposing a portion of the surface of the substrate; forming a first planar layer, a portion of the first planar layer filling the first recess and the second recess and being in contact with a portion of the surface of the substrate exposed.

10. The method of claim 4, wherein, The non-display area further comprises a cutting area located away from the display area on a side of the bending area; In the process of forming the first recess penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the preparation method further comprises: forming a third recess penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the third recess being located in the cutting area and exposing a portion of the surface of the inorganic layer.

11. The method of claim 10, wherein, The preparation method further comprises: patterning the inorganic layer through the third recess to form a fourth recess in communication with the third recess, the fourth recess exposing a portion of the surface of the substrate; forming a first planar layer, a portion of the first planar layer filling the third recess and the fourth recess and being in contact with a portion of the surface of the substrate exposed.

12. The method of claim 1, wherein, The step of forming the first functional layer comprises: forming a first gate insulating layer, a first gate electrode, a second gate insulating layer, a second gate electrode and a third gate insulating layer in sequence, a projection of the first gate electrode on the substrate partially overlapping a projection of the first active layer on the substrate, and a projection of the second gate electrode on the substrate partially overlapping a projection of the second active layer on the substrate; The step of forming the second functional layer comprises: forming a fourth gate insulating layer, a third gate electrode and a fifth gate insulating layer in sequence, a projection of the third gate electrode on the substrate partially overlapping a projection of the second active layer on the substrate.

13. The method of claim 12, wherein, The substrate has a display area, and the display area comprises a plurality of pixel circuit areas; In the process of forming the first via penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the preparation method further comprises: forming a fifth recess penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the fifth recess being located between two adjacent pixel circuit areas; In a process of forming an interlayer dielectric layer on the second functional layer, the interlayer dielectric layer also fills the fifth groove.

14. The method of claim 13, wherein, The forming of the fifth groove through at least part of the second functional layer and at least part of the first functional layer comprises: Before the forming of the first via through at least part of the second functional layer and at least part of the first functional layer, a sixth groove is formed through at least part of the second functional layer and the third gate insulating layer, the sixth groove being located between two adjacent pixel circuit regions; In a process of forming the first via through at least part of the second functional layer and at least part of the first functional layer, a seventh groove is formed through the second gate insulating layer and the first gate insulating layer and in communication with the sixth groove through the sixth groove, the fifth groove comprising the sixth groove and the seventh groove.

15. The preparation method according to claim 12, characterized in that, A normal projection of the fourth gate insulating layer on the substrate and a normal projection of the third gate electrode on the substrate coincide.

16. The production method according to any one of claims 1 to 15, characterized by, The material of the first active layer comprises polysilicon, and the material of the second active layer comprises metal oxide.

17. A display substrate, comprising: The display substrate is prepared by the preparation method in any one of claims 1-16.

18. A display device comprising: The display device comprises the display substrate in claim 17.

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