A composite ADC circuit for audio active noise reduction

Abstract

This application relates to the field of integrated circuit technology and discloses a composite ADC circuit for audio active noise reduction. The circuit comprises a sampling module for acquiring a sampled signal and converting it into an analog output signal; a filtering module electrically connected to the output of the sampling module for performing at least two-order noise shaping on the analog signal based on a sigma-delta modulator architecture to obtain a filtered signal; and a quantization module electrically connected to the output of the filtering module for asynchronously sampling the filtered signal and outputting at least a 4-bit quantized signal. This application significantly reduces the latency of the digital filter without reducing the overall signal-to-noise ratio of the circuit, meeting the processing time requirements of active noise reduction and being applicable to the low latency, high precision, and low power consumption requirements of active noise reduction audio ADCs.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a composite ADC circuit for audio active noise reduction function. Background Art

[0002] With the development of mobile internet, especially the popularity of mobile phones and portable in-ear headphones, noise cancellation has become a new product highlight. Headphone noise cancellation is mainly categorized into passive and active noise cancellation. Active noise cancellation uses a microphone to actively capture ambient noise, quickly processes it, and then transmits it to the headphones for playback. This creates a sound wave signal that is in phase with the ambient noise, canceling out the effects on the eardrum, achieving active noise cancellation. However, due to the structural limitations of headphones and the human ear, the entire active noise cancellation processing time, from the microphone capturing ambient noise to the output of the inverted signal, must be extremely short. Otherwise, the ambient noise will have already reached the eardrum, and the active noise cancellation output will not be able to keep up with the ambient noise propagation through the air and ear canal, resulting in ineffective active noise cancellation. Considering the physical structure of typical headphones, the distance from the microphone's acquisition point to the actual headphone output point is only 1-2 cm. Since sound propagates at 340 m / s in air, this processing time is 29-58 μs. Therefore, the entire active noise cancellation processing time must be within this range to achieve effective noise cancellation.

[0003] The sampling rate of existing sigma-delta modulators used for audio active noise reduction functions is 8K-48KHZ. Simply sampling a point requires 20us-125us. In addition, the sigma-delta modulator structure uses the time accumulation result of multiple sampling as a sampling point output, so the actual delay of its digital filter will be even greater. Generally, the oversampling rate is 128, and the ADC clock of the modulator is 6.144MHz (48K*128). The sound delay after digital filtering is close to 100us, which cannot meet the active noise reduction processing time requirements.

[0004] With respect to the above-mentioned related technologies, the inventors have found that the existing sigma-delta modulator has the problem of being difficult to simultaneously meet the requirements of delay performance, signal-to-noise ratio and power consumption. Summary of the Invention

[0005] In order to improve latency performance while reducing the impact on the chip's signal-to-noise ratio and lowering power consumption, the present application provides a composite ADC circuit for audio active noise reduction function.

[0006] In a first aspect, the present application provides a composite ADC circuit for audio active noise reduction function.

[0007] This application is achieved through the following technical solutions:

[0008] A composite ADC circuit for audio active noise reduction function, comprising:

[0009] Sampling module, used to obtain sampling signals and convert them into analog signal output;

[0010] a filtering module, electrically connected to an output end of the sampling module, configured to perform at least second-order noise shaping on the analog signal based on a sigma-delta modulator architecture to obtain a filtered signal;

[0011] The quantization module is electrically connected to the output end of the filtering module and is used to asynchronously sample the filtered signal and output a quantized signal of at least 4 bits.

[0012] In a preferred example, the present application may be further configured as follows: the filtering module performs 2nd to 4th order noise shaping on the analog signal.

[0013] In a preferred example, the present application can be further configured as follows: the filtering module adopts any one of CIFF / CIFB / CRFF / CRFB modulators.

[0014] In a preferred example, the present application can be further configured as follows: the quantization module outputs a 4-8 bit quantization signal.

[0015] In a preferred example, the present application may be further configured as follows: the filtering module includes a 0th-order holder, a first integrator, a second integrator, a first adder, a second adder, and a first delay module;

[0016] The input end of the 0th-order holder is connected to the sampling voltage, the output end of the 0th-order holder is connected to the input end of the first integrator, the output end of the first integrator is connected to an input end of the first adder, the output end of the sampling module is connected to the input end of the second integrator, the output end of the second integrator is connected to the other input end of the first adder, the output end of the first adder is connected to an input end of the second adder, the output end of the second adder is connected to the input end of the first delay module, and the output end of the first delay module is connected to the other input end of the second adder.

[0017] In a preferred example, the present application may be further configured as follows: the filtering module further includes a third integrator, a third adder, and a second delay module;

[0018] The output end of the first delay module is also connected to the input end of the third integrator, the output end of the third integrator is connected to an input end of the third adder, the output end of the third adder is connected to the input end of the second delay module, and the output end of the second delay module is connected to the other input end of the third adder.

[0019] In a preferred example, the present application may be further configured as follows: the filtering module further includes a fourth integrator, a fifth integrator, a sixth integrator and a fourth adder, and the second delay module is connected to the input end of the quantization module via the fourth adder;

[0020] The output end of the second delay module is connected to the input end of the fourth integrator, and the output end of the fourth integrator is connected to an input end of the fourth adder;

[0021] The output end of the first delay module is connected to the input end of the fifth integrator, and the output end of the fifth integrator is connected to the other input end of the fourth adder;

[0022] The output end of the 0th-order holder is connected to the input end of the sixth integrator, and the output end of the sixth integrator is connected to another input end of the fourth adder.

[0023] In a preferred example, the present application can be further configured as follows: the quantization module is an ADC quantizer.

[0024] In a preferred example, the present application may be further configured as follows: the ADC quantizer includes a comparator of asynchronous SAR logic, and the output end of the second delay module is connected to the input end of the comparator.

[0025] In a preferred example, the present application may be further configured as follows: the sampling module includes a capacitor array DAC quantizer.

[0026] In a preferred example, the present application can be further configured as follows: the capacitor array is formed by capacitors of the same value being connected in parallel.

[0027] In a preferred example, the present application can be further configured as follows:

[0028] The workspace module is electrically connected to the quantization module and is used to store the quantization signal.

[0029] In a second aspect, the present application provides an audio active noise reduction method of a composite ADC circuit.

[0030] This application is achieved through the following technical solutions:

[0031] An audio active noise reduction method for a composite ADC circuit includes the following steps:

[0032] Trigger the DAC quantizer to obtain the sampling signal and convert it into an analog signal output;

[0033] performing at least second-order noise shaping on the analog signal based on a sigma-delta modulator architecture to obtain a filtered signal;

[0034] An ADC quantizer is used to asynchronously sample the filtered signal and output a quantized signal of at least 4 bits.

[0035] In a preferred example, the present application may be further configured as follows: the step of asynchronously sampling the filtered signal by the ADC quantizer includes:

[0036] Start the external clock;

[0037] The comparator performs a sampling conversion in response to the external clock, and

[0038] The comparator generates a clock each time a comparison is completed to promote the charge and discharge / comparison of multiple bits.

[0039] In a preferred example, the present application can be further configured as follows: the step of the DAC quantizer acquiring the sampled signal and converting it into an analog signal output includes:

[0040] Determine the target capacitance based on the charge and discharge pattern of the capacitor array and the total number of input digital codes;

[0041] In response to the external clock, the target capacitors sequentially participate in charge conversion integration, complete capacitance-voltage conversion, and output analog signals.

[0042] In a preferred example, the present application may be further configured as follows: before the step of making the target capacitor participate in the charge conversion integration, the step further includes:

[0043] introducing a second clock having a higher frequency than the external clock;

[0044] When the second clock flips, in response to the external clock, the target capacitors sequentially participate in the charge conversion integration, wherein the total unit capacitance of each target capacitor remains unchanged.

[0045] In a preferred example, the present application can be further configured as follows: the order of the noise shaping and the bit value of the ADC quantizer satisfy the following relationship:

[0046] SNR max =10*lg[1.5*(2L+1) / (PI 2L )*OSR (2L+1) *2 (N-1) ]

[0047] Where, SNR max is the upper limit of the target signal-to-noise ratio, L is the order of noise shaping, OSR is the oversampling rate of the ADC quantizer, N is the bit value of the ADC quantizer, and PI is a constant.

[0048] In a third aspect, the present application provides an integrated circuit.

[0049] This application is achieved through the following technical solutions:

[0050] An integrated circuit comprises any one of the above-mentioned composite ADC circuits for audio active noise reduction function.

[0051] In a fourth aspect, the present application provides an audio processing chip.

[0052] This application is achieved through the following technical solutions:

[0053] An audio processing chip includes an integrated circuit, wherein the integrated circuit includes any one of the composite ADC circuits described above for audio active noise reduction function.

[0054] In a fifth aspect, the present application provides a portable in-ear headset.

[0055] This application is achieved through the following technical solutions:

[0056] A portable in-ear headset comprises a microphone and a speaker, wherein the microphone and the speaker are electrically connected to a composite ADC circuit for audio active noise reduction function as described above.

[0057] In summary, compared with the prior art, the technical solution provided by this application has at least the following beneficial effects:

[0058] Based on the sigma-delta modulator architecture, at least two orders of spectrum shifting or noise shaping are achieved, so that the oversampling rate can be configured to only 32 or 16. At the same time, the quantization part adopts an asynchronous sampling structure to directly output at least 4-bit quantized signals, achieving the goals of high sampling rate and low power consumption. Without reducing the overall signal-to-noise ratio of the circuit, the delay of the digital filter is greatly reduced, meeting the processing time requirements of active noise reduction, and can be applied to the low latency, high precision and low power consumption requirements of active noise reduction frequency ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A schematic structural diagram of a composite ADC circuit for audio active noise reduction function provided by an exemplary embodiment of the present application.

[0060] Figure 2 A structural block diagram of an ADC quantizer of a composite ADC circuit for audio active noise reduction function provided by yet another exemplary embodiment of the present application.

[0061] Figure 3 A structural block diagram of a DAC quantizer of a composite ADC circuit for audio active noise reduction function provided by another exemplary embodiment of the present application.

[0062] Figure 4 This figure compares the shaped spectrum and achievable SNR of a conventional audio sigma-delta ADC structure with the shaped spectrum and achievable SNR of a composite ADC circuit for audio active noise reduction provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0063] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed, but as long as they are within the scope of the claims of the present application, they are protected by the patent law.

[0064] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0065] In this document, the term "and / or" simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document, unless otherwise specified, generally indicates an "or" relationship between the related objects.

[0066] The sigma-delta ADC used in active noise cancellation (ANC) for headphones has a sampling rate of 8K-48KHZ, meaning that simply sampling a single point takes 20us-125us. Furthermore, the sigma-delta ADC uses the accumulated time of multiple samplings as a single output point, leading to a greater delay in the digital filter. For a modulator with an oversampling rate (OSR) of 128 and an ADC clock of 6.144MHz (48K*128), the delay after passing through the digital filter is typically close to 100us, making it difficult to meet the ANC processing time requirement of less than 29us-58us.

[0067] The delay of the digital filter is To reduce latency, OSR must be reduced or fmod must be increased. However, reducing OSR reduces the signal-to-noise ratio (SNR) of the sigma-delta ADC, failing to meet the SNR requirements for microphone recording. Increasing fmod dramatically increases the power consumption of the ADC modulator. Furthermore, simply increasing the sampling rate or modulator clock frequency to achieve low latency in audio sigma-delta ADCs results in significant power consumption and clock complexity.

[0068] Therefore, the present application proposes a composite ADC circuit for audio active noise reduction function, which adopts a sigma-delta modulator structure to achieve at least 2-order noise spectrum shifting or noise shaping. The oversampling rate can be configured to only 32 or 16. At the same time, the modulator quantizer samples the asynchronous SARADC structure to directly output at least 4-bit quantized signal, achieving the purpose of high sampling rate and low power consumption.

[0069] The embodiments of the present application are described in further detail below with reference to the accompanying drawings.

[0070] The embodiment of the present application provides a composite ADC circuit for audio active noise reduction function, comprising:

[0071] Sampling module, used to obtain sampling signals and convert them into analog signal output;

[0072] a filtering module, electrically connected to an output end of the sampling module, configured to perform at least second-order noise shaping on the analog signal based on a sigma-delta modulator architecture to obtain a filtered signal;

[0073] The quantization module is electrically connected to the output end of the filtering module and is used to asynchronously sample the filtered signal and output a quantized signal of at least 4 bits.

[0074] The sampling module acquires the sampled signal and converts it into an analog signal, which is then fed back into the modulation loop. The filtering module, based on the sigma-delta modulator architecture, performs at least two orders of spectrum shifting or noise shaping on the analog signal. The oversampling rate can be configured to only 32 or 16. At the same time, the quantization module adopts an asynchronous sampling structure to directly output at least a 4-bit quantized signal, achieving a high sampling rate and low power consumption. Without reducing the overall signal-to-noise ratio of the circuit, the delay of the digital filter is greatly reduced, meeting the processing time requirements of active noise reduction, and being applicable to the low latency, high precision, and low power consumption requirements of the active noise reduction frequency ADC.

[0075] Furthermore, in order to meet the audio active noise reduction performance of the headset, the filtering module performs 2-4 order noise shaping on the analog signal, which can reduce power consumption as much as possible and reduce the overall power consumption of the circuit.

[0076] Furthermore, in order to meet the time requirement of the noise reduction processing, the quantization module outputs a 4-8 bit quantized signal, which can reduce the overall power consumption of the circuit while meeting the processing speed requirement.

[0077] Furthermore, a composite ADC circuit for audio active noise reduction function also includes:

[0078] The workspace module is electrically connected to the quantization module and is used to store the quantization signal to reduce the loss of the quantization result.

[0079] Specifically, refer to Figure 1 ,Take the filtering module using 2nd order noise shaping CIFF and the quantization module outputting 6-bit quantized signal as an example.

[0080] The multi-bit ADC quantizer requires a matching multi-bit DAC quantizer (i.e., asynchronous SARADC output) within the modulator loop. The sampling module uses a DAC quantizer to sample six signals from the device's Result. The DAC quantizer converts these signals into analog signals that are fed back to the modulator loop. The sampling module can use a DAC0832 digital-to-analog converter, a DAC3482 digital-to-analog converter, or an MCP4725 digital converter.

[0081] A sigma-delta ADC is used as the main part of a composite ADC circuit to implement a noise shaping function.

[0082] The filtering module includes a 0th-order holder, a first integrator, a second integrator, a first adder, a second adder and a first delay module; the input end of the 0th-order holder is connected to the sampling voltage, the output end of the 0th-order holder is connected to the input end of the first integrator, the output end of the first integrator is connected to one input end of the first adder, the output end of the sampling module is connected to the input end of the second integrator, the output end of the second integrator is connected to the other input end of the first adder, the output end of the first adder is connected to one input end of the second adder, the output end of the second adder is connected to the input end of the first delay module, and the output end of the first delay module is connected to the other input end of the second adder, so as to complete the first-order noise shaping and realize the noise reduction of the sampling signal.

[0083] The filtering module also includes a third integrator, a third adder and a second delay module; the output end of the first delay module is also connected to the input end of the third integrator, the output end of the third integrator is connected to one input end of the third adder, the output end of the third adder is connected to the input end of the second delay module, and the output end of the second delay module is connected to the other input end of the third adder to complete second-order noise shaping. The higher the order, the better the noise shaping effect, and a higher signal-to-noise ratio can be achieved.

[0084] The higher the order of noise shaping, the higher the number of integrator stages consumed. In order to match the second-order noise shaping structure, the filtering module further includes a fourth integrator, a fifth integrator, a sixth integrator and a fourth adder. The second delay module is connected to the input end of the quantization module via the fourth adder; the output end of the second delay module is connected to the input end of the fourth integrator, and the output end of the fourth integrator is connected to an input end of the fourth adder.

[0085] The output end of the first delay module is connected to the input end of the fifth integrator, and the output end of the fifth integrator is connected to another input end of the fourth adder; the output end of the 0th-order holder is connected to the input end of the sixth integrator, and the output end of the sixth integrator is connected to another input end of the fourth adder.

[0086] Furthermore, in one embodiment, the modulator order mainly considers the audio MIC head sensor. Assuming that the signal-to-noise ratio (SNR) is 80dB, a 2nd-order or 3rd-order shaping filter is selected to meet the signal-to-noise ratio requirement of MIC recording and achieve lower power consumption.

[0087] Furthermore, the filtering module can adopt any one of CIFF (cascade of integrators, feedforward form) / CIFB (cascade of integrators, feedback form) / CRFF (cascade of resonators, feedforward form) / CRFB (cascade of resonators, feedback form) modulators. There are many types of filtering modules to choose from, which is convenient for mass production.

[0088] When the filter module adopts CIFB, compared with the CIFF structure, the quantizer part does not require an adder, only the output of the last-stage integrator is quantized, and the DAC output feedback needs to be connected to the input of each stage of the integrator.

[0089] When the filter module adopts the CRFF / CRFB structure, the integrator of each stage needs to be changed to a circuit with both integration and differentiation.

[0090] Reference Figure 2 The quantization module is an ADC quantizer. The ADC quantizer includes a comparator with asynchronous SAR logic. The output of the second delay module is connected to the input of the comparator. The comparator performs SAR (successive approach register) logic processing based on the comparison result.

[0091] For asynchronous SAR ADC quantizers, the oversampling rate is equal to the ADC modulator clock frequency. Asynchronous SAR ADC quantizers utilize only an external clock to initiate a single sampling conversion. The internal multi-bit charge charging, discharging, and comparison are driven by the clock generated by the comparator at the completion of each comparison. This leverages the comparator's ability to quickly complete comparisons when there is a significant difference between the two comparison voltages, enabling high-speed comparison and quantization conversion. This improves processing efficiency and meets the latency performance requirements of audio active noise reduction.

[0092] Taking a modulator clock of 6.144 MHz as an example, with an OSR of 32, the actual sampling rate is 384 kHz. This significantly reduces latency compared to sampling rates with an OSR of 128 / 96 kHz. Although the modulator clock remains the same, the quantizer inside the modulator, an asynchronous SAR ADC, samples at the modulator clock frequency of 6.144 MHz. If the modulator clock is increased to 12.288 MHz, the sampling rate can be increased to 768 kHz.

[0093] When the sigma-delta ADC modulator clock is fixed, the high sampling rate of the asynchronous SAR ADC is utilized to implement multi-bit quantization, allowing the SNR of the entire modulator to remain within a high range. This reduces the OSR of the digital filter and its delay, further shortening the active noise reduction function of the target audio.

[0094] The filtering module adopts 3 / 4 order, and the quantization module outputs 4 / 5 / 7 / 8-bit circuit structure, which is similar to the circuit structure in which the filtering module adopts 2-order noise shaping and the quantization module outputs 6-bit quantized signal. The higher the order, the more integrators are consumed, including op amps and capacitor arrays, which increases power consumption, but the noise shaping effect is better and a higher SNR can be achieved. I will not go into details here.

[0095] Reference Figure 3 In one embodiment, the sampling module includes a capacitor array DAC quantizer. In order to achieve low power consumption, this embodiment uses a capacitor array charge and discharge method.

[0096] Because of the matching requirements of the DAC capacitor array, in order to improve the capacitor mismatch problem, the capacitor array can be formed by connecting capacitors of the same value in parallel, or by introducing the traditional DWA algorithm (data weight average).

[0097] For example, the 6-bit DAC input digital code D<5:0> is converted to a binary number ranging from 0 to 63. This means that the DAC capacitor-to-voltage conversion involves 0 to 63 unit capacitors participating in the charge conversion integration. Without the DWA algorithm, the capacitor-to-voltage conversion is performed directly according to the input digital code. For example, a fixed number of 0, 1, 2, 3, ..., 63 unit capacitors are involved in the conversion each time. This results in the weight of a certain capacitor affecting the conversion accuracy. In one embodiment, the DWA algorithm introduces a clock CLK with a higher frequency than the external clock. Even if the current input digital code is 1, as the high-frequency CLK flips, the total number of unit capacitors selected by the mux selector remains fixed at 1 each time. However, a different capacitor is selected for the conversion during each flip cycle. Even if a capacitor has a large weight, it is not fixed in the actual conversion, thus reducing the impact of capacitor mismatch.

[0098] The performance indicators that can be achieved by using a composite ADC circuit for audio active noise reduction function of the present application are shown in Table 1 below. It can be seen that the entire delay of the ADC modulator of the present application can be controlled within 10us and the power consumption is low.

[0099] Table 1

[0100]

[0101] like Figure 4 As shown, the first figure is a schematic diagram of the noise shaping spectrum and the achieved SNR index of a common audio sigma-delta ADC modulator with 1-bit quantization when OSR = 128. The second figure is a schematic diagram of the noise shaping spectrum and the achieved SNR index of the audio sigma-delta ADC modulator with 6-bit quantization of the present application when OSR = 32. At this time, the SNR index can also reach 90dB, meeting the audio low noise requirement.

[0102] In summary, a composite ADC circuit for audio active noise reduction uses a sigma-delta modulator structure to achieve at least 2-order noise spectrum shifting or noise shaping, but the OSR can be configured to only 32 or 16. At the same time, the modulator quantizer samples the asynchronous SARADC structure to directly output at least a 4-bit quantized signal, achieving a high sampling rate and low power consumption to ensure the SNR requirements of the overall circuit. However, because the OSR is reduced, the delay performance of the digital filter is improved. For example, the delay of the digital filter becomes 1 / 4 or 1 / 8 of the original, which can meet the processing time requirements of active noise reduction and even reach within 10us. At this time, the SNR is maintained at around 80-90dB, which can better meet the low latency, high precision and low power consumption requirements of the active noise reduction audio ADC.

[0103] Each module in the aforementioned composite ADC circuit for audio active noise reduction can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0104] The present application also provides an audio active noise reduction method for a composite ADC circuit. The audio active noise reduction method for the composite ADC circuit is applied to a composite ADC circuit for audio active noise reduction function in the above embodiment. The audio active noise reduction method for the composite ADC circuit includes the following steps:

[0105] Trigger the DAC quantizer to obtain the sampling signal and convert it into an analog signal output;

[0106] performing at least second-order noise shaping on the analog signal based on a sigma-delta modulator architecture to obtain a filtered signal;

[0107] An ADC quantizer is used to asynchronously sample the filtered signal and output a quantized signal of at least 4 bits.

[0108] In one embodiment, the step of asynchronously sampling the filtered signal by the ADC quantizer includes:

[0109] Start the external clock;

[0110] The comparator performs a sampling conversion in response to the external clock, and

[0111] The comparator generates a clock each time a comparison is completed to promote the charge and discharge / comparison of multiple bits.

[0112] In one embodiment, the step of the DAC quantizer acquiring a sampled signal and converting it into an analog signal for output includes:

[0113] Determine the target capacitance based on the charge and discharge pattern of the capacitor array and the total number of input digital codes;

[0114] In response to the external clock, the target capacitors sequentially participate in charge conversion integration, complete capacitance-voltage conversion, and output analog signals.

[0115] In one embodiment, before the step of allowing the target capacitance to participate in the charge conversion integration, the method further includes:

[0116] introducing a second clock having a higher frequency than the external clock;

[0117] When the second clock flips, in response to the external clock, the target capacitors sequentially participate in the charge conversion integration, wherein the total unit capacitance of each target capacitor remains unchanged.

[0118] In one embodiment, the order of the noise shaping and the bit value of the ADC quantizer satisfy the following relationship:

[0119] SNR max =10*lg[1.5*(2L+1) / (PI 2L )*OSR (2L+1) *2 (N-1) ]

[0120] Where, SNR max is the upper limit of the target signal-to-noise ratio, L is the order of noise shaping, OSR is the oversampling rate of the ADC quantizer, N is the bit value of the ADC quantizer, PI is a constant, and PI can be 3.14159.

[0121] For the specific definition of the audio active noise reduction method of a composite ADC circuit, please refer to the above definition of a composite ADC circuit for audio active noise reduction function, which will not be repeated here.

[0122] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0123] In one embodiment, an integrated circuit is provided, comprising any one of the above-mentioned composite ADC circuits for audio active noise reduction function.

[0124] In one embodiment, an audio processing chip is provided, including an integrated circuit, wherein the integrated circuit includes any one of the above-mentioned composite ADC circuits for audio active noise reduction function.

[0125] In one embodiment, a portable in-ear headset is provided, comprising a microphone and a speaker, wherein the microphone and the speaker are electrically connected to a composite ADC circuit for audio active noise reduction function as described above.

[0126] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. When executed, the computer program can include the processes of the above-described method embodiments.

[0127] Those skilled in the art will clearly understand that for the sake of convenience and brevity in description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above.

Claims

1. A composite ADC circuit for audio active noise reduction function, characterized in that: include, Sampling module, used to obtain sampling signals and convert them into analog signal output; a filtering module electrically connected to the output end of the sampling module, configured to perform at least 2nd-order noise shaping on the analog signal based on a sigma-delta modulator architecture to obtain a filtered signal; wherein the filtering module includes a 0th-order holder, a first integrator, a second integrator, a first adder, a second adder, and a first delay module; The input end of the 0-order holder is connected to the sampling voltage, the output end of the 0-order holder is connected to the input end of the first integrator, the output end of the first integrator is connected to an input end of the first adder, the output end of the sampling module is connected to the input end of the second integrator, the output end of the second integrator is connected to the other input end of the first adder, the output end of the first adder is connected to an input end of the second adder, the output end of the second adder is connected to the input end of the first delay module, and the output end of the first delay module is connected to the other input end of the second adder; The quantization module is electrically connected to the output end of the filtering module and is used to asynchronously sample the filtered signal and output a quantized signal of at least 4 bits.

2. The composite ADC circuit for audio active noise reduction according to claim 1, characterized in that: The filtering module performs 2nd to 4th order noise shaping on the analog signal.

3. The composite ADC circuit for audio active noise reduction according to claim 1, wherein: The filtering module adopts any one of CIFF / CIFB / CRFF / CRFB modulators.

4. The composite ADC circuit for audio active noise reduction according to claim 1, wherein: The quantization module outputs a 4-8 bit quantized signal.

5. The composite ADC circuit for audio active noise reduction according to claim 1, wherein: The filtering module further includes a third integrator, a third adder and a second delay module; The output end of the first delay module is also connected to the input end of the third integrator, the output end of the third integrator is connected to an input end of the third adder, the output end of the third adder is connected to the input end of the second delay module, and the output end of the second delay module is connected to the other input end of the third adder.

6. The composite ADC circuit for audio active noise reduction according to claim 5, characterized in that: The filtering module further includes a fourth integrator, a fifth integrator, a sixth integrator and a fourth adder, and the second delay module is connected to the input end of the quantization module via the fourth adder; The output end of the second delay module is connected to the input end of the fourth integrator, and the output end of the fourth integrator is connected to an input end of the fourth adder; The output end of the first delay module is connected to the input end of the fifth integrator, and the output end of the fifth integrator is connected to the other input end of the fourth adder; The output end of the 0th-order holder is connected to the input end of the sixth integrator, and the output end of the sixth integrator is connected to another input end of the fourth adder.

7. The composite ADC circuit for audio active noise reduction according to claim 5, characterized in that: The quantization module is an ADC quantizer.

8. The composite ADC circuit for audio active noise reduction according to claim 7, characterized in that: The ADC quantizer includes a comparator of asynchronous SAR logic, and the output end of the second delay module is connected to the input end of the comparator.

9. The composite ADC circuit for audio active noise reduction according to claim 1, wherein: The sampling module includes a capacitor array DAC quantizer.

10. The composite ADC circuit for audio active noise reduction according to claim 9, characterized in that: The capacitor array is formed by connecting capacitors of the same value in parallel.

11. The composite ADC circuit for audio active noise reduction according to claim 1, wherein: Also includes, The workspace module is electrically connected to the quantization module and is used to store the quantization signal.

12. An audio active noise reduction method for a composite ADC circuit, characterized in that: The composite ADC circuit for audio active noise reduction function according to any one of claims 1 to 11 comprises the following steps: Trigger the DAC quantizer to obtain the sampling signal and convert it into an analog signal output; performing at least second-order noise shaping on the analog signal based on a sigma-delta modulator architecture to obtain a filtered signal; An ADC quantizer is used to asynchronously sample the filtered signal and output a quantized signal of at least 4 bits.

13. The audio active noise reduction method of the composite ADC circuit according to claim 12, characterized in that: The step of asynchronously sampling the filtered signal by the ADC quantizer comprises: Start the external clock; The comparator performs a sampling conversion in response to the external clock, and The comparator generates a clock each time a comparison is completed to promote the charge and discharge / comparison of multiple bits.

14. The audio active noise reduction method of the composite ADC circuit according to claim 13, characterized in that: The DAC quantizer obtains the sampling signal and converts it into an analog signal for output, including: Determine the target capacitance based on the charge and discharge pattern of the capacitor array and the total number of input digital codes; In response to the external clock, the target capacitors sequentially participate in charge conversion integration, complete capacitance-voltage conversion, and output analog signals.

15. The audio active noise reduction method of the composite ADC circuit according to claim 14, characterized in that: Before the step of allowing the target capacitor to participate in the charge conversion integration, the method further includes: introducing a second clock having a higher frequency than the external clock; When the second clock flips, in response to the external clock, the target capacitors sequentially participate in the charge conversion integration, wherein the total unit capacitance of each target capacitor remains unchanged.

16. The audio active noise reduction method of the composite ADC circuit according to claim 12, characterized in that: The order of the noise shaping and the bit value of the ADC quantizer satisfy the following relationship: SNR max =10*lg[1.5*(2L+1) / (PI 2L )*OSR (2L+1) *2 (N-1) ] Where, SNR max is the upper limit of the target signal-to-noise ratio, L is the order of noise shaping, OSR is the oversampling rate of the ADC quantizer, N is the bit value of the ADC quantizer, and PI is a constant.

17. An integrated circuit, characterized in that: A composite ADC circuit for audio active noise reduction function comprising the composite ADC circuit according to any one of claims 1 to 11.

18. An audio processing chip, comprising an integrated circuit, characterized in that: The integrated circuit includes the composite ADC circuit for audio active noise reduction function according to any one of claims 1 to 11.

19. A portable in-ear headset comprising a microphone and a speaker, characterized in that: The composite ADC circuit for audio active noise reduction function according to any one of claims 1 to 11 is electrically connected between the microphone and the speaker.

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