Low power counting method based on single slope adc

Abstract

The application provides a low-power consumption counting method based on a single-ramp ADC, which comprises a single-ramp ADC structure, wherein the single-ramp ADC structure comprises a comparator, a control circuit and a counter, and the comparator is connected with the control circuit and the counter. RM The application has the beneficial effects that: according to different comparator flip times, the counting method of upward counting or downward counting is adopted to only quantify the part between the set voltage V and the comparator flip point, the redundant part at the beginning of the quantization ramp is avoided, and the redundant power consumption generated by the redundant part is eliminated.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and in particular relates to a low-power counting method based on a single-slope ADC. Background Technology

[0002] CMOS image sensors typically consist of a pixel array, an analog-to-digital converter (ADC), timing control circuitry, and some peripheral circuitry. The ADC, which converts the analog signals of pixels into output digital signals, is a crucial component of current CMOS image sensors, and its performance plays a decisive role in the imaging performance of the sensor. Single-slope ADCs are widely used in various image sensors due to their simple structure, high integration, and good linearity.

[0003] With the development of high-speed, large-area CMOS image sensors, there is an increasing need for high-speed, high-sampling-rate, and high-resolution ADCs to convert image signals. However, this often leads to a corresponding increase in circuit power consumption. High power consumption shortens the device's battery life and reduces its lifespan. Furthermore, the heat generated by power consumption raises the chip temperature, leading to increased dark current and a decline in the image quality of the CMOS image sensor. Therefore, low-power design has become particularly critical.

[0004] In the traditional single-slope ADC working principle, its counting method is based on the slope voltage V. ramp When the counter starts to count as time changes, the reset signal fluctuates around a relatively fixed reset voltage during the quantization of the image sensor pixel reset signal. Users usually pay attention to the voltage value near the signal fluctuation, so the first half of the ramp quantization is a redundant part, and the counting power consumption of this part is also an unnecessary power consumption. Summary of the Invention

[0005] In view of this, the present invention aims to propose a low-power counting method based on a single-slope ADC to solve the problems of excessive redundant counting and high power consumption in the prior art.

[0006] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0007] A low-power counting method based on a single-slope ADC includes a single-slope ADC structure, which comprises a comparator, a control circuit, and a counter, wherein the comparator is connected to the control circuit and the counter.

[0008] The non-inverting input of the comparator is V. in The inverting input is V ramp V inV represents the signal voltage transmitted by the pixel array. ramp This represents a ramp voltage signal that changes over time. comp_out is the output of a comparator, which is connected to the input of a control circuit. The input of the control circuit is also connected to the input signal ramp_mid. The outputs of the control circuit are counter_en and counter_up / down, respectively. Both counter_en and counter_up / down are connected to a counter. counter_en is used to control the counting enable of the counter, and counter_up / down is used to control the counting direction of the counter.

[0009] Among them, V ramp >V in When comp_out is low, V ramp <V in When this occurs, comp_out is at a high level.

[0010] Furthermore, the counting method of the single-slope ADC structure includes the following:

[0011] The quantization reset voltage V is from t1 to t4. rst Phase, in which,

[0012] At time t1, V ramp Jump to the highest voltage V RH ;

[0013] V during stage t1~t2 ramp The voltage remains at its highest voltage V RH V during the t2 to t4 stage ramp The voltage signal decreases and drops to the quantization reset voltage V at time t4. rst The lowest voltage V of the stage RL V ramp Continuously with reset voltage V rst Make comparisons;

[0014] At time t2, V ramp >V in The comparator output comp_out is low.

[0015] At time t3, V ramp =V in The comparator output comp_out then toggles to a high level.

[0016] Quantization signal voltage V during the t4 to t7 stage rst ,in,

[0017] time t4 V ramp The voltage signal jumps to the highest voltage VRH ;

[0018] t4~t5 stage V ramp The voltage remains at its highest voltage V RH V in the t5 to t7 stage ramp Descending at the same slope in stages t2 to t3 and converging with V in Compare;

[0019] At time t5, V ramp >V in The comparator output comp_out is low at time t6, V ramp =V sig The comparator then toggles from low to high, where V sig This is the signal voltage.

[0020] Furthermore, the control circuit includes an XOR gate XOR1 and a transmission gate TG1. ramp_mid is connected to the A1 input of the XOR gate XOR1 and the control terminal of the transmission gate TG1. The comparator output comp_out is connected to the A2 input of the XOR gate XOR1 and the input of the transmission gate TG1. The output of the XOR gate XOR1 is counter_en, and the output of the transmission gate TG1 is counterup / down.

[0021] Furthermore, the control circuit controls the counter's counting enable via an XOR gate (XOR1), and the control method is as follows:

[0022] When counter_en is high, the clock signal counter starts counting; when counter_en is low, the counter stops counting.

[0023] During the t1 to t3 phase, ramp_mid remains low.

[0024] From t1 to t2, V ramp The voltage remains at its highest voltage V RH From t2 to t3, V ramp The voltage starts from the highest voltage V RH Decrease, at this time V ramp >V in When the comparator output comp_out is low, counter_en is also low.

[0025] If the comparator descends to the set voltage V during the ramp-down phase RM A flip occurred previously, i.e., V ramp <V inWhen comp_out jumps to a high level, this moment is recorded as time t8. When ramp_mid is low and comp_out is high, the XOR gate output counter_en is high, and the counter starts counting.

[0026] At time t3, ramp_mid goes high, comp_out goes high, the XOR gate output counter_en goes low, and the counter stops counting.

[0027] If the comparator descends to the set voltage V during the ramp-down phase RM If a flip occurs afterward, at time t3, ramp_mid goes high, and V... ramp >V in When the comparator output comp_out is low, the XOR gate output counter_en becomes high, and the counter starts counting.

[0028] t8 time V ramp =V in After V ramp <V in When the comparator output comp_out goes high, both ramp_mid and comp_out go high, the XOR gate output counter_en goes low, and the counter stops counting.

[0029] The counter operates between t8 and t3 or between t3 and t9, with the quantization reset voltage V. rst The process is defined as the reset quantization phase;

[0030] At time t4, V ramp It returns to its highest voltage V RH When ramp_mid goes low, V ramp >V in When the comparator output `comp_out` goes low, the quantization of the signal voltage V begins. sig ;

[0031] From t4 to t5, V ramp Maintain the highest voltage V RH During the period from t4 to t6, ramp_mid remains low and becomes high at time t6.

[0032] Homogeneous reset voltage V rst Similarly, if the comparator flips and the slope drops to the set voltage V, RM Previously, i.e., t 10 When the timer goes high, ramp_mid goes low, comp_out goes high, the XOR gate output counter_en goes high, and the counter starts counting.

[0033] At time t6, ramp_mid goes high, comp_out goes high, the XOR gate output counter_en goes low, and the counter stops counting.

[0034] If the comparator flips after the ramp descends to the middle, at time t6, ramp_mid becomes high, meaning the comparator output comp_out is low, the XOR gate output counter_en becomes high, and the counter starts counting.

[0035] t 11 When the time comparator output comp_out goes high, both ramp_mid and comp_out go high, the XOR gate outputs counter_en go low, and the counter stops counting.

[0036] The counter at t 10 to t6 or t6 to t 11 Working between them.

[0037] Furthermore, the control circuit controls the counting direction of the counter through the transmission gate TG1, and the control method is as follows:

[0038] When the transmission gate output counterup / down is high, the counter counts down; when the transmission gate output counterup / down is low, the counter counts up.

[0039] During the reset quantization phase, the quantization reset voltage V rst ,in,

[0040] When the comparator flips at time t8, it flips from low level to high level. That is, when the comparator flip occurs before time t3, ramp_mid is low level, transmission gate TG1 is turned on, and the comparator output comp_out can be transmitted to the output terminal to control the counter to count down between t8 and t3.

[0041] When the comparator flips at time t9, that is, when the comparator flips after time t3, at time t3, ramp_mid is high, transmission gate TG1 is closed, the output is low, and the counter counts up between t3 and t9.

[0042] Quantization signal voltage V sig This is the signal quantization stage, in which...

[0043] time t4 V ramp It jumps back to the highest voltage V RH When ramp_mid goes low, V ramp >V inThe comparator output comp_out goes low.

[0044] When t 10 When the time comparator flips, specifically before time t6, ramp_mid is low, transmission gate TG1 is turned on, and the comparator output comp_out can be transmitted to the output terminal to control the counter at time t6. 10 Count downwards from t6;

[0045] When t 11 The time comparator flips, meaning the flip occurs after time t6. 11 When ramp_mid is high, transmission gate TG1 is closed, the output is low, and the counter is between t6 and t7. 11 Count upwards from the beginning.

[0046] Furthermore, the result of the counter during the reset quantization phase is related to (V RM -V rst The result in the signal quantization stage is directly proportional to (V). RM -V sig Proportional to;

[0047] Among them, the reset voltage V rst It is the reset quantization stage V in The voltage, signal voltage V sig It is V in Voltage during the signal quantization phase;

[0048] The final quantization result is the difference between the result of the reset quantization stage and the result of the signal quantization stage. The formula for the difference is: (V RM -V sig )-(V RM -V rst ) = V rst -V sig .

[0049] Compared with existing technologies, the low-power counting method based on a single-slope ADC described in this invention has the following advantages:

[0050] The low-power counting method based on a single-slope ADC described in this invention uses either up-counting or down-counting modes depending on the comparator toggle time, and only quantizes the set voltage V. RM The portion between the comparator flip point avoids the redundant portion at the beginning of the quantization ramp, thereby eliminating the excess power consumption generated by the redundant portion. Attached Figure Description

[0051] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0052] Figure 1 This is a schematic diagram of the single-slope ADC structure according to an embodiment of the present invention;

[0053] Figure 2 This is a schematic diagram of the control circuit structure and its operating timing as described in an embodiment of the present invention;

[0054] Figure 3 This is a schematic diagram showing the power consumption ratio of the counter under different output code values ​​for the scheme of the present invention and the conventional scheme described in the embodiments of the present invention;

[0055] Figure 4 This is a schematic diagram illustrating the working principle of the present invention as described in an embodiment of the present invention. Detailed Implementation

[0056] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0057] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0058] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0059] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0060] In this embodiment, the schematic diagram of the single-slope ADC structure of the present invention is as follows: Figure 1 As shown, it consists of a comparator, a control circuit, and an up / down counter. The up / down counter can increment or decrement. The non-inverting input of the comparator is V. in The inverting input is V ramp V in V represents the signal voltage transmitted by the pixel array. ramp This represents a ramp voltage signal that varies with time, where comp_out is the comparator output, V ramp >V in When comp_out is low, V ramp <V in When the counter is active, comp_out is high. The control circuit controls the enable and direction of the counter's counting. The inputs of the control circuit are the comparator's output comp_out and an input signal ramp_mid.

[0061] This invention addresses the problem of excessive power consumption caused by existing single-slope ADCs that can only start counting from the initial stage of the slope during quantization. It designs a method that only consumes power at a preset voltage value (set voltage V). RM This invention employs a counting method that counts between the comparator's topping point and the comparator's flip point, ensuring accurate counting through counting in different directions. This low-power counting method is a key feature of the invention.

[0062] This invention quantizes the set voltage V using either an up-counting or down-counting method, depending on the different comparator toggle times. RM The portion between the comparator flip point avoids the redundant portion at the beginning of the quantization ramp, thereby eliminating the excess power consumption generated by the redundant portion.

[0063] In V ramp Descending to V RM (Set voltage V) RM Before that, ramp_mid remained low, V ramp Drop to the set voltage V RM Then, ramp_mid goes high, setting the voltage V. RM Let V be a voltage at a certain point in the middle of the selected slope, between V RH With V RL Between. The outputs of the control circuit are counter_en and counter_up / down. counter_en controls the counting enable of the counter, and counter_up / down controls the counting direction of the counter. The counter detects that ramp_mid has toggled from low to high (V ramp Descending to VRM ) or the comparator flips from low to high (V ramp Descending to V in The signal is counted, and the actual result obtained is V. RM and V in The difference information between them includes only noise and non-ideal effects. Compared with the traditional counting method that starts quantization from the initial stage of the ramp, this eliminates the redundant part of the first half of the ramp quantization, thus avoiding unnecessary power consumption in this part. The specific structure and operation are described below.

[0064] like Figure 4 As shown, the ramp signal in this invention is consistent with the traditional design, and the quantization reset voltage V is used from t1 to t4. rst During the phase t1, the voltage V generated by the ramp generator is... ramp Jump to the highest voltage V RH V during the t1 to t2 stage ramp The voltage remains at its highest voltage V RH V during the t2 to t4 stage ramp The voltage signal decreases and drops to the quantization reset voltage V at time t4. rst The lowest voltage V of the stage RL V ramp Continuously with reset voltage V rst Compare; at time t2, V ramp >V in The comparator output comp_out is low at time t3, V ramp =V in The comparator output comp_out then flips to high; the quantization signal voltage V during the t4 to t7 period... sig V at time t4 ramp The voltage signal jumps to the highest voltage V RH V during the t4 to t5 stage ramp The voltage remains at its highest voltage V RH V in the t5 to t7 stage ramp Descending at the same slope in stages t2 to t3 and converging with V in Compare; at time t5, V ramp >V in The comparator output comp_out is low at time t6, V ramp =V sig The comparator then toggles from low to high, where V rst V is the reset voltage. sig This is the signal voltage.

[0065] The working process of this technology is as follows: Figure 2As shown, (a) is the main structure of the control circuit, and (b) is a timing diagram. The main structure of the control circuit consists of an XOR gate (XOR1) and a transmission gate (TG1). ramp_mid is connected to the A1 input of the XOR gate (XOR1) and the control terminal of the transmission gate (TG1). The comparator output comp_out is connected to the A2 input of the XOR gate (XOR1) and the input of the transmission gate (TG1). The output of the XOR gate (XOR1) is counter_en, and the output of the transmission gate (TG1) is counterup / down. At times t3 and t6, V... ramp Descending to V RM The moment. V RM Located in V RH and V RL Between, typically V RM =(V RH +V RL ) / 2.

[0066] The circuit structure of this invention controls the counting enable of the counter through an XOR gate (XOR1). Specifically, when counter_en is high, the clock signal counter starts counting; when counter_en is low, the counter stops counting. From t1 to t3, ramp_mid remains low; from t1 to t2, V... ramp Maintain the highest voltage V RH From t2 to t3, V ramp Start from V RH Decrease, at this time V ramp >V in When the comparator output `comp_out` is low, `counter_en` is also low. If the comparator drops to V on the ramp... RM A flip occurred previously, i.e., V ramp <V in At time t8, `comp_out` jumps high, and `comp_out` goes high. The XOR gate output `counter_en` goes high, and the counter starts counting. At time t3, `ramp_mid` goes high, `comp_out` goes high, and the XOR gate output `counter_en` goes low, stopping the counter. If the comparator descends to V... RM If a flip occurs afterward, at time t3, ramp_mid goes high, and V... ramp >V in When the comparator output `comp_out` is low, the XOR gate output `counter_en` goes high, and the counter starts counting; at time t8, V ramp =V in After Vramp <V in When the comparator output `comp_out` goes high, both `ramp_mid` and `comp_out` go high, and the XOR gate output `counter_en` goes low, stopping the counter. The timing is shown in (b). The counter is only active between t8 and t3 or between t3 and t9; redundant parts do not need to count. This is due to the quantization reset voltage V. rst The process.

[0067] At time t4, V ramp It returns to its highest voltage V RH When ramp_mid goes low, V ramp >V in When the comparator output `comp_out` goes low, the quantization of the signal voltage V begins. sig From t4 to t5, V ramp Maintain the highest voltage V RH During the t4 to t6 phase, ramp_mid remains low and becomes high at time t6. (Isoquantization V) rst Similarly, if the comparator flips as it descends to V on the ramp... RM Previously, that is, at t 10 At time t6, ramp_mid becomes high, comp_out becomes high, and the XOR gate output counter_en becomes high, starting the counter. At time t7, ramp_mid becomes high, comp_out becomes high, and the XOR gate output counter_en becomes low, stopping the counter. If the comparator flips after the ramp has descended to the middle, at time t6, ramp_mid becomes high, comp_out becomes low, and the XOR gate output counter_en becomes high, starting the counter. 11 When the time comparator output `comp_out` goes high, and both `ramp_mid` and `comp_out` are high, the XOR gate outputs `counter_en` low, and the counter stops counting. Only when `t`... 10 to t6 or t6 to t 11 The counter operates between these points.

[0068] The circuit structure of this invention controls the counting direction of the counter through the transmission gate TG1. Specifically, the control method is as follows: when the transmission gate output `counterup / down` is high, the counter counts downwards; when the transmission gate output `counterup / down` is low, the counter counts upwards. Quantization reset voltage V rstDuring the phase, when the comparator flips at time t8, changing from low to high (i.e., the flip occurs before time t3), ramp_mid is low, transmission gate TG1 is on, and the comparator output comp_out can be transmitted to the output terminal, controlling the counter to count downwards between t8 and t3. When the comparator flips at time t9, after time t3, ramp_mid is high at t3, transmission gate TG1 is off, the output terminal is low, and the counter counts upwards between t3 and t9. Counting in different directions ensures the accuracy of the count. Then, the signal voltage V is quantized. sig V at time t4 ramp It jumps back to the highest voltage V RH When ramp_mid goes low, V ramp >V in The comparator output `comp_out` goes low. When t... 10 When the time comparator flips, specifically before time t6, ramp_mid is low, transmission gate TG1 is turned on, and the comparator output comp_out can be transmitted to the output terminal to control the counter at time t6. 10 Count downwards from t to t6; when t 11 The time comparator flips, meaning the flip occurs after time t6. 11 When ramp_mid is high, transmission gate TG1 is closed, the output is low, and the counter is between t6 and t7. 11 Count upwards from the beginning.

[0069] Based on the above control, the quantization result of the counter during the reset phase is compared with (V RM -V rst The result is directly proportional to (V) during the signal quantization stage. RM -V sig It is directly proportional to V, where V rst It is the reset quantization stage V in voltage, V sig It is V in The voltage during the signal quantization stage. The final quantization result is the difference between the quantization result during the reset stage and the quantization result during the signal stage, i.e., (V RM -V sig )-(V RM -V rst ) = V rst -V sig Traditional counters require counting stages V. RH -V sig and V RH -V rst Therefore, compared with the traditional method, it reduces 2×(V)RH –V RM The counting of voltage values ​​effectively reduces power consumption.

[0070] The main technical solution of this invention reduces the power consumption of the counter section in the ADC circuit. To verify the effectiveness of this invention, the power consumption of one counter flip is set to P0, while the counter output code value in the traditional solution is N. i When the counting period is N tr The power consumption is P tr =N tr ×P0; The counter output code value of this invention is N i When the counting period is N lp The power consumption is P lp =N lp ×P0. The table below shows the power consumption ratio P between the present invention and the conventional solution under the same output code value obtained through simulation of a 10-bit ADC. lp / P tr The correspondence.

[0071] Figure 3 This is a graph showing the power consumption ratio of the counter under different output code values ​​for the present invention and the traditional solution. The horizontal axis represents the output code value, and the vertical axis represents the power consumption ratio. It can be seen that when the quantization code value is lower than 256, the power consumption of the present technology is significantly reduced compared to the traditional method, by less than 60%. As the quantization code value increases, the advantage of low power consumption technology will decrease, but when the code value reaches 1024, there is still a 17.75% power consumption optimization.

[0072] Furthermore, the counting method in this invention can be applied to single-slope and multi-slope counting, achieving correlated double sampling and correlated multiple sampling. In the above implementation, it is only necessary to adjust the pulse signal of the UP / DOWN counter counting direction according to whether the sampling slope is operating in reset quantization or signal quantization and according to the subsequent quantization calculation method. In the above implementation, the technology of this invention can also reduce redundant counting and reduce power consumption.

[0073] This invention proposes a low-power technique to reduce redundant counting, which only quantizes the set voltage V. RM The section between the comparator flip point and the ramp point eliminates the redundant quantization process in the front section of the ramp, thereby reducing power consumption.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power counting method based on a single-slope ADC, characterized in that: The invention includes a single-slope ADC structure, which comprises a comparator, a control circuit, and a counter, wherein the comparator is connected to the control circuit and the counter. The non-inverting input of the comparator is V. in The inverting input is V ramp V in V represents the signal voltage transmitted by the pixel array. ramp This represents a ramp voltage signal that changes over time. comp_out is the output of a comparator, which is connected to the input of a control circuit. The input of the control circuit is also connected to the input signal ramp_mid. The outputs of the control circuit are counter_en and counter_up / down, respectively. Both counter_en and counter_up / down are connected to a counter. counter_en is used to control the counting enable of the counter, and counter_up / down is used to control the counting direction of the counter. Among them, V ramp >V in When comp_out is low, V ramp <V in At that time, comp_out is high. The control circuit includes an XOR gate XOR1 and a transmission gate TG1. ramp_mid is connected to the A1 input of the XOR gate XOR1 and the control terminal of the transmission gate TG1. The comparator output comp_out is connected to the A2 input of the XOR gate XOR1 and the input of the transmission gate TG1. The output of the XOR gate XOR1 is counter_en, and the output of the transmission gate TG1 is counter up / down. The control circuit controls the counter's counting enable via an XOR gate (XOR1). The control method is as follows: When counter_en is high, the clock signal counter starts counting; when counter_en is low, the counter stops counting. During the t1 to t3 phase, ramp_mid remains low. From t1 to t2, V ramp The voltage remains at its highest voltage V RH From t2 to t3, V ramp The voltage starts from the highest voltage V RH Decrease, at this time V ramp >V in When the comparator output comp_out is low, counter_en is also low. If the comparator descends to the set voltage V during the ramp-down phase RM A flip occurred previously, i.e., V ramp =V in， After V ramp <V in When comp_out jumps to a high level, this moment is recorded as time t8. When ramp_mid is low and comp_out is high, the XOR gate output counter_en is high, and the counter starts counting. At time t3, ramp_mid goes high, comp_out goes high, the XOR gate output counter_en goes low, and the counter stops counting. If the comparator flips after the ramp has reached the set voltage V RM , then at time t3, ramp mid goes high, and V ramp >V in , the comparator output comp out goes low, and the XOR output counter en goes high, and the counter starts counting. t8 time V ramp =V in After V ramp <V in When the comparator output comp_out goes high, both ramp_mid and comp_out go high, the XOR gate output counter_en goes low, and the counter stops counting. The counter works between t8 and t3 or t3 and t9 for quantizing the reset voltage V rst defined as the reset quantization phase. at time t4, V ramp again becomes the highest voltage V RH , ramp mid becomes low, at which time V ramp >V in , the comparator output comp out becomes low, and the quantization signal voltage V sig begins to be measured; t4 to t5 phase, V ramp highest voltage V RH , t4 to t6 phase, ramp mid remains low, becomes high at t6 Equalization reset voltage V rst The same, if the comparator flip in the ramp down to the set voltage V RM Before, namely t 10 The moment becomes high level, ramp_mid is low level, comp_out is high level, and the exclusive or gate output counter_en is high level, and the counter starts counting. At time t6, ramp_mid goes high, comp_out goes high, the XOR gate output counter_en goes low, and the counter stops counting. If the comparator flips after the ramp descends to the middle, at time t6, ramp_mid becomes high, meaning the comparator output comp_out is low, the XOR gate output counter_en becomes high, and the counter starts counting. t 11 The moment comparator output comp_out becomes high, ramp_mid and comp_out are high at the same time, the output of the XOR gate is counter_en low, and the counter stops counting; The counter works between t 10 to t6 or t6 to t 11 ; The control circuit controls the counting direction of the counter through transmission gate TG1, and the control method is as follows: When the output counter up / down of the transmission gate is high, the counter counts down; when the output counter up / down of the transmission gate is low, the counter counts up. The reset quantization stage, quantizes the reset voltage V rst wherein, When the comparator flips at time t8, it flips from low level to high level. That is, when the comparator flip occurs before time t3, ramp_mid is low level, transmission gate TG1 is turned on, and the comparator output comp_out can be transmitted to the output terminal to control the counter to count down between t8 and t3. When the comparator flips at time t9, that is, when the comparator flips after time t3, at time t3, ramp_mid is high, transmission gate TG1 is closed, the output is low, and the counter counts up between t3 and t9. Quantized signal voltage V sig is a signal quantization stage, wherein, t4 V ramp again to the highest voltage V RH , ramp mid goes low, and V ramp >V in , the comparator output comp out goes low; When t 10 When the time comparator flips, specifically before time t6, ramp_mid is low, transmission gate TG1 is turned on, and the comparator output comp_out can be transmitted to the output terminal to control the counter at time t6. 10 Count downwards from t6; When t 11 The time comparator flips, meaning the flip occurs after time t6. 11 When ramp_mid is high, transmission gate TG1 is closed, the output is low, and the counter is between t6 and t7. 11 Count upwards from the beginning.

2. The low-power counting method based on a single-slope ADC according to claim 1, characterized in that: The counting method of a single-slope ADC structure includes the following: The quantization reset voltage V is from t1 to t4. rst Phase, in which, At time t1, V ramp Jump to the highest voltage V RH ; V during t1~t2 ramp The voltage remains at its highest voltage V RH V during the t2~t4 stage ramp The voltage signal decreases and drops to the quantization reset voltage V at time t4. rst The lowest voltage V of the stage RL V ramp Continuously with reset voltage V rst Make comparisons; At time t2, V ramp >V in The comparator output comp_out is low. At time t3, V ramp =V in The comparator output comp_out then toggles to a high level. Quantization signal voltage V during t4~t7 stages sig ,in, time t4 V ramp The voltage signal jumps to the highest voltage V RH ; t4~t5 stage V ramp The voltage remains at its highest voltage V RH V in the t5~t7 stage ramp Descending at the same slope in stages t2 to t3 and converging with V in Compare; At time t5, V ramp >V in The comparator output comp_out is low at time t6, V ramp =V sig The comparator then toggles from low to high, where V sig This is the signal voltage.

3. The low-power counting method based on a single-slope ADC according to claim 1, characterized in that: Based on the control methods for enabling and controlling the counting direction, the result of the counter during the reset and quantization phase is related to (V). RM -V rst The result in the signal quantization stage is directly proportional to (V). RM -V sig Proportional to; Among them, the reset voltage V rst It is the reset quantization stage V in The voltage, signal voltage V sig It is V in Voltage during the signal quantization phase; The final quantization result is the difference between the result of the reset quantization stage and the result of the signal quantization stage. The formula for the difference is: (V RM -V sig )-(V RM -V rst )=V rst -V sig .

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