Start-up circuit for bandgap reference circuit

Abstract

The application discloses a starting circuit for a band gap reference circuit, the band gap reference circuit is a voltage mode band gap reference circuit, comprising an operational amplifier, a first MOS tube, a first branch and a second branch, the starting circuit comprises: a pull-up resistor and a second MOS tube, the first end of the pull-up resistor is connected with a power supply voltage, the second end is connected with the second end of the second MOS tube, the first end of the second MOS tube is connected with a ground potential, and the control end is controlled by a driving signal; and a control tube, the first end of the control tube is connected with an output node, the second end is connected with the control end of the first MOS tube, and the control end is connected with the second end of the pull-up resistor.The application introduces a certain negative feedback by setting the control tube MNS while pulling down the gate potential of MP1, and the band gap reference voltage monotonously rises in the whole starting process, so that the problem of overshoot of the band gap reference voltage of the starting circuit in the power-on process can be effectively solved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a startup circuit for a bandgap reference circuit. Background Technology

[0002] In large-scale integrated circuit systems, bandgap reference circuits are an essential component. They provide the integrated circuit system with a reference voltage and current bias to minimize temperature drift. Therefore, the startup circuit used for the bandgap reference circuit directly affects whether it can start up normally and operate stably.

[0003] In existing technologies, an NMOS transistor is typically used to pull the gate of the PMOS transistor in the bandgap reference circuit down to ground (GND) to start the bandgap reference circuit. However, this startup method can easily cause excessive pull-down of the PMOS transistor's gate potential, resulting in an insufficient bandgap reference voltage V. BG Overshoot.

[0004] Therefore, in view of the above-mentioned technical problems, it is necessary to provide a startup circuit for a bandgap reference circuit. Summary of the Invention

[0005] In view of this, the object of the present invention is to provide a startup circuit for a bandgap reference circuit, so as to solve the problem of bandgap reference voltage V during startup. BG The problem of overshoot.

[0006] To achieve the above objectives, an embodiment of the present invention provides the following technical solution:

[0007] A startup circuit for a bandgap reference circuit, wherein the bandgap reference circuit is a voltage-mode bandgap reference circuit, includes an operational amplifier, a first MOSFET, a first branch, and a second branch. The first terminal of the first MOSFET is connected to a power supply voltage, and the second terminal is connected to an output node. The first branch includes a first bipolar transistor and several first matching resistors, and the second branch includes a second bipolar transistor and several second matching resistors. The first and second input terminals of the operational amplifier are respectively connected to the first and second branches, and the output terminal is connected to the control terminal of the first MOSFET. The output node is used to output the bandgap reference voltage V. BG The startup circuit includes:

[0008] A pull-up resistor and a second MOSFET are provided. The first end of the pull-up resistor is connected to the power supply voltage, and the second end is connected to the second end of the second MOSFET. The first end of the second MOSFET is connected to ground potential. The control terminal is controlled by a drive signal.

[0009] The control transistor has its first end connected to the output node, its second end connected to the control terminal of the first MOS transistor, and the control terminal connected to the second end of the pull-up resistor.

[0010] In one embodiment, the first MOS transistor is a PMOS transistor, with a first terminal as the source, a second terminal as the drain, and a control terminal as the gate; and / or,

[0011] Both the control transistor and the second MOS transistor are NMOS transistors, with the first terminal being the source, the second terminal being the drain, and the control terminal being the gate.

[0012] In one embodiment, the control terminal of the second MOS transistor is connected to the output node, and the drive signal is the bandgap reference voltage V. BG .

[0013] In one embodiment, the startup circuit further includes a current replication unit, comprising a third MOS transistor and a fourth MOS transistor, wherein the third MOS transistor is a PMOS transistor and the fourth MOS transistor is an NMOS transistor;

[0014] The source of the third MOS transistor is connected to the power supply voltage, the gate is connected to the control terminal of the first MOS transistor, the drain is connected to the drain of the fourth MOS transistor, the source of the fourth MOS transistor is connected to ground potential, and the gate and drain are shorted and connected to the control terminal of the second MOS transistor.

[0015] In one embodiment, the starting unit further includes a voltage limiting unit, the first end of which is connected to the control terminal of the control tube, and the second end of which is connected to ground potential. The voltage limiting unit includes a current limiting device or multiple current limiting devices connected in series.

[0016] In one embodiment, the voltage limiting unit includes a fifth MOS transistor and a sixth MOS transistor, both of which are NMOS transistors;

[0017] The source of the fifth MOS transistor is connected to ground, the drain is shorted to the gate and connected to the source of the sixth MOS transistor, and the drain and gate of the sixth MOS transistor are shorted to the control terminal of the control transistor MNS.

[0018] In one embodiment, the first branch includes first matching resistors R1a and R1b and a first bipolar transistor, wherein the first end of the first matching resistor R1a is connected to the second end of the first MOS transistor, the second end is connected to the first end of the first matching resistor R2a, the second end of the first matching resistor R2a is connected to the second end of the first bipolar transistor, the control terminal of the first bipolar transistor is shorted to the second end, and the first end is connected to ground potential.

[0019] The second branch includes a second matching resistor R2 and a second bipolar transistor. The first end of the second matching resistor R2 is connected to the second end of the first MOS transistor, the second end is connected to the second end of the second bipolar transistor, the control terminal of the second bipolar transistor is shorted to the second end, and the first end is connected to ground potential.

[0020] The technical solution provided by one embodiment of the present invention is as follows:

[0021] A startup circuit for a bandgap reference circuit, wherein the bandgap reference circuit is a current-mode bandgap reference circuit, comprising an operational amplifier, a first MOSFET, a seventh MOSFET, a first branch, a second branch, and a current-to-voltage conversion circuit. The first terminals of the first and seventh MOSFETs are both connected to a power supply voltage, and their second terminals are respectively connected to the first and second input terminals of the operational amplifier. Control terminals of both are connected to the output terminal of the operational amplifier. The first branch includes a first bipolar transistor and several first matching resistors, and the second branch includes a second bipolar transistor and several second matching resistors. The first branch is connected between the first input terminal of the operational amplifier and ground potential, and the second branch is connected between the second input terminal of the operational amplifier and ground potential. The current-to-voltage conversion circuit outputs a bandgap reference voltage V. BG The startup circuit includes:

[0022] A pull-up resistor and a second MOSFET are provided. The first end of the pull-up resistor is connected to the power supply voltage, and the second end is connected to the second end of the second MOSFET. The first end of the second MOSFET is connected to ground potential. The control terminal is controlled by a drive signal.

[0023] Several control transistors are provided, wherein the first end of each control transistor is connected to the first or second input terminal of an operational amplifier, the second end is connected to the control terminal of a first or seventh MOS transistor, and the control terminal is connected to the second end of a pull-up resistor.

[0024] In one embodiment, both the first and seventh MOS transistors are PMOS transistors, with the first terminal being the source, the second terminal being the drain, and the control terminal being the gate; and / or,

[0025] Both the control transistor and the second MOS transistor are NMOS transistors, with the first terminal being the source, the second terminal being the drain, and the control terminal being the gate.

[0026] In one embodiment, the control terminal of the second MOS transistor is connected to the output node, and the drive signal is the bandgap reference voltage V. BG .

[0027] In one embodiment, the startup circuit further includes a current replication unit, comprising a third MOS transistor and a fourth MOS transistor, wherein the third MOS transistor is a PMOS transistor and the fourth MOS transistor is an NMOS transistor;

[0028] The source of the third MOS transistor is connected to the power supply voltage, the gate is connected to the control terminal of the first MOS transistor, the drain is connected to the drain of the fourth MOS transistor, the source of the fourth MOS transistor is connected to ground potential, and the gate and drain are shorted and connected to the control terminal of the second MOS transistor.

[0029] In one embodiment, the starting unit further includes a voltage limiting unit. The first end of the voltage limiting unit is connected to the control terminal of the control tube, and the second end is connected to the ground potential. The voltage limiting unit includes a current limiting device or multiple current limiting devices connected in series.

[0030] In one embodiment, the voltage limiting unit includes a fifth MOS transistor and a sixth MOS transistor, both of which are NMOS transistors;

[0031] The source of the fifth MOS transistor is connected to ground, the drain is shorted to the gate and connected to the source of the sixth MOS transistor, and the drain and gate of the sixth MOS transistor are shorted to the control terminal of the control transistor MNS.

[0032] In one embodiment, the first branch includes first matching resistors R1a and R1b and a first bipolar transistor. The first end of the first matching resistor R1a is connected to the second end of the first MOSFET, and the second end is connected to the second end of the first bipolar transistor. The control terminal of the first bipolar transistor is shorted to the second end, and the first end is connected to ground potential. The first end of the first matching resistor R1b is connected to the second end of the first MOSFET, and the second end is connected to ground potential.

[0033] The second branch includes a second matching resistor R2 and a second bipolar transistor. The first end of the second matching resistor R2 is connected to the second end of the seventh MOS transistor, and the second end is connected to ground potential. The second end of the second bipolar transistor is connected to the second end of the seventh MOS transistor. The control terminal is shorted to the second end, and the first end is connected to ground potential.

[0034] In one embodiment, the current-to-voltage conversion circuit includes an eighth MOS transistor and a first resistor. The eighth MOS transistor is a PMOS transistor, with its source connected to the power supply voltage, its drain connected to the output node, and its gate connected to the control terminal of the first MOS transistor. The first terminal of the first resistor is connected to the output node, and the second terminal is connected to ground potential.

[0035] The present invention has the following beneficial effects:

[0036] This invention introduces a certain amount of negative feedback by controlling the setting of the MNS transistor, which pulls down the gate potential of MP1. The bandgap reference voltage rises monotonically throughout the startup process, which can effectively solve the problem of bandgap reference voltage overshoot during power-up of the startup circuit, avoid false triggering caused by bandgap reference voltage overshoot, and improve the reliability and stability of the circuit. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 is a circuit diagram of a voltage-mode bandgap reference circuit in the prior art;

[0039] Figure 2 is a schematic diagram of a start-up circuit for a bandgap reference circuit in a one-to-one ratio according to the present invention;

[0040] Figure 3 is a waveform diagram of bandgap reference voltage V when the start-up circuit in the one-to-one ratio of the present invention is powered on rapidly BG ;

[0041] Figure 4 is a schematic diagram of a start-up circuit for a voltage-mode bandgap reference circuit in Embodiment 1 of the present invention;

[0042] Figure 5 is a waveform diagram of bandgap reference voltage V when the start-up circuit in Embodiment 1 of the present invention is powered on rapidly BG ;

[0043] Figure 6 is a schematic diagram of a start-up circuit for a current-mode bandgap reference circuit in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0044] To enable those skilled in the art to better understand the technical solutions in the present invention, the following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort shall fall within the protection scope of the present invention.

[0045] In the description herein, unless otherwise specified and limited, the terms "connected" and "connected" shall be understood in a broad sense. For example, they may be direct connection or indirect connection through an intermediate medium. Those of ordinary skill in the art can understand the specific meanings of the above terms according to specific situations.

[0046] Reference Figure 1It is a schematic diagram of a voltage-mode bandgap reference circuit in the prior art, which comprises an operational amplifier A, a first MOS transistor MP1, a first branch and a second branch. The first MOS transistor MP1 is a PMOS transistor, whose source is connected to the power supply voltage V DD , the drain is connected to an output node. The first branch comprises a first bipolar transistor Q1 and first matching resistors R1a and R1b, the second branch comprises a second bipolar transistor Q2 and a plurality of matching resistors R2. A first input terminal vp and a second input terminal vn of the operational amplifier A are connected to the first branch and the second branch respectively, an output terminal of the operational amplifier A is connected to the gate of the first MOS transistor MP1, and the output node is configured to output a bandgap reference voltage V BG .

[0047] Specifically, the first branch comprises first matching resistors R1a, R1b and a first bipolar transistor Q1, wherein a first terminal of the first matching resistor R1a is connected to the second terminal of the first MOS transistor MP1, a second terminal of the first matching resistor R1a is connected to the first terminal of a second matching resistor R2a, the second terminal of the second matching resistor R2a is connected to the second terminal of the first bipolar transistor Q1, the control terminal of the first bipolar transistor Q1 is short-circuited with the second terminal, and the first terminal is connected to the ground potential;

[0048] The second branch comprises a second matching resistor R2 and a second bipolar transistor Q2, wherein a first terminal of the second matching resistor R2 is connected to the second terminal of the first MOS transistor MP1, a second terminal of the second matching resistor R2 is connected to the second terminal of the second bipolar transistor Q2, the control terminal of the second bipolar transistor Q2 is short-circuited with the second terminal, and the first terminal is connected to the ground potential.

[0049] Wherein, Q1 and Q2 are NPN-type transistors for illustration, the first terminal is an emitter, the second terminal is a collector, and the control terminal is a base. In other embodiments, PNP-type transistors can also be used.

[0050] The principle that the voltage-mode bandgap reference circuit generates the bandgap reference voltage V BG belongs to the prior art, and will not be repeated in the present invention.

[0051] Comparative Example:

[0052] Ref Figure 2 erence is a schematic diagram of a starting circuit for a bandgap reference circuit in a comparative example of the present invention, the bandgap reference circuit is a voltage-mode bandgap reference circuit 11, whose circuit diagram refers to Figure 1 , which will not be repeated here.

[0053] The starting circuit 12' in this comparative example comprises:

[0054] a pull-up resistor R0 and a second MOS transistor MN1, a first terminal of the pull-up resistor R0 and the power supply voltage V DDis connected, a second end of the second MOS transistor MN1 is connected to a second end of the second MOS transistor MN1, a first end of the second MOS transistor MN1 is connected to ground potential, and a control end is connected to an output node;

[0055] a control transistor MNS, a first end of the control transistor MNS is connected to ground potential, a second end of the control transistor MNS is connected to a control end of a first MOS transistor MP1, and a control end of the control transistor MNS is connected to a second end of the pull-up resistor R0.

[0056] wherein, the second MOS transistor MN1 and the control transistor MNS are both NMOS transistors, the first end is a source, the second end is a drain, and the control end is a gate.

[0057] In this comparative example, during the startup of the bandgap reference circuit, the control transistor MNS directly pulls down the gate of the first MOS transistor MP1 to ground potential, which easily causes excessive pull-down of the gate potential of MP1, resulting in the bandgap reference voltage V BG to overshoot.

[0058] In addition, the gate of the control transistor MNS is pulled up by the pull-up resistor R0, and the fed-back V BG controls the second MOS transistor MN1 to pull down the potential, which lacks amplitude limiting for the gate potential of the control transistor MNS, which easily causes the gate potential of MNS to rise too high, makes the pull-down capability of MNS too strong, and further causes V BG to overshoot.

[0059] Refer to Figure 3 , which shows the waveform diagram of the bandgap reference voltage V BG when the startup circuit is powered on rapidly (1μs) in this comparative example. It can be found that the bandgap reference voltage V BG has an obvious overshoot.

[0060] Example 1:

[0061] Refer to Figure 4 , which shows a schematic diagram of a startup circuit for a bandgap reference circuit in this example. The bandgap reference circuit is a voltage-mode bandgap reference circuit 11, and its circuit diagram refers to Figure 1 , which will not be repeated herein.

[0062] The startup circuit 12 in this example includes:

[0063] a pull-up resistor R0 and a second MOS transistor MN1, a first end of the pull-up resistor R0 is connected to a power supply voltage V DD , a second end of the pull-up resistor R0 is connected to a second end of the second MOS transistor MN1, a first end of the second MOS transistor MN1 is connected to ground potential, and a control end is controlled by a driving signal;

[0064] The control transistor MNS has its first terminal connected to the output node and its second terminal connected to the control terminal of the first MOSFET MP1. The control terminal is connected to the second terminal of the pull-up resistor R0.

[0065] Among them, the control transistor and the second MOS transistor MN1 are both NMOS transistors, with the first terminal being the source, the second terminal being the drain, and the control terminal being the gate.

[0066] Preferably, the startup circuit of this embodiment further includes a current replication unit, including a third MOS transistor MP2 and a fourth MOS transistor MN2, wherein the third MOS transistor MP2 is a PMOS transistor and the fourth MOS transistor MN2 is an NMOS transistor.

[0067] Specifically, the source of the third MOSFET MP2 is connected to the power supply voltage V. DD The gate of the first MOSFET MP1 is connected to the control terminal, the drain of the fourth MOSFET MN2 is connected to the drain of the fourth MOSFET MN2, the source of the fourth MOSFET MN2 is connected to ground, and the gate and drain are shorted together and connected to the control terminal of the second MOSFET MN1.

[0068] Furthermore, the startup unit in this embodiment also includes a voltage limiting unit. The first end of the voltage limiting unit is connected to the control terminal of the control transistor, and the second end is connected to the ground potential. The voltage limiting unit includes a current limiting device or multiple current limiting devices connected in series. The current limiting device can be a MOSFET, a diode, etc.

[0069] Specifically, the voltage limiting unit in this embodiment includes a fifth MOS transistor MN3 and a sixth MOS transistor MN4, both of which are NMOS transistors. The source of the fifth MOS transistor MN3 is connected to ground, and its drain is shorted to its gate and connected to the source of the sixth MOS transistor MN4. The drain and gate of the sixth MOS transistor MN4 are shorted and shorted to the control terminal of the control transistor MNS.

[0070] In this embodiment, the source of the control transistor MNS is connected to the output node (i.e., the bandgap reference voltage V). BG The circuit is connected in series with the second MOSFET MN1, and the gate drive signal of the second MOSFET MN1 has been optimized, which can effectively solve the problem of the bandgap reference voltage V during the power-on process of the startup circuit. BG The problem of overshoot.

[0071] Upon initial power-up, the bandgap reference circuit is not activated, there is no current in MP2, and both MN1 and MN2 are cut off. The gate potential of the control transistor MNS is pulled up through R0, causing MNS to conduct. At this time, vn and vp are still at low potentials, so the gate potential of MP1 is pulled low through the conduction of MNS, allowing MP1 to conduct. After MP1 conducts, current begins to flow in transistors Q1 and Q2, and the bandgap reference voltage V... BG It begins to rise, at which point V BGis low, MNS continues pulling down the gate of MP1, the current in MP1 further increases, and V BG further rises. The current in MP1 is copied by MP2 according to a certain proportion, so that the gate potentials of MN1 and MN2 start to rise. When the current in MP1 increases to a certain extent, MN1 pulls down the gate potential of MNS to turn it off, thus the start-up circuit is turned off, and the bandgap reference circuit enters the op-amp controlled loop response.

[0072] Furthermore, the gate potential of MNS can be clamped by MN3 and MN4 to prevent it from being pulled up too high, which would cause the gate potential of MP1 to be pulled down rapidly and further result in V BG voltage overshoot. In addition, MN3 and MN4 are connected in series, and the clamping voltage is 2V GS , which can avoid the problem of start-up failure caused by premature turn-off of MNS due to the rise of the source potential of MNS (V BG ).

[0073] On the other hand, MNS provides direct negative feedback control from V BG to the gate potential of MP1. When V BG rises rapidly, MNS connected in a common-gate amplification configuration simultaneously raises the gate potential of MP1, weakens the conduction capability of MP1, and thus slows down the rise rate of V BG , preventing overshoot of V BG during power-on.

[0074] Refer to Figure 5 for the waveform diagram of the bandgap reference voltage V BG when the start-up circuit is powered on rapidly (1μs) in this embodiment. It can be found that the start-up circuit significantly slows down the rising rate of the bandgap reference voltage V BG , and V BG has substantially no overshoot under PVT (process corner) conditions.

[0075] Example 2:

[0076] Refer to Figure 6 for the schematic diagram of the start-up circuit for a bandgap reference circuit in this embodiment, wherein the bandgap reference circuit is a current-mode bandgap reference circuit 21.

[0077] The current-mode bandgap reference circuit comprises an operational amplifier A, a first MOS transistor MP1, a seventh MOS transistor MP0, a first branch, a second branch and a current-voltage conversion circuit, wherein both the first MOS transistor MP1 and the seventh MOS transistor MP0 are PMOS transistors.

[0078] The sources of the first MOS transistor MP1 and the seventh MOS transistor MP0 are both connected to the power supply voltage V DDThe drains of the two transistors are connected to the first input terminal vp and the second input terminal vn of operational amplifier A, respectively, and the gates of both are connected to the output terminal of operational amplifier A. The first branch includes a first bipolar transistor Q1 and several first matching resistors, and the second branch includes a second bipolar transistor Q2 and several second matching resistors. The first branch is connected between the first input terminal vp of operational amplifier A and ground potential, and the second branch is connected between the second input terminal vn of operational amplifier A and ground potential. The current-to-voltage conversion circuit is used to output the bandgap reference voltage V. BG .

[0079] The first branch includes first matching resistors R1a and R1b, and a first bipolar transistor Q1. The first end of the first matching resistor R1a is connected to the second end of the first MOSFET MP1, and the second end is connected to the second end of the first bipolar transistor Q1. The control terminal of the first bipolar transistor Q1 is shorted to the second end, and the first end is connected to ground potential. The first end of the first matching resistor R1b is connected to the second end of the first MOSFET MP1, and the second end is connected to ground potential.

[0080] The second branch includes a second matching resistor R2 and a second bipolar transistor Q2. The first end of the second matching resistor R2 is connected to the second end of the seventh MOS transistor MP0, and the second end is connected to ground potential. The second end of the second bipolar transistor Q2 is connected to the second end of the seventh MOS transistor MP0. The control terminal is shorted to the second end, and the first end is connected to ground potential.

[0081] Q1 and Q2 are illustrated using NPN transistors as an example, with the first terminal being the emitter, the second terminal being the collector, and the control terminal being the base. In other embodiments, PNP transistors can also be used.

[0082] In addition, the current-to-voltage conversion circuit in this embodiment includes an eighth MOS transistor MP3 and a first resistor R3. The eighth MOS transistor MP3 is a PMOS transistor, and its source is connected to the power supply voltage V. DD The drain is connected to the output node, the gate is connected to the control terminal of the first MOSFET MP1, the first end of the first resistor R3 is connected to the output node, and the second end is connected to ground. The output node is used to output the bandgap reference voltage V. BG .

[0083] The startup circuit 22 in this embodiment includes:

[0084] Pull-up resistor R0 and second MOSFET MN1, the first terminal of pull-up resistor R0 is connected to the power supply voltage V. DD The first terminal is connected to the second terminal of the second MOSFET MN1, and the first terminal of the second MOSFET MN1 is connected to ground potential. The control terminal is controlled by a drive signal.

[0085] Several control transistors are provided. The first terminal of each control transistor is connected to the first input terminal vp or the second input terminal vn of operational amplifier A. The second terminal is connected to the control terminal of the first MOSFET MP1 or the seventh MOSFET MP0. The control terminal is connected to the second terminal of the pull-up resistor R0.

[0086] Among them, the control transistor and the second MOS transistor MN1 are both NMOS transistors, with the first terminal being the source, the second terminal being the drain, and the control terminal being the gate.

[0087] For example, the control transistors include a first control transistor MNS1 and a second control transistor MNS2, wherein:

[0088] The source of the first control transistor MNS1 is connected to the second input terminal vn of the operational amplifier A, and the drain is connected to the gate of the first MOS transistor MP1 or the seventh MOS transistor MP0. The gate is connected to the second terminal of the pull-up resistor R0.

[0089] The source of the second control transistor MNS2 is connected to the first input terminal vp of the operational amplifier A, and the drain is connected to the gate of the first MOS transistor MP1 or the seventh MOS transistor MP0. The gate is connected to the second terminal of the pull-up resistor R0.

[0090] It should be understood that in other embodiments, only the first control tube MNS1 or only the second control tube MNS2 may be provided, and the number of control tubes is not limited.

[0091] Preferably, the startup circuit of this embodiment further includes a current replication unit, including a third MOS transistor MP2 and a fourth MOS transistor MN2. The third MOS transistor MP2 is a PMOS transistor and the fourth MOS transistor MN2 is an NMOS transistor. Their connection method is exactly the same as that of Embodiment 1, and will not be described again here.

[0092] Furthermore, the starting unit in this embodiment also includes a voltage limiting unit. The first end of the voltage limiting unit is connected to the control terminal of the control tube, and the second end is connected to the ground potential. The voltage limiting unit includes a current limiting device or multiple current limiting devices connected in series.

[0093] Specifically, the voltage limiting unit in this embodiment includes a fifth MOS transistor MN3 and a sixth MOS transistor MN4. Both the fifth MOS transistor MN3 and the sixth MOS transistor MN4 are NMOS transistors, and their connection method is exactly the same as that in Embodiment 1, so it will not be described again here.

[0094] In this embodiment, by connecting the sources of control transistors MNS1 / MNS2 to the input of the operational amplifier and optimizing the gate drive signal of the second MOS transistor MN1, the problem of bandgap reference voltage V during power-on of the startup circuit can be effectively solved. BG The problem of overshoot. The principle of the power-on process of the startup circuit in this embodiment is similar to that in Embodiment 1, and will not be described again here.

[0095] It should be understood that in Embodiments 1 and 2 above, the gate drive signal for controlling the second MOS transistor MN1 is generated through a current replication unit. In other embodiments, a bandgap reference voltage V can also be used. BG Using it directly as the gate drive signal for the second MOSFET MN1 can also solve the V signal issue during the power-on process of the startup circuit. BG Overshoot, bandgap reference voltage V BG Circuit parameters for controlling the gate of the second MOS transistor MN1 Figure 2 As shown, further details will not be elaborated here.

[0096] As can be seen from the above technical solutions, the present invention has the following beneficial effects:

[0097] This invention introduces a certain amount of negative feedback by controlling the setting of the MNS transistor, which pulls down the gate potential of MP1. The bandgap reference voltage rises monotonically throughout the startup process, which can effectively solve the problem of bandgap reference voltage overshoot during power-up of the startup circuit, avoid false triggering caused by bandgap reference voltage overshoot, and improve the reliability and stability of the circuit.

[0098] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0099] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A startup circuit for a bandgap reference circuit, wherein the bandgap reference circuit is a voltage-mode bandgap reference circuit, comprising an operational amplifier, a first MOSFET, a first branch, and a second branch, wherein a first terminal of the first MOSFET is connected to a power supply voltage, and a second terminal is connected to an output node; the first branch includes a first bipolar transistor and several first matching resistors; the second branch includes a second bipolar transistor and several second matching resistors; a first input terminal and a second input terminal of the operational amplifier are respectively connected to the first branch and the second branch; the output terminal is connected to the control terminal of the first MOSFET; and the output node is used to output a bandgap reference voltage V. BG Its characteristics are, The startup circuit includes: The system includes a pull-up resistor and a second MOSFET. The first terminal of the pull-up resistor is connected to the power supply voltage, and the second terminal is connected to the second terminal of the second MOSFET. The first terminal of the second MOSFET is connected to ground. The control terminal is controlled by a drive signal. The control terminal of the second MOSFET is connected to the output node, and the drive signal is the bandgap reference voltage V. BG ; The control transistor has its first end connected to the output node, its second end connected to the control terminal of the first MOS transistor, and the control terminal connected to the second end of the pull-up resistor.

2. A startup circuit for a bandgap reference circuit, wherein the bandgap reference circuit is a voltage-mode bandgap reference circuit, comprising an operational amplifier, a first MOSFET, a first branch, and a second branch, wherein a first terminal of the first MOSFET is connected to a power supply voltage, and a second terminal is connected to an output node; the first branch includes a first bipolar transistor and several first matching resistors; the second branch includes a second bipolar transistor and several second matching resistors; a first input terminal and a second input terminal of the operational amplifier are respectively connected to the first branch and the second branch; the output terminal is connected to the control terminal of the first MOSFET; and the output node is used to output a bandgap reference voltage V. BG Its characteristics are, The startup circuit includes: A pull-up resistor and a second MOSFET are provided. The first end of the pull-up resistor is connected to the power supply voltage, and the second end is connected to the second end of the second MOSFET. The first end of the second MOSFET is connected to ground potential. The control terminal is controlled by a drive signal. A control transistor, wherein the first end of the control transistor is connected to the output node, the second end is connected to the control terminal of the first MOS transistor, and the control terminal is connected to the second end of the pull-up resistor. The startup circuit also includes a current replication unit, comprising a third MOS transistor and a fourth MOS transistor, wherein the third MOS transistor is a PMOS transistor and the fourth MOS transistor is an NMOS transistor; The source of the third MOS transistor is connected to the power supply voltage, the gate is connected to the control terminal of the first MOS transistor, the drain is connected to the drain of the fourth MOS transistor, the source of the fourth MOS transistor is connected to ground potential, and the gate and drain are shorted and connected to the control terminal of the second MOS transistor.

3. The startup circuit for a bandgap reference circuit according to claim 1 or 2, characterized in that, The first MOS transistor is a PMOS transistor, with the first terminal being the source, the second terminal being the drain, and the control terminal being the gate; and / or, Both the control transistor and the second MOS transistor are NMOS transistors, with the first terminal being the source, the second terminal being the drain, and the control terminal being the gate.

4. The startup circuit for a bandgap reference circuit according to claim 1 or 2, characterized in that, The startup circuit also includes a voltage limiting unit. The first end of the voltage limiting unit is connected to the control terminal of the control tube, and the second end is connected to the ground potential. The voltage limiting unit includes a current limiting device or multiple current limiting devices connected in series.

5. The startup circuit for a bandgap reference circuit according to claim 4, characterized in that, The voltage limiting unit includes a fifth MOS transistor and a sixth MOS transistor, both of which are NMOS transistors; The source of the fifth MOS transistor is connected to ground, the drain is shorted to the gate and connected to the source of the sixth MOS transistor, and the drain and gate of the sixth MOS transistor are shorted to the control terminal of the control transistor MNS.

6. The startup circuit for a bandgap reference circuit according to claim 1 or 2, characterized in that, The first branch includes first matching resistors R1a and R1b, and a first bipolar transistor. The first end of the first matching resistor R1a is connected to the second end of the first MOS transistor, the second end of the first matching resistor R1b is connected to the first end of the first matching resistor R1b, the second end of the first matching resistor R1b is connected to the second end of the first bipolar transistor, the control terminal of the first bipolar transistor is shorted to the second end, and the first end is connected to ground potential. The second branch includes a second matching resistor R2 and a second bipolar transistor. The first end of the second matching resistor R2 is connected to the second end of the first MOS transistor, the second end is connected to the second end of the second bipolar transistor, the control terminal of the second bipolar transistor is shorted to the second end, and the first end is connected to ground potential.

7. A startup circuit for a bandgap reference circuit, wherein the bandgap reference circuit is a current-mode bandgap reference circuit, comprising an operational amplifier, a first MOSFET, a seventh MOSFET, a first branch, a second branch, and a current-to-voltage conversion circuit. The first terminals of the first and seventh MOSFETs are both connected to a power supply voltage, and their second terminals are respectively connected to the first and second input terminals of the operational amplifier. Control terminals of both are connected to the output terminal of the operational amplifier. The first branch includes a first bipolar transistor and several first matching resistors, and the second branch includes a second bipolar transistor and several second matching resistors. The first branch is connected between the first input terminal of the operational amplifier and ground potential, and the second branch is connected between the second input terminal of the operational amplifier and ground potential. The current-to-voltage conversion circuit outputs a bandgap reference voltage V. BG Its characteristics are, The startup circuit includes: The system includes a pull-up resistor and a second MOSFET. The first terminal of the pull-up resistor is connected to the power supply voltage, and the second terminal is connected to the second terminal of the second MOSFET. The first terminal of the second MOSFET is connected to ground. The control terminal is controlled by a drive signal. The control terminal of the second MOSFET is connected to the output node, and the drive signal is the bandgap reference voltage V. BG ; Several control transistors are provided, wherein the first end of each control transistor is connected to the first or second input terminal of an operational amplifier, the second end is connected to the control terminal of a first or seventh MOS transistor, and the control terminal is connected to the second end of a pull-up resistor.

8. A startup circuit for a bandgap reference circuit, wherein the bandgap reference circuit is a current-mode bandgap reference circuit, comprising an operational amplifier, a first MOSFET, a seventh MOSFET, a first branch, a second branch, and a current-to-voltage conversion circuit. The first terminals of the first and seventh MOSFETs are both connected to a power supply voltage, and their second terminals are respectively connected to the first and second input terminals of the operational amplifier. Control terminals of both are connected to the output terminal of the operational amplifier. The first branch includes a first bipolar transistor and several first matching resistors, and the second branch includes a second bipolar transistor and several second matching resistors. The first branch is connected between the first input terminal of the operational amplifier and ground potential, and the second branch is connected between the second input terminal of the operational amplifier and ground potential. The current-to-voltage conversion circuit outputs a bandgap reference voltage V. BG Its characteristics are, The startup circuit includes: A pull-up resistor and a second MOSFET are provided. The first end of the pull-up resistor is connected to the power supply voltage, and the second end is connected to the second end of the second MOSFET. The first end of the second MOSFET is connected to ground potential. The control terminal is controlled by a drive signal. Several control transistors, wherein the first terminal of the control transistor is connected to the first or second input terminal of the operational amplifier, the second terminal is connected to the control terminal of the first or seventh MOS transistor, and the control terminal is connected to the second terminal of the pull-up resistor. The startup circuit also includes a current replication unit, comprising a third MOS transistor and a fourth MOS transistor, wherein the third MOS transistor is a PMOS transistor and the fourth MOS transistor is an NMOS transistor; The source of the third MOS transistor is connected to the power supply voltage, the gate is connected to the control terminal of the first MOS transistor, the drain is connected to the drain of the fourth MOS transistor, the source of the fourth MOS transistor is connected to ground potential, and the gate and drain are shorted and connected to the control terminal of the second MOS transistor.

9. The startup circuit for a bandgap reference circuit according to claim 7 or 8, characterized in that, Both the first and seventh MOS transistors are PMOS transistors, with the first terminal being the source, the second terminal being the drain, and the control terminal being the gate; and / or, Both the control transistor and the second MOS transistor are NMOS transistors, with the first terminal being the source, the second terminal being the drain, and the control terminal being the gate.

10. The startup circuit for a bandgap reference circuit according to claim 7 or 8, characterized in that, The startup circuit also includes a voltage limiting unit. The first end of the voltage limiting unit is connected to the control terminal of the control tube, and the second end is connected to the ground potential. The voltage limiting unit includes a current limiting device or multiple current limiting devices connected in series.

11. The startup circuit for a bandgap reference circuit according to claim 10, characterized in that, The voltage limiting unit includes a fifth MOS transistor and a sixth MOS transistor, both of which are NMOS transistors; The source of the fifth MOS transistor is connected to ground, the drain is shorted to the gate and connected to the source of the sixth MOS transistor, and the drain and gate of the sixth MOS transistor are shorted to the control terminal of the control transistor MNS.

12. The startup circuit for a bandgap reference circuit according to claim 7 or 8, characterized in that, The first branch includes first matching resistors R1a and R1b, and a first bipolar transistor. The first end of the first matching resistor R1a is connected to the second end of the first MOSFET, and the second end is connected to the second end of the first bipolar transistor. The control terminal of the first bipolar transistor is shorted to the second end, and the first end is connected to ground potential. The first end of the first matching resistor R1b is connected to the second end of the first MOSFET, and the second end is connected to ground potential. The second branch includes a second matching resistor R2 and a second bipolar transistor. The first end of the second matching resistor R2 is connected to the second end of the seventh MOS transistor, and the second end is connected to ground potential. The second end of the second bipolar transistor is connected to the second end of the seventh MOS transistor. The control terminal is shorted to the second end, and the first end is connected to ground potential.

13. The startup circuit for a bandgap reference circuit according to claim 7 or 8, characterized in that, The current-to-voltage conversion circuit includes an eighth MOS transistor and a first resistor. The eighth MOS transistor is a PMOS transistor, with its source connected to the power supply voltage, its drain connected to the output node, and its gate connected to the control terminal of the first MOS transistor. The first terminal of the first resistor is connected to the output node, and the second terminal is connected to ground potential.

Images