Data gating using the scan enable pin

Abstract

The present disclosure provides an integrated circuit (100) that includes a storage element (102) and control circuitry (106, 110). The control circuitry is configured to: select between a functional data input and a scan data input to be used as an input to the storage element in response to a scan enable control; selectively disable toggling of an output of the storage element by gating a clock signal provided to the storage element in response to a clock enable control; and select the input to the storage element as the scan data input when the clock enable control indicates that toggling of the output of the storage element is to be prohibited.

Description

Technical Field

[0001] The present disclosure generally relates to integrated circuits and, more particularly, to power reduction in gated clock circuits in integrated circuits. Background Art

[0002] To mitigate the test challenges of integrated circuits (ICs) comprising millions of transistors, a scan mode is often implemented where the flip-flops of the IC are daisy-chained, allowing for simple scan chain testing of an otherwise complex state machine. For an overview of scan test techniques, see, for example, “Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic”, IEEE Transactions on Computers, C-22(1), 46-60; M. Williams and J. Angell (doi: 10.1109 / t-c.1973.223600).

[0003] To reduce the dynamic power consumption of ICs with millions of transistors, clock gating is often used. In “Clock Gating - A Power Optimization Technique for VLSI Circuits” (J. Shinde et al., 2011 Annual IEEE India Conference, Dec. 16-18, 2011; DOI 10.1109 / INDCON.2011.6139440), the authors studied various clock gating techniques that can be used to optimize power in VLSI circuits at the RTL level and discussed the various issues involved in applying this power optimization technique at the RTL level. Summary of the Invention

[0004] Embodiments described herein provide an integrated circuit (IC) including a storage element and control circuitry. The control circuitry is configured to: select between a functional data input and a scan data input to be used as an input to the storage element in response to a scan enable control; selectively disable toggling of an output of the storage element by gating a clock signal provided to the storage element in response to a clock enable control; and select the input of the storage element as the scan data input when the clock enable control indicates that toggling of the output of the storage element is to be prohibited.

[0005] In some embodiments, the storage element includes one or more latches, and, when the scan data input is selected, the control circuit is configured to prevent any of the latches in the storage element from toggling while the output is inhibited from toggling, regardless of whether the functional data input is toggling. In an exemplary embodiment, the control circuit is configured to prevent the latches from toggling without adding delay to the functional data input.

[0006] In the embodiments disclosed herein, by selecting the scan data input when the clock enable control indicates that the output will be inhibited from toggling, the control circuit is configured to set the input to the storage element to a constant logic state, regardless of whether the functional data input is toggling. In another embodiment, the control circuit includes logic gates configured to set the storage element to scan mode in response to the clock enable control disabling the clock signal.

[0007] In another embodiment, the control circuit includes logic gates configured to set the input to the storage element to a constant logic state in response to the clock enable control disabling the clock signal. In another embodiment, the storage element includes latches clocked by the inverse of the clock signal, and, when the scan data input is selected while the clock enable control indicates that the output will be inhibited from toggling, the control circuit is configured to set the input to the latches to a constant logic state.

[0008] According to the embodiments described herein, a method in an integrated circuit (IC) including at least a storage element is also provided. The method includes selecting between a functional data input and a scan data input to be used as an input to the storage element in response to a scan enable control. Selectively disabling toggling of the output of the storage element by gating a clock signal provided to the storage element in response to a clock enable control. Selecting the input to the storage element as the scan data input when the clock enable control indicates that the output of the storage element will be inhibited from toggling.

[0009] According to an embodiment described herein, there is also provided an apparatus including a processor, the processor including (i) an acquisition circuit configured to acquire instructions, and (ii) an execution circuit configured to execute instructions. One or both of the acquisition circuit and the execution circuit include a storage element and a control circuit. The control circuit is configured to: in response to a scan enable control, select between a functional data input and a scan data input to be used as an input to the storage element; in response to a clock enable control, selectively disable toggling of an output of the storage element by gating a clock signal provided to the storage element; and when the clock enable control indicates that toggling of the output of the storage element is to be prohibited, select the input of the storage element as the scan data input.

[0010] In conjunction with the accompanying drawings, a more complete understanding of the present disclosure will be obtained from the following detailed description of embodiments of the present disclosure, in which: BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram schematically showing the structure of an integrated circuit (IC) according to an embodiment described herein;

[0012] Figure 2 is a block diagram schematically showing the structure of a D-type flip-flop (DFF) coupled to a scan circuit and clock gating according to an embodiment described herein;

[0013] Figure 3 is a block diagram schematically showing the structure of a computer according to an embodiment described herein;

[0014] Figure 4 is a flowchart schematically showing a method of reducing power consumption using data gating according to an embodiment described herein;

[0015] Figure 5 is a diagram schematically showing various types of systems that may include any one of the circuits, devices, or systems discussed herein; and

[0016] Figure 6 is a block diagram showing an exemplary non-transitory computer-readable storage medium storing circuit design information according to some embodiments. DETAILED DESCRIPTION

[0017] Overview

[0018] Typically, a complex integrated circuit includes storage elements, each configured to store a "logic-1" or "logic-0" value. In this context, the term "storage element" refers to elements such as flip-flops, latches, etc. For example, the embodiments described herein refer to flip-flops, but the techniques disclosed by the present invention are applicable to other suitable types of storage elements.

[0019] There are various types of flip-flops, including for example clocked flip-flops and non-clocked flip-flops, R-S flip-flops, J-K flip-flops, T flip-flops, etc. A common type of flip-flop widely used in today's integrated circuits is the D flip-flop (sometimes referred to as DFF), which includes a D input, a clock input, and an output. The DFF is configured to store the logic value asserted at its D input when the clock input transitions, for example from logic low to logic high. In the following disclosure, for example, the flip-flop and the DFF may sometimes be referred to interchangeably.

[0020] To allow easy testing of digital integrated circuits, a scan circuit can be added to a set of DFFs in the integrated circuit. An external tester can indicate a scan mode (or scan enable) to the scan circuit, in which the set of DFFs should be scanned. The scan circuit is configured to sequentially interconnect (e.g., "daisy-chain") the DFFs in the set in response to the scan mode indication, such that a scan input external to the set of DFFs propagates between the DFFs in the set, from the first DFF to the last DFF, and from the last DFF to the scan-out output of the set of DFFs. (Two modes of integrated circuit operation will be addressed below - one is the scan mode described above, and the other is the functional mode, in which the scan circuit does not operate and the DFFs receive functional inputs instead of scan inputs.)

[0021] Hereinafter, logic low and logic high will further be referred to as low level and high level respectively; we will refer to the transition from low to high as the rising edge (or "positive edge"), and the transition from high to low as the falling edge (or "negative edge"). It should be understood that the low level and the high level do not necessarily represent voltage levels; for example, in some logic families, the low level and the high level can refer to current directions; furthermore, in some logic families, the low level represents a voltage level higher than the voltage level represented by the high level (e.g., in negative logic).

[0022] A DFF generally includes a primary latch and a secondary latch. In a positive-edge-triggered DFF, when the clock input is low, the primary latch propagates the D input of the DFF to the input of the secondary latch and latches the value of the D input at the rising edge of the clock; when the clock input is high, the secondary latch propagates the output of the primary latch to the DFF output and latches the value of the primary latch at the falling edge of the clock. Conversely, in a negative-edge-triggered DFF, the primary latch propagates the input when the clock is high and latches at the negative edge of the clock, while the secondary latch propagates the output of the primary latch when the clock is low and latches the output at the rising edge of the clock. (Note that the primary and secondary latches can operate in a manner that those skilled in the art also refer to as “master” (i.e., primary) and “slave” (i.e., secondary). Although the primary / secondary terminology is used herein, it is expressly intended that “primary” and “secondary” be interpreted to cover these corresponding terms.

[0023] High-speed high-density integrated circuits can include millions of DFFs, and the toggling of the clock input of the DFFs is a significant factor in the power consumption of the integrated circuit. A common technique for reducing power consumption is clock gating, in which the clock signal is disabled in unused circuit portions. Clock gating saves power by pruning the clock tree, but at the cost of adding more logic components to the circuit.

[0024] Typically, when the clock of a DFF is disabled, the clock input of the DFF is set to a logic level at which the primary latch is transparent (i.e., it propagates the D input to the secondary latch), but does not latch the logic value, while the secondary latch stores the last value output by the primary latch at the falling edge of the clock (e.g., for a positive-edge-triggered DFF, the clock is set to low). Thus, since the secondary latch does not toggle, the power dissipation is significantly reduced. (The secondary latch typically drives a logic circuit, and when toggling, charges and discharges additional nodes, resulting in significant power dissipation.)

[0025] However, when the primary latch is transparent, it typically toggles when the D input toggles, even if the clock of the DFF can be disabled and the change in the D input is not visible at the output of the secondary latch. Thus, even if the clock of the DFF is disabled, toggling of the secondary latch can still result in significant power consumption.

[0026] The embodiments described herein provide apparatuses and methods that use data gating in addition to clock gating of clock-disabled DFFs to further reduce the power consumption of clock-disabled DFFs. In some embodiments, a control circuit is configured to direct a scan enable input that is constant when scan is not indicated to an input of a corresponding DFF in response to a clock disable input, thereby setting the DFF input to a constant logic level. Thus, when the clock is disabled, both the data input and the clock input are gated, thereby significantly reducing the power consumption of the integrated circuit.

[0027] In addition, the control circuit disclosed in the present invention does not add any logic components in the functional data path (e.g., before the functional input of a flip-flop). Thus, the techniques disclosed in the present invention do not introduce additional delay and do not reduce the achievable data throughput or clock speed.

[0028] System Description

[0029] Figure 1 is a block diagram schematically showing the structure of an integrated circuit (IC) 100 according to the embodiments described herein. The IC 100 can include any suitable type of IC configured to perform any suitable function, such as a microprocessor, a video processor, or any other IC. The IC includes: a set of dual-latch D-type flip-flops (DFFs) 102 that share a common clock input (designated "clock"); and combinational logic circuitry 104 configured to generate functional inputs of the DFFs 102 in response to data stored in the DFFs (and possibly in response to other inputs). Each DFF includes a clock input ("CLK"), a D input, and a Q output (in embodiments, the DFFs 102 can include other inputs, such as reset).

[0030] It should be understood that an integrated circuit according to some embodiments can include multiple clock inputs and multiple sets of DFFs, with each set of DFFs sharing one of the multiple clock inputs. In some embodiments, the IC 100 can include other logic components, such as non-clock flip-flops, memories, analog circuits, etc. However, for clarity, embodiments in which the IC 100 includes a single clock will be referred to hereinafter, and circuits not relevant to the DFF set, such as memories, analog subsystems, etc., will be ignored.

[0031] According to Figure 1 the exemplary embodiment shown in, the IC 100 includes a scan circuit 106, each scan circuit being coupled to a corresponding DFF 102 and configured to be able to transfer a functional input (output from the combinational logic circuitry 104) or a scan input to the D input of the DFF in response to a scan enable input.

[0032] The DFFs 102 are coupled to each other in a daisy chain such that the scan input of the scan circuit coupled to the first DFF is coupled to the SCAN-IN input of the IC 100, the scan input of the scan circuit coupled to the second DFF is coupled to the Q output of the first DFF, and so on. The Q output of the last DFF is coupled to the SCAN-OUT output of the IC. (In some embodiments, SCAN-IN and / or SCAN-OUT are not inputs / outputs of the IC 100; rather, scan-in can be an input from a built-in self-test (BIST) circuit in the IC 100 and / or SCAN-OUT can be an output to a built-in self-test (BIST) circuit in the IC 100.)

[0033] The IC 100 also includes a clock disabling circuit 108 that is configured to disable the clock inputs of the DFFs 102 that may be in an inactive state. A clock gating circuit 110 is coupled to each DFF 102; the clock gating circuit is configured to disable the clock input of the DFF in response to a clock disable control output by the clock disabling circuit 108 (e.g., by applying a constant logic low to the clock input of the DFF). As described above, this will prevent the secondary latches of the DFF 102 from toggling back and forth and thus reduce power consumption.

[0034] According to Figure 1 the exemplary embodiment shown in Figure 2 data gating is also employed in addition to clock gating to prevent the primary latches (in addition to the secondary latches) from toggling back and forth. (An exemplary internal structure of the dual-latch flip-flop 102 is described below

[0035] which shows the primary latch and the primary latch.) The scan circuit 106 is configured to send a constant logic level (e.g., low level) to the D input of the corresponding DFF in response to a clock disable input. Thus, the primary latch will not toggle and additional power reduction will be achieved (in an embodiment, in response to a clock disable input, the scan circuit sends a scan enable input to the D input of the DFF, which is a constant low level in the functional mode). Figure 1 It should be understood that

[0036] the structure of the IC 100 shown and described above is an exemplary embodiment cited for clarity. In alternative embodiments, other structures may be used. For example, the scan circuit may also be used to set the DFFs to a known state; other types of flip-flops may be used; and more than one scan chain may be implemented in the IC. Figure 1Implemented by different circuits or different organizations. In this context, the terms "clock enable input" and "clock disable input" are used interchangeably to refer to a signal that controls whether the clock is enabled or disabled.

[0037] Figure 2 FIG. is a block diagram schematically showing the structure of DFF 102 coupled to scan circuit 106 and clock gating 110 according to an embodiment described herein. Herein, according to Figure 2 The example embodiments shown are described in more detail with reference to Figure 1 The DFF 102, scan circuit 106, and clock gating 110 discussed above. As described below, for ease of presentation, Figure 2 FIG. shows the logical functions of embodiments of scan circuit 106 and clock gate 110 in terms of AND gates and OR gates. However, it should be noted that any suitable circuit structure can be employed to implement the functions shown.

[0038] DFF 102 includes two latches - a primary latch 202 and a secondary latch 204. When the clock input is low, the primary latch propagates the D input of the DFF to the input of the secondary latch and latches the value of the D input at the rising edge of the clock. When the clock input is high, the secondary latch propagates the output of the primary latch to the DFF output and latches the value of the primary latch at the falling edge of the clock.

[0039] The clock input of DFF 102 shared by primary latch 202 and secondary latch 204 is generated by clock gating 110. According to Figure 2 The exemplary embodiment shown, clock gating 110 is an AND gate that propagates the clock input to the DFF clock input when the clock enable input is high and sets the DFF's clock input to low when the clock enable is low, thereby preventing the secondary latch from toggling back and forth.

[0040] Scan circuit 106 includes: a multiplexer 206 configured to select the source for the D input of DFF 102; an AND gate 208 configured to gate the scan data; an inverter 209; and an OR gate 210 configured to indicate which source the multiplexer 206 should send to the D input of DFF 102.

[0041] In scan mode, the scan enable input is high, the AND gate 208 outputs the scan-in data, and the OR gate 210 outputs a logic high, causing the multiplexer 206 to transfer the output of the AND gate 208 to the D input of DFF 102. Thus, the scan path is configured, and the scan input propagates through the Q output of DFF 102 (and thus propagates to the scan input of the scan circuit of the next DFF stage, as Figure 1As shown in). In the functional mode, the scan enable input is low, and if the clock enable input is high, the multiplexer 206 transfers the functional input to the D input of the DFF 202.

[0042] However, in the functional mode, if the clock enable is low, the OR gate 210 indicates that the multiplexer 206 should transfer the output of the AND gate 208 to the D input of the DFF 102. When the scan enable input is now low, the inverter 209 outputs high and the AND gate 208 will output low, the D input of the DFF 102 will be low, and thus, regardless of any toggling in the functional input, the primary latch 202 will not toggle back and forth, thereby further reducing power consumption.

[0043] It should be understood that Figure 2 The structures of the DFF 102, the scan circuit 106, and the clock gating 110 shown and described above are cited by way of example. In alternative embodiments, various suitable structures may be used. For example, the De Morgan equivalent form of the gated shown may be used. In some embodiments, the scan enable input and / or the clock enable input may be active low. In embodiments, other types of DFFs may be used, and in some embodiments, some or all of the DFFs may be replaced by other types of flip - flops (e.g., T flip - flops).

[0044] In this example, in addition to the flip - flop 102 Figure 2 various elements (the scan circuit 106 and the clock gate 110) serve as the control circuit for implementing the techniques disclosed in the present invention. In alternative embodiments, the control circuit may have any other suitable configuration.

[0045] Figure 3 is a block diagram schematically showing the structure of a computer 300 according to an embodiment described herein. The computer 300 includes a central processing unit (CPU) 304 and a memory 306. The CPU includes: an instruction fetch circuit 308 configured to fetch and decode instructions (e.g., from the memory 306); and an instruction execution circuit 310 configured to execute the decoded instructions.

[0046] The user can interact with the computer 300 through a display device and one or more input devices (in this example, the display / keyboard / mouse subsystem 312). It should be understood that the computer 300 may include multiple CPUs and many other components, including for example, an encryption / decryption unit, a graphics processor, a network interface circuit, an analog circuit, and a wireless interface unit.

[0047] The instruction fetch circuit 308 and the instruction execution circuit 310 include multiple flip - flops, such as Figure 1 and Figure 2trigger 102. According to Figure 3 the exemplary embodiment shown, the CPU 304 includes a scan chain 316 that covers at least some of the flip-flops in the instruction fetch circuit 308 and the instruction execution circuit 310 (and / or additional logic circuits that the CPU 300 may include). The scan chain includes a scan circuit (e.g., Figure 2 scan circuit 106) that is configured to operate the corresponding flip-flop in scan mode and, when the clock of the corresponding flip-flop is disabled, set the D input of the flip-flop to a constant logic level, for example, by routing the scan enable input to the D input of the flip-flop.

[0048] Figure 4 is a flowchart schematically showing a method 400 of using data gating to reduce power consumption according to the embodiments described herein. The flowchart is executed by the clock gating 110 and the scan circuit 106 ( Figure 1 ). Each of the scan circuit and the clock gating executes this process independently of the other scan circuits and clock gating.

[0049] The flowchart begins at the check-scan-enable stage 402, where the scan circuit checks whether scan-enable is indicated. If so, the flowchart enters the "route scan to flip-flop" stage 404, where the scan circuit routes the scan-in input to the D input of the DFF 102, enters the scan test of the DFF, and the flowchart ends.

[0050] If no scan enable indication is present in stage 402, the clock gating and the scan circuit enter the check-clock-enable stage 406 and check whether the clock of the corresponding DFF is enabled. If so, the clock gating and the scan circuit enter the functional operation stage 408, where the scan mode is disabled and the clock is not gated, and then the flowchart ends.

[0051] If the clock is not enabled in stage 406, the scan circuit will route the scan input (which is set to low in the functional mode) to the D input of the DFF 102 in the "route scan input to flip-flop" stage 410, so that the primary latch of the DFF will not switch back and forth. Then, in the "force flip-flop clock to low" stage, the clock gating 110 sets the clock input of the flip-flop to low, thereby preventing the secondary latch from switching back and forth.

[0052] Therefore, according to Figure 4In the method shown and described above, the clock gating and scan circuitry is operable to route the scan-in input to the D input of the corresponding flip-flop in response to a scan mode indication (scan enable high); and in response to a clock disable indication (clock enable low), i) force a constant low level at the clock input of the flip-flop to prevent the secondary latch from toggling back and forth, and ii) route the scan enable input (which is low in functional mode) to the D input of the flip-flop to prevent the primary latch from toggling back and forth.

[0053] Figure 5 FIG. 500 schematically illustrates various types of systems that may include any of the circuits, devices, or systems discussed above, according to an embodiment described herein. Systems or devices 500 that may incorporate or otherwise utilize one or more of the techniques described herein can be used in a wide range of fields. For example, system or device 500 can be used as part of the hardware of systems such as desktop computer 510, laptop computer 520, tablet computer 530, cellular or mobile phone 540, or television 550 (or a set-top box coupled to a television).

[0054] Similarly, the disclosed elements can be used in wearable devices 560, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can implement a variety of different functions - for example, access to email, cellular service, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0055] System or device 500 can also be used in a variety of other contexts. For example, system or device 500 can be used in the context of a server computer system, such as a dedicated server, or on shared hardware implementing cloud-based services 570. Further still, system or device 500 can be implemented in a wide range of dedicated everyday devices, including devices 580 common in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is commonly referred to as the "Internet of Things" (IoT). The elements can also be implemented in various modes of transportation. For example, system or device 500 can be used in control systems, guidance systems, entertainment systems, etc. of various types of vehicles 590.

[0056] Figure 5The applications shown are merely exemplary and are not intended to limit the potential future applications of the disclosed systems or devices. Other exemplary applications include, but are not limited to: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, and the like.

[0057] The present disclosure has described various exemplary circuits in detail above. It is intended that the present disclosure cover not only embodiments including such circuits, but also computer-readable storage media including design information specifying such circuits. Accordingly, the present disclosure is intended to support claims that cover not only apparatuses including the disclosed circuits, but also storage media that specify the circuits in a format recognized by a manufacturing system configured to produce hardware (e.g., integrated circuits) including the disclosed circuits. Claims to such storage media are intended to cover, for example, entities that generate circuit designs but do not themselves manufacture the designs.

[0058] Figure 6 is a block diagram showing an exemplary non-transitory computer-readable storage medium storing circuit design information, according to some embodiments. In the illustrated embodiment, semiconductor manufacturing system 620 is configured to process design information 615 stored on non-transitory computer-readable medium 610 and manufacture integrated circuit 830 based on design information 615.

[0059] The non-transitory computer-readable storage medium 610 can include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 610 can be an installation medium such as a CD-ROM, floppy disk, or tape device; computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory such as flash memory, magnetic media such as a hard disk drive, or optical storage device; registers, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 610 can also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 810 can include two or more memory media that may reside in different locations, e.g., in different computer systems connected by a network.

[0060] Design information 615 may be specified using any of a variety of suitable computer languages, including hardware description languages such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, and the like. Design information 615 may be used by semiconductor manufacturing system 620 to manufacture at least a portion of integrated circuit 630. The format of design information 615 is recognizable by at least one semiconductor manufacturing system 620. In some embodiments, design information 615 may also include one or more cell libraries that specify the synthesis, layout, or both of integrated circuit 630. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies the cell library elements and their connectivity. Design information 615, obtained separately, may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information 815 may specify the circuit elements to be manufactured, but not their physical layout. In such cases, design information 815 may need to be combined with layout information to actually manufacture the specified circuit system.

[0061] In various embodiments, integrated circuit 630 may include one or more custom macrocells, such as memory, analog or mixed-signal circuits, and the like. In this case, design information 615 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to Graphics Data System II (GDSII) or any other suitable format.

[0062] Semiconductor manufacturing system 620 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 820 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0063] In various embodiments, integrated circuit 630 is configured to operate according to the circuit design specified by design information 615, which may include performing any of the functions described herein. For example, integrated circuit 630 may include Figure 1 、 Figure 2 、 Figure 3 and Figure 5 Any of the various elements shown in . In addition, integrated circuit 630 can be configured to perform the various functions described herein in conjunction with other components. In addition, the functionality described herein can be performed by multiple connected integrated circuits.

[0064] As used herein, a phrase of the form "design information specifying the design of a circuit configured to..." does not imply that the circuit in question must be fabricated in order to meet the element. Instead, the phrase indicates that the design information describes a circuit that, when fabricated, will be configured to perform the indicated actions or will include the specified components.

[0065] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). An embodiment is a distinct, particular implementation or instance of the disclosed concepts. References to "an embodiment", "one embodiment", "a particular embodiment", etc. do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of this disclosure.

[0066] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular implementation realizes an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why a particular implementation that falls within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of this disclosure that, in combination with one of the disclosed embodiments, negates or diminishes one or more of the disclosed advantages. Additionally, suboptimal design implementation of a particular implementation (e.g., a particular implementation technique or tool) may also negate or diminish the disclosed advantages. Even assuming a technically sound implementation, the realization of an advantage may still depend on other factors, such as the circumstances of the environment in which the implementation is deployed. For example, the input provided to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on a particular occasion, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors outside the scope of this disclosure, any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate one or more types of improvements available to designers who benefit from this disclosure. Permanently describing such advantages (e.g., stating that a particular advantage "may occur") is not intended to convey doubt as to whether such advantages can actually be realized, but rather to recognize the technical reality that the realization of such advantages typically depends on additional factors.

[0067] Unless otherwise indicated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even in cases where only a single example is described for a particular feature. The disclosed embodiments of the present invention are intended to be exemplary rather than restrictive, without any contrary statement in this disclosure. Accordingly, this application is intended to allow claims that cover the disclosed embodiments, as well as such alternative, modified, and equivalent forms, which will be apparent to those skilled in the art who are aware of the effective effects of this disclosure.

[0068] For example, the features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this patent application (or a patent application claiming priority therefrom) for any such combination of features. Specifically, with reference to the appended claims, the features of a dependent claim may, where appropriate, be combined with the features of other dependent claims, including claims that depend on other independent claims. Similarly, the features from corresponding independent claims may be combined where appropriate.

[0069] Accordingly, while the appended dependent claims may be drafted such that each dependent claim depends on a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with this disclosure is contemplated, and such combinations may be protected by claims in this patent application or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0070] Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0071] ***

[0072]

[0073] References to items in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. "A plurality" of items means a collection of two or more items.

[0074] The word "may" is used herein in the permissive sense (i.e., having the potential to, being able to), rather than in the mandatory sense (i.e., must).​

[0075] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to".

[0076] When the term "or" is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the statement "x or y" is equivalent to "x or y, or both", and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0077] The statements "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities of individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in that list of elements. This phrase should not be construed as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0078] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for features (e.g., "first circuit", "second circuit", "specific circuit", "given circuit", etc.) refer to different instances of the feature. Beyond that, unless otherwise stated, the labels "first", "second", and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0079] The phrase "based on" or is used to describe one or more factors that affect a determination. This term does not exclude the possibility that there may be additional factors that affect the determination. That is, the determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "determine A based on B". This phrase specifies that B is a factor used to determine A or that B affects the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments where A is determined only based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on".

[0080] The phrases "responsive to" and "responsive" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect, either in conjunction with or independent of the specified factors. That is, the effect can be responsive solely to these factors, or can be responsive to the specified factors as well as other unspecified factors. Consider the phrase "perform A responsive to B". This phrase specifies that B is the factor that triggers the performance of A or triggers a particular result of A. This phrase does not exclude the possibility that the performance of A may also be responsive to some other factor, such as C. This phrase also does not exclude the possibility that the performance of A may be performed in response to B and C in combination. This phrase is also intended to cover embodiments where A is performed responsive solely to B. As used herein, the phrase "responsive" is synonymous with the phrase "responsive at least in part to". Similarly, the phrase "responsive to" is synonymous with the phrase "responsive at least in part to".

[0081] ***

[0082] Within the present disclosure, different entities (which may variously be referred to as "units", "circuits", other components, etc.) may be described or claimed as "configured to" perform one or more tasks or operations. This expression - [entity] configured to [perform one or more tasks] - is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a certain task even if the structure is not currently being operated. Thus, an entity described or represented as "configured to" perform a certain task refers to a physical thing used to implement that task, such as a device, a circuit, a system having a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to intangible things.

[0083] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations even if not specifically stated.

[0084] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA can be "configurable to" perform that function. After appropriate programming, the FPGA can then be considered "configured to" perform a particular function.

[0085] For purposes of a U.S. patent application based on this disclosure, reciting in a claim that a structure "is configured to" perform one or more tasks is specifically intended not to invoke 35 U.S.C. § 112(f) for that claim element. If an applicant wishes to invoke 35 U.S.C. § 112(f) during the prosecution of a U.S. patent application based on this disclosure, it will phrase the claim element using the "means for [performing a function]" structure.

[0086] Different "circuits" may be described in this disclosure. These circuits or "circuitry" constitute hardware that includes various types of circuit elements such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, and the like. The circuits may be custom designed or taken from a standard library. In various specific embodiments, the circuits may optionally include digital components, analog components, or a combination of both. Certain types of circuits may generally be referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit systems.

[0087] Accordingly, the disclosed circuits / units / components and other elements shown in the figures and described herein include hardware elements such as those described in the previous paragraphs. In many cases, the internal arrangement of the hardware elements within a particular circuit may be specified by describing the function of the circuit. For example, a particular "decoding unit" may be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of functional units," which means that the decoding unit "is configured to" perform that function. For a person skilled in the art of computing, this functional specification is sufficient to imply a set of possible structures for the circuit.

[0088] In various embodiments, as discussed in the preceding paragraphs, the arrangement of circuits, cells, and other elements defined by the functions or operations they are configured to implement, relative to one another, and the manner in which such circuits / cells / components interact form a micro-architecture definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to form a physical implementation of the micro-architecture definition. Thus, the micro-architecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the micro-architecture definition. That is, a person having the micro-architecture definition provided by the present disclosure can, without undue experimentation and using the applications of an ordinary skilled person, implement the structure by encoding a description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. HDL descriptions are often expressed in a manner that can appear functional. However, for those skilled in the art, the HDL description is a means of translating the structure of a circuit, cell, or component into the next level of implementation details. Such HDL descriptions can take the form of behavioral code (which is typically non-synthesizable), register transfer language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL descriptions can be sequentially synthesized for a cell library designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is transferred to a foundry to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and circuit elements. Some embodiments can implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete components can be used in some embodiments. Alternatively, the HDL design can be synthesized into a programmable logic array such as a field programmable gate array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits typically results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation beyond a description of what the circuit is configured to do, as the process is carried out at different stages of the circuit implementation process.

[0089] The fact that many different low-level combinations of circuit elements can be used to implement the same specification of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations can vary depending on manufacturing technology, the foundry chosen to fabricate the integrated circuit, the cell library provided for a particular project, etc. In many cases, the choice of generating these different implementations through different design tools or methods can be arbitrary.

[0090] In addition, for a given implementation, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the sheer volume of this information makes it impractical to provide a complete narrative of the low-level structures for implementing a single implementation, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of a circuit using functional shorthand commonly used in the industry.

Claims

1. An integrated circuit IC, comprising: a storage element; and a control circuit configured to: select between a functional data input and a scan data input to be used as an input to the storage element in response to a scan enable control; selectively disable toggling of an output of the storage element by gating a clock signal provided to the storage element in response to a clock enable control; and when the clock enable control indicates that the output of the storage element is to be prohibited from toggling, select the input of the storage element as the scan data input.

2. The IC according to claim 1, wherein the storage element includes one or more latches, and wherein, When selecting the scan data input, the control circuit is configured to prevent any of the latches in the latch from toggling while the output is prohibited from toggling, regardless of whether the functional data input is toggling.

3. The IC according to claim 2, wherein the control circuit is configured to prevent the latch from toggling without adding a delay to the functional data input.

4. The IC according to claim 1, wherein, By selecting the scan data input when the clock enable control indicates that the output is to be prohibited from toggling, the control circuit is configured to set the input to the storage element to a constant logic state, regardless of whether the functional data input is toggling.

5. The IC according to claim 1, wherein the control circuit includes a logic gate configured to set the storage element to a scan mode by disabling the clock signal in response to the clock enable control.

6. The IC according to claim 1, wherein the control circuit includes a logic gate configured to set the input to the storage element to a constant logic state by disabling the clock signal in response to the clock enable control.

7. The IC according to claim 1, wherein the storage element includes a latch clocked by an inversion of the clock signal, and wherein, When selecting the scan data input when the clock enable control indicates that the output is to be prohibited from toggling, the control circuit is configured to set the input of the latch to a constant logic state.

8. A method in an integrated circuit IC including at least a storage element, the method comprising: selecting between a functional data input and a scan data input to be used as an input to the storage element in response to a scan enable control; selectively disabling toggling of an output of the storage element by gating a clock signal provided to the storage element in response to a clock enable control; and when the clock enable control indicates that the output of the storage element is to be prohibited from toggling, selecting the input of the storage element as the scan data input.

9. The method according to claim 8, wherein the storage element includes one or more latches, and wherein selecting the scan data input includes preventing any of the latches from toggling while the output is prohibited from toggling, regardless of whether the functional data input is toggling.

10. The method according to claim 9, wherein preventing the latch from toggling is performed without adding a delay to the functional data input.

11. The method according to claim 8, wherein selecting the scan data input comprises: When the clock enable control indicates that the output is to be prohibited from toggling back and forth, the input to the storage element is set to a constant logic state, regardless of whether the functional data input is toggling.

12. The method of claim 8, wherein selecting the scan data input includes disabling the clock signal in response to the clock enable control and setting the storage element to scan mode using a logic gate.

13. The method of claim 8, wherein selecting the scan data input includes disabling the clock signal in response to the clock enable control and setting the input to the storage element to a constant logic state using a logic gate.

14. The method of claim 8, wherein the storage element includes a latch clocked by the inverse of the clock signal, and wherein selecting the scan data input includes setting the input to the latch to a constant logic state when the clock enable control indicates that the output is to be prohibited from toggling back and forth.

15. An apparatus including a processor, the processor including (i) an acquisition circuit configured to acquire instructions, and (ii) an execution circuit configured to execute the instructions, wherein one or both of the acquisition circuit and the execution circuit include: a storage element; and a control circuit configured to: select between a functional data input and a scan data input to be used as the input to the storage element in response to a scan enable control; selectively disable toggling of the output of the storage element by gating the clock signal provided to the storage element in response to a clock enable control; and select the input to the storage element as the scan data input when the clock enable control indicates that the output of the storage element is to be prohibited from toggling back and forth.

16. The apparatus of claim 15, further including a display device and one or more input devices.

17. The apparatus according to claim 15, wherein the storage element includes one or more latches, and wherein, When selecting the scan data input, the control circuit is configured to prevent any of the latches in the latch from toggling in the case where the output is prohibited from toggling back and forth, regardless of whether the functional data input is toggling.

18. The device according to claim 15, wherein, By selecting the scan data input in the case where the clock enable control indicates that the output is to be prohibited from toggling back and forth, the control circuit is configured to set the input to the storage element to a constant logic state, regardless of whether the functional data input is toggling.

19. The apparatus of claim 15, wherein the control circuit includes a logic gate configured to set the storage element to scan mode by disabling the clock signal in response to the clock enable control.

20. The apparatus of claim 15, wherein the control circuit includes a logic gate configured to set the input to the storage element to a constant logic state by disabling the clock signal in response to the clock enable control.

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