A packaging body and packaging method thereof

Abstract

The present application provides a package and a packaging method thereof, wherein the package includes a substrate, a chip, a sealing layer and a conductive layer; wherein the chip is located on one side of the substrate, the non-functional surface of the chip faces the substrate, the non-functional surface of the chip is provided with a first groove, and the first groove extends from the non-functional surface of the chip to the first grounding pad on the functional surface of the chip; the sealing layer and the chip are arranged on the same side of the substrate, and the sealing layer is arranged around the chip; the conductive layer is located between the substrate and the chip, and partially extends into the first groove to electrically connect the first grounding pad with the second grounding pad on the substrate, and the conductive layer extends from the non-functional surface of the chip to the sealing layer. In the present application, the conductive layer is designed to extend from the non-functional surface of the chip to the sealing layer, so that the orthographic projection of the conductive layer on the substrate is larger than the orthographic projection of the chip on the substrate, so that the package can be applied to high-power devices.

Description

Technical Field

[0001] The present application belongs to the field of semiconductors, and specifically relates to a package and a packaging method thereof. Background Art

[0002] Integrated circuit packaging not only serves to electrically connect the bonding points inside the integrated circuit chip to the outside, but also provides a stable and reliable working environment for the integrated circuit chip, and plays a role in mechanical or environmental protection of the integrated circuit chip, so that the integrated circuit chip can function normally and ensure its high stability and reliability.

[0003] Specifically, packaging is to place the bare IC die on a substrate that serves as a carrier, lead out the pins, and then fix the package into a whole. Packaging can not only place, fix, seal, protect the chip and enhance the electrical and thermal performance, but also serve as a bridge between the internal world of the chip and the external circuit. Therefore, for many integrated circuit products, packaging technology is a very critical link and has an important impact on the performance and performance of the chip itself.

[0004] In short, the quality of integrated circuit packaging has a great impact on the overall performance of the integrated circuit. Therefore, the package should have strong mechanical properties, good electrical properties, heat dissipation performance and chemical stability. At present, the packaging quality and packaging integration can still be further improved. Summary of the invention

[0005] The present application provides a package body and a packaging method thereof, which can improve packaging quality and packaging integration.

[0006] In order to solve the above technical problems, a technical solution adopted by the present application is: the present application provides a package, which includes a substrate, a chip, a sealing layer and a conductive layer; wherein the chip is located on one side of the substrate, the non-functional surface of the chip faces the substrate, and the non-functional surface of the chip is provided with a first groove, and the first groove extends from the non-functional surface of the chip to the first grounding pad on the functional surface of the chip; the sealing layer and the chip are arranged on the same side of the substrate, and the sealing layer is arranged around the chip; the conductive layer is located between the substrate and the chip, and partially extends into the first groove to electrically connect the first grounding pad with the second grounding pad on the substrate, and the conductive layer extends from the non-functional surface of the chip to the orthographic projection of the sealing layer on the substrate.

[0007] Another technical solution adopted in the present application is: providing a packaging method, the method comprising: placing a chip on a temporary carrier, with the functional surface of the chip facing the temporary carrier; forming a sealing layer on the periphery of the chip; opening a first groove on the non-functional surface of the chip, the first groove extending from the non-functional surface of the chip to the first grounding pad on the functional surface of the chip; forming a conductive layer on the non-functional surface of the chip, wherein part of the conductive layer extends into the first groove, and part extends from the non-functional surface of the chip to the sealing layer; removing the temporary carrier; electrically connecting the conductive layer to the second grounding pad on the substrate, so that the first grounding pad is electrically connected to the second grounding pad through the conductive layer.

[0008] The beneficial effects of the present application are as follows: by extending the conductive layer from the non-functional surface of the chip to the sealing layer, the orthographic projection of the conductive layer on the substrate is larger than the orthographic projection of the chip on the substrate, thereby improving the chip's anti-interference and anti-static field impact performance, and reducing the risk of the chip being broken down by the electrostatic field, so that the package can be suitable for high-power devices, while having the advantages of high integration and a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0010] Figure 1 It is a schematic structural diagram of an embodiment of a package in the present application;

[0011] Figure 2 is a schematic diagram of the process of preparing the encapsulation body in the present application;

[0012] Figure 3 yes Figure 2 Step S1 corresponds to a structural schematic diagram of an embodiment;

[0013] Figure 4 yes Figure 2 Steps S2-S5 correspond to a schematic structural diagram of an embodiment;

[0014] Figure 5 yes Figure 2 Schematic diagram of the process corresponding to step S6;

[0015] Figure 6 yes Figure 5 The steps in the figure correspond to a schematic diagram of a structure of an embodiment;

[0016] Figure 7 yes Figure 2 Step S7 corresponds to a structural schematic diagram of an embodiment;

[0017] Figure 8 yes Figure 2 Schematic diagram of the process of step S8;

[0018] Fig. 9 yes Figure 8 The steps in the figure correspond to a schematic diagram of a structure of an embodiment;

[0019] Fig.10 yes Figure 2 Schematic diagram of the process of step S9;

[0020] Fig.11 yes Fig.10 The steps in the figure correspond to a schematic diagram of a structure of an embodiment;

[0021] Fig.12 yes Figure 2 A structural diagram of an embodiment corresponding to step S10;

[0022] Fig.13 yes Figure 2 Schematic diagram of the process of step S11;

[0023] Fig.14 yes Fig.13 The steps in the figure correspond to a schematic diagram of a structure of an embodiment;

[0024] Fig.15 yes Figure 2 Step S12 corresponds to a structural schematic diagram of an embodiment;

[0025] Explanation of the reference numerals: 1 substrate; 11 second ground pad; 12 second signal transmission pad; 13 first solder ball; 14 first bottom fill; 2 chip; 21 non-functional surface; 22 functional surface; 23 first groove; 24 first ground pad; 25 first signal transmission pad; 26 second solder ball; 261 second solder; 27 second insulating layer; 28 second opening; 29 conductive block; 3 sealing layer; 31 through groove; 32 conductive column; 4 conductive layer; 5 first insulating layer; 51 first opening; 6 solder layer; 7 redistribution layer; 8 temporary carrier; 81 protective layer; 82 carrier; 9 second bottom fill. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] See also Figure 1The present application provides a package, which includes a substrate 1, a chip 2, a sealing layer 3 and a conductive layer 4; wherein the chip 2 is located on one side of the substrate 1, the non-functional surface 21 of the chip 2 faces the substrate 1, and the non-functional surface 21 of the chip 2 is provided with a first groove 23, and the first groove 23 extends from the non-functional surface 21 of the chip 2 to a first grounding pad 24 on the functional surface 22 of the chip 2; the sealing layer 3 and the chip 2 are arranged on the same side of the substrate 1, and the sealing layer 3 is arranged around the chip 2; the conductive layer 4 is located between the substrate 1 and the chip 2, and partially extends into the first groove 23 to electrically connect the first grounding pad 24 with the second grounding pad 11 on the substrate 1, and the conductive layer 4 extends from the non-functional surface 21 of the chip 2 to the orthographic projection of the sealing layer 3 on the substrate 1.

[0028] Specifically, the substrate 1 can provide electrical connection, protection, support, heat dissipation, assembly and other functions for the chip 2, so as to achieve various connection methods, reduce the volume of the packaged product, and improve the electrical performance and heat dissipation performance.

[0029] The chip 2 is located on one side of the substrate 1, the non-functional surface 21 of the chip 2 faces the substrate 1, so that the functional surface 22 of the chip 2 is away from the substrate 1, and the non-functional surface 21 of the chip 2 is provided with a first groove 23, and the first groove 23 extends from the non-functional surface 21 of the chip 2 to the first grounding pad 24 on the functional surface 22 of the chip 2. In other words, the first grounding pad 24 is exposed in the first groove 23.

[0030] The sealing layer 3 and the chip 2 are both located on the same side of the substrate 1, and the sealing layer 3 surrounds the chip 2, so that the sealing layer 3 can protect the chip 2, prevent water vapor from entering and damaging the chip 2, and ensure the overall performance of the package. At the same time, the sealing layer 3 also provides support for the design of the conductive layer 4, and the conductive layer 4 electrically connects the substrate 1 and the chip 2. Specifically, the conductive layer 4 is arranged between the substrate 1 and the chip 2, and part of it extends into the first groove 23, connected to the first grounding pad 24 of the chip 2, and the other part is connected to the second grounding pad 11 on the substrate 1, which plays the role of conducting the connection path between the first grounding pad 24 and the second grounding pad 11. In addition, the conductive layer 4 extends from the non-functional surface 21 of the chip 2 to the orthographic projection of the sealing layer 3 on the substrate 1, so that the orthographic projection of the conductive layer 4 on the substrate 1 is larger than the orthographic projection of the chip 2 on the substrate 1, thereby increasing the grounding area of ​​the chip 2, improving the chip's anti-interference and anti-static field impact performance, and reducing the risk of the chip being broken down by the electrostatic field, so that the package can be suitable for high-power devices, and at the same time, the package has the advantages of high integration and a wide range of applications.

[0031] Please continue reading Figure 1, the conductive layer 4 fills the first groove 23, that is, the first groove 23 is filled with the conductive layer 4. This setting can reduce the resistance of the conductive layer 4 transmission and ensure the safety performance of the transmission. Of course, in other embodiments, the conductive layer 4 may not fill the first groove 23. For example, the conductive layer 4 is formed on the groove wall of the first groove 23. In short, as long as the conductive layer 4 extends into the first groove 23 and is electrically connected to the first ground pad 24, it will be fine.

[0032] Continue reading Figure 1 In one embodiment, the package further includes a first insulating layer 5, which is located between the conductive layer 4 and the chip 2, and is provided with a first opening 51 connected to the first groove 23, and the conductive layer 4 extends from the first opening 51 to the first groove 23. The first insulating layer 5 can be used to ensure the insulation performance between the chip 2 and the conductive layer 4 located on both sides thereof, and the first opening 51 provided in the first insulating layer 5 can allow the conductive layer 4 to extend into the first groove 23. The size of the first opening 51 can match the size of the first groove 23.

[0033] Continue reading Figure 1 In one embodiment, the package further includes a solder layer 6, which is located between the conductive layer 4 and the substrate 1, and is used to electrically connect the conductive layer 4 and the second ground pad 11 on the substrate 1. In other words, the solder layer 6 is used to solder the conductive layer 4 and the second ground pad 11 on the substrate 1 together. The orthographic projection of the solder layer 6 on the substrate 1 may overlap with the second ground pad 11. Of course, in other embodiments, the orthographic projection of the solder layer 6 on the substrate 1 may be larger than the area of ​​the second ground pad 11, or smaller than the area of ​​the second ground pad 11. The solder layer 6 is made of a conductive material.

[0034] In one embodiment, the orthographic projection of the second ground pad 11 on the substrate 1 is larger than the orthographic projection of the first ground pad 24 on the substrate 1. Through this design, the electrical signal of the first ground pad 24 in the chip 2 can be effectively transmitted through the second ground pad 11, and the area of ​​the second ground pad 11 is larger, thereby increasing the grounding area of ​​the chip 2 and improving the anti-interference and anti-static field impact performance of the chip 2.

[0035] Please continue reading Figure 1 The sealing layer 3 is provided with a through groove 31, and the package body also includes a rewiring layer 7 and a conductive column 32, wherein the rewiring layer 7 is located on the side of the chip 2 and the sealing layer 3 away from the substrate 1, and is electrically connected to the first signal transmission pad 25 on the functional surface 22 of the chip 2; the conductive column 32 is arranged in the through groove 31, the first end of the conductive column 32 is electrically connected to the rewiring layer 7, and the second end is electrically connected to the second signal transmission pad 12 on the substrate 1.

[0036] Specifically, the rewiring layer 7 is electrically connected to the first signal transmission pad 25 on the functional surface 22 of the chip 2, so that the rewiring layer 7 can lead out the electrical signal on the first signal transmission pad 25 on the chip 2. The combination of the rewiring layer 7 and the conductive column 32 realizes electrical signal conduction between the first signal transmission pad 25 and the second signal transmission pad 12, and realizes the design of fan-out. The design of the rewiring layer 7 and the conductive column 32 replaces the wire bonding method in the prior art, which is simple in process and can reduce the area of ​​the package.

[0037] Continue reading Figure 1 In one embodiment, a first solder ball 13 is disposed on the second end of the conductive pillar 32, and the first solder ball 13 electrically connects the conductive pillar 32 and the second signal transmission pad 12. During preparation, the first solder ball 13 can be formed by reflow, which can play a role in fixing the conductive pillar 32 and the second signal transmission pad 12.

[0038] In one embodiment, the package further includes a first underfill 14, which is filled in the gap between the sealing layer 3 and the substrate 1. Specifically, the first underfill 14 filled between the sealing layer 3 and the substrate 1 surrounds the first solder ball 13, and at the same time wraps around the conductive layer 4, the first insulating layer 5 and the solder layer 6, which is conducive to effectively filling the position between the first solder ball 13 and the conductive layer 4, and protecting the structural stability of the package.

[0039] Please continue reading Figure 1 A second solder ball 26 is disposed on the first signal transmission pad 25 of the chip 2, and the second solder ball 26 electrically connects the rewiring layer 7 with the first signal transmission pad 25. Specifically, the second solder ball 26 is made of a conductive material, so that the electrical signal conduction between the rewiring layer 7 and the first signal transmission pad 25 can be achieved.

[0040] Continue reading Figure 1 In one embodiment, the package further includes a second insulating layer 27 and a conductive block 29, the second insulating layer 27 is located between the chip 2 and the redistribution layer 7, and is provided with a second opening 28 exposing the first signal transmission pad 25; the conductive block 29 is arranged in the second opening 28 and is electrically connected to the first signal transmission pad 25, wherein the second solder ball 26 is arranged on a side surface of the conductive block 29 away from the chip 2.

[0041] Specifically, the second insulating layer 27 serves to isolate the chip 2 from the rewiring layer 7, so that the circuits between the chip 2 and the rewiring layer 7 will not crosstalk. Since the second insulating layer 27 is located on the side of the functional surface 22 of the chip 2, by opening a second opening 28 in the second insulating layer 27 at the position of the first signal transmission pad 25, and arranging a conductive block 29 in the second opening 28, the electrical signal on the first signal transmission pad 25 is transmitted to the rewiring layer 7 through the conductive block 29. This method is easy to prepare and can effectively lead the electrical signal on the first signal transmission pad 25 in the chip 2 to the rewiring layer 7.

[0042] Please continue reading Figure 1 The package body further includes a protective layer 81, which is located on the side of the rewiring layer 7 away from the substrate 1; by arranging the protective layer 81 on the side of the rewiring layer 7 away from the substrate 1, it is beneficial to protect the rewiring layer 7.

[0043] Continue reading Figure 1 In one embodiment, the package further includes a second underfill 9, which is filled in the gap between the chip 2 and the protective layer 81. Specifically, the second underfill 9 is arranged around the second solder ball 26, ensuring the stability of the positional relationship between the second solder ball 26 and the chip 2, and preventing water vapor from invading and damaging the second solder ball 26, thereby improving the overall structural stability of the package.

[0044] See also Figure 2 The present application also provides a packaging method, the method comprising:

[0045] S1: forming a redistribution layer 7 on a temporary carrier 8.

[0046] See also Figure 2 and Figure 3 ,like Figure 3 As shown, the temporary carrier 8 includes a stacked carrier 82 and a protective layer 81. Specifically, a temporary bonding glue can be coated on the carrier 82, and then the protective layer 81 is prepared on the side of the temporary bonding glue facing away from the carrier 82. In one embodiment, the protective layer 81 can be prepared by coating, and the protective layer 81 can be a polyimide (PI) film layer.

[0047] The preparation of the rewiring layer 7 can be performed by first sputtering a seed layer, and then reserving a preparation position of the rewiring layer 7 on the protective layer 81 by means of coating, exposure, and development, and preparing the rewiring layer 7 by means of electroplating, and removing the remaining part of the seed layer by means of degumming, metal etching, etc., to complete the preparation of the rewiring layer 7. The prepared rewiring layer 7 is as follows: Figure 3 As shown, specifically, the material of the rewiring layer 7 may include at least one of metal materials such as copper (Cu), aluminum (Al), nickel (Ni), and gold (Au).

[0048] S2 : forming a second insulating layer 27 on the functional surface 22 of the chip 2 .

[0049] Specifically, the wafer (whose material may be silicon or a compound semiconductor) includes a plurality of chips 2. During preparation, in this embodiment, a second insulating layer 27 is formed on the functional surface of the wafer, thereby forming a second insulating layer 27 on the functional surface of the chip 2.

[0050] Of course, in other implementations, the wafer may be cut first to obtain a plurality of independent chips 2 , and then the second insulating layer 27 may be formed on the functional surface 22 of the chip 2 .

[0051] The material of the second insulating layer 27 may be silicon dioxide (SiO 2 ) or a photosensitive polymer adhesive, such as PI adhesive.

[0052] The second insulating layer 27 may be formed by any method, such as a CVD (chemical vapor deposition) process or a coating process.

[0053] S3 : opening a second opening 28 on the second insulating layer 27 to expose the first signal transmission pad 25 .

[0054] like Figure 4 As shown, a second opening 28, i.e., a window, is prepared in the second insulating layer 27 at a position corresponding to the first signal transmission pad 25 to expose the pad of the chip 2 for subsequent signal transmission. Specifically, when the material of the second insulating layer 27 is SiO2, the window can be opened by means of glue coating, photolithography and dry etching; when the material of the second insulating layer 27 is PI material, the window can be opened by means of photolithography and development.

[0055] S4 : forming a conductive block 29 electrically connected to the first signal transmission pad 25 in the second opening 28 , and subsequently forming a second solder ball 26 on the conductive block 29 .

[0056] like Figure 4 As shown, a conductive block 29 is prepared in the second opening 28, and the conductive block 29 is electrically connected to the first signal transmission pad 25. The conductive block 29 can be prepared by processes such as sputtering a seed layer, coating, exposing, developing, electroplating, degumming, metal etching, and removing a seed layer. The material of the conductive block 29 may include one or more metal materials such as Cu, Al, Ni, and Au.

[0057] S5 : forming a second solder ball 26 on the first signal transmission pad 25 of the chip 2 , and subsequently the chip 2 is electrically connected to the rewiring layer 7 via the second solder ball 26 .

[0058] like Figure 4As shown, the second solder 261 is coated on the conductive block 29. The second solder 261 can also be prepared by an electroplating process, and the second solder ball 26 is obtained by a reflow process. Figure 4 The solder may be tin or an alloy containing tin, such as a tin-silver alloy or a tin-lead alloy. After the second solder ball 26 is prepared, the chip 2 and the rewiring layer 7 may be connected via the second solder ball 26 .

[0059] Then, the chips 2 on the wafer are cut to obtain single chips 2 on which second solder balls 26 are prepared.

[0060] S6 : placing the chip 2 on the temporary carrier 8 , with the functional surface 22 of the chip 2 facing the temporary carrier 8 .

[0061] See also Figure 5 and Figure 6 Specifically, step S6 includes:

[0062] S61 : placing the chip 2 on the side of the rewiring layer 7 away from the temporary carrier 8 , and electrically connecting the first signal transmission pad 25 on the functional surface 22 of the chip 2 to the rewiring layer 7 .

[0063] like Figure 6 As shown, the chip 2 is electrically connected to the rewiring layer 7 through the second solder ball 26. The second solder ball 26 contains tin material, and tin welding can firmly bond metal materials, and has good conductivity and corrosion resistance. Therefore, the second solder ball 26 can fix the chip 2 and the rewiring layer 7, so that the first signal transmission pad 25 on the functional surface 22 of the chip 2 is electrically connected to the rewiring layer 7.

[0064] S62 : filling the gap between the chip 2 and the temporary carrier 8 with a second underfill 9 .

[0065] The second underfill 9 can be prepared by a dispensing process, specifically, as Figure 6 As shown, the underfill is filled between the chip 2 and the temporary carrier 8 and cured at high temperature, so that the second underfill 9 wraps the second solder ball 26 and the filling effect is good.

[0066] S7 : forming a sealing layer 3 on the periphery of the chip 2 .

[0067] See also Figure 7 The sealing layer 3 can protect the chip 2 from being corroded by water vapor. Specifically, step S7 includes:

[0068] S71 : forming a sealing layer 3 on the periphery of the chip 2 , wherein the orthographic projection of the sealing layer 3 on the temporary carrier 8 overlaps with the orthographic projection of the rewiring layer 7 on the temporary carrier 8 .

[0069] The sealing layer 3 is located outside the chip 2 to protect the chip 2 from external water vapor erosion. At the same time, the orthographic projection of the sealing layer 3 on the temporary carrier 8 overlaps with the orthographic projection of the rewiring layer 7 on the temporary carrier 8, so that the sealing layer 3 protects at least the portion of the rewiring layer 7 protruding from the chip 2.

[0070] S8 : opening a first groove 23 on the non-functional surface 21 of the chip 2 , wherein the first groove 23 extends from the non-functional surface 21 of the chip 2 to the first ground pad 24 on the functional surface 22 of the chip 2 .

[0071] See also Figure 8 and Fig. 9 , step S8 comprises:

[0072] S81 : forming a first insulating layer 5 on the non-functional surface 21 of the chip 2 .

[0073] like Fig. 9 As shown, a first insulating layer 5 is formed on the side of the chip 2 facing away from the temporary carrier 8 , that is, the first insulating layer 5 covers the non-functional surface 21 of the chip 2 .

[0074] S82 : forming a first opening 51 on the first insulating layer 5 to expose the non-functional surface 21 of the chip 2 , and forming a first groove 23 on the exposed non-functional surface 21 .

[0075] like Fig. 9 As shown, a first opening 51 is firstly opened at a position of the first insulating layer 5 corresponding to the first grounding pad 24 to expose the non-functional surface 21 of the chip 2, and then a first groove 23 is opened on the exposed non-functional surface 21 of the chip 2, and the first groove 23 extends to the first grounding pad 24.

[0076] Of course, in other embodiments, the first opening 51 and the first groove 23 can be prepared at the same time. The first groove 23 can be prepared by processes such as coating, photolithography, and dry etching (deep ion reaction etching). After the first ground pad 24 is exposed, the preparation of the first groove 23 is completed, and then the materials required for preparing the first groove 23, such as photoresist, are removed.

[0077] S9: forming a conductive layer 4 on the non-functional surface 21 of the chip 2 , wherein a portion of the conductive layer 4 extends into the first groove 23 , and a portion of the conductive layer 4 extends from the non-functional surface 21 of the chip 2 to the sealing layer 3 .

[0078] See also Fig.10 and Fig.11 , step S9 specifically includes:

[0079] S91 : forming a conductive layer 4 on a side of the first insulating layer 5 facing away from the chip 2 .

[0080] like Fig.11As shown, the conductive layer 4 leads out the ground signal on the first ground pad 24, part of the conductive layer 4 extends into the first groove 23, and part of it extends from the non-functional surface 21 of the chip 2 to the sealing layer 3; at the same time, the orthographic projection of the conductive layer 4 on the temporary carrier 8 is larger than the orthographic projection of the chip 2 on the temporary carrier 8, so that the conductive layer 4 protrudes out of the chip 2 setting and part of it extends to the sealing layer 3.

[0081] The conductive layer 4 can be formed by process flows such as sputtering a seed layer, coating, exposing, developing, electroplating, debonding, and metal etching a seed layer. The material of the conductive layer 4 is metal, specifically, it can be one or more metals such as Cu, Al, Ni, and Au.

[0082] After step S9, the method further includes:

[0083] S92 : Opening a through groove 31 in the sealing layer 3 to expose the redistribution layer 7 .

[0084] like Fig.11 As shown, a through groove 31 is formed on the sealing layer 3 at a position corresponding to the rewiring layer 7 to expose at least a portion of the rewiring layer 7. The process of forming the through groove 31 may be laser drilling, laser induced etching or dry etching, etc., which is not limited here.

[0085] S93 : forming a conductive pillar 32 electrically connected to the redistribution layer 7 in the through groove 31 .

[0086] like Fig.11 As shown, the conductive pillar 32 is electrically connected to the rewiring layer 7. The conductive pillar 32 can be made by processes such as sputtering a seed layer, coating, exposure, development, electroplating, debonding, and metal etching a seed layer. The material of the conductive pillar 32 is metal, specifically, one or more metals such as Cu, Al, Ni, and Au.

[0087] S94 : forming a first solder ball 13 on the conductive pillar 32 , so that the subsequent conductive pillar 32 is electrically connected to the second signal transmission pad 12 through the first solder ball 13 .

[0088] like Fig.11 As shown, the first solder ball 13 on the conductive column 32 can be made by printing, ball planting or electroplating process, and reflow soldering process, and the solder of the first solder ball 13 can be tin or a tin-containing alloy, such as tin-silver alloy, tin-lead alloy, etc. The conductive column 32 is subsequently connected to the second signal transmission pad 12 through the first solder ball 13 to achieve electrical signal transmission.

[0089] S95: forming a solder layer 6 on the side of the conductive layer 4 facing away from the chip 2;

[0090] like Fig.11As shown, solder is applied by printing or electroplating process, and then solder layer 6 is made by reflow process, and the solder of solder layer 6 can be tin or tin-containing alloy, such as tin-silver alloy, tin-lead alloy, so that solder layer 6 can play the role of connection and electrical signal transmission.

[0091] In one embodiment, the first solder ball 13 and the solder layer 6 may be prepared simultaneously using the same material and the same process, or they may be prepared separately.

[0092] S10: removing the temporary carrier plate 8.

[0093] See also Fig.12 The temporary carrier 8 includes a carrier sheet 82 and a protective layer 81 which are stacked. Specifically, step S10 includes:

[0094] S101: Remove the slide 82.

[0095] The carrier sheet 82 provides support for the structure preparation in the above steps. The volume of the package can be further reduced by removing the carrier sheet 82. In addition, the protective layer 81 is retained in the package to protect the rewiring layer 7 and the chip 2.

[0096] Specifically, the carrier sheet 82 may be removed by a debonding process to remove the carrier sheet 82 and the bonding adhesive, and retain the protective layer 81 of the temporary carrier 8 in the package.

[0097] In one embodiment, after the carrier sheet 82 is removed, the sealing layer 3 is cut to obtain a single plastic-sealed chip 2 .

[0098] S11 : electrically connecting the conductive layer 4 to the second ground pad 11 on the substrate 1 , so that the first ground pad 24 is electrically connected to the second ground pad 11 through the conductive layer 4 .

[0099] See also Fig.13 and Fig.14 Specifically, step S11 includes:

[0100] S111 : electrically connecting the solder layer 6 to the second ground pad 11 on the substrate 1 .

[0101] like Fig.14 As shown, after the solder layer 6 and the second ground pad 11 are aligned, the solder layer 6 and the second ground pad 11 can be electrically connected through a reflow process to achieve signal transmission.

[0102] At the same time as step S11, it also includes:

[0103] S112 : electrically connecting the conductive pillar 32 to the second signal transmission pad 12 on the substrate 1 .

[0104] like Fig.14 As shown, the first solder ball 13 is aligned with the second signal transmission pad 12, and the first solder ball 13 and the second signal transmission pad 12 are electrically connected through a reflow process to achieve signal transmission.

[0105] S12 : filling the gap between the sealing layer 3 and the substrate 1 with a first underfill 14 .

[0106] See also Fig.15 , prepare the first underfill 14, which is located in the gap between the sealing layer 3 and the substrate 1 and wraps the first solder ball 13 to protect the overall structural stability of the package. Specifically, the first underfill 14 can be filled between the chip 2 and the substrate 1 by a dispensing process and cured at high temperature to complete the preparation of the first underfill 14.

[0107] In the package in the present application, the conductive layer 4 extends from the non-functional surface 21 of the chip 2 to the sealing layer 3, so that the positive projection of the conductive layer 4 on the substrate 1 is greater than the positive projection of the chip 2 on the substrate 1, so the package can be applied to high-power devices, and has the advantages of high integration and wide application range. At the same time, the package in the present application has high packaging integration, small packaging volume, strong system, and high power density, which caters to the development trend of miniaturization, complexity and integration of integrated circuits. In addition, the packaging method in the present application, by making the non-functional surface 21 of the chip 2 relative to the substrate 1, the single chip located on the wafer after the initial processing (to obtain the second solder ball 26) is cut, and then plastic-sealed, so that the conductive layer 4 can extend to the sealing layer 3, and the grounding area of ​​the first grounding pad 24 in the chip 2 is expanded; after plastic sealing, the chip 2 is cut again, and after obtaining the single chip 2, the fan-out technology is applied to lead out the signal in the chip 2, and a package with a small volume and suitable for high-power devices is prepared.

[0108] The above description is only an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A package, It is characterized in that The package comprises: substrate; A chip is located at one side of the substrate, the non-functional surface of the chip faces the substrate, the non-functional surface of the chip is provided with a first groove, and the first groove extends from the non-functional surface of the chip to a first ground pad on the functional surface of the chip; A sealing layer, which is arranged on the same side of the substrate as the chip and surrounds the chip; a conductive layer, located between the substrate and the chip, and partially extending into the first groove to electrically connect the first grounding pad with the second grounding pad on the substrate, and the conductive layer extends from the non-functional surface of the chip to within the orthographic projection of the sealing layer on the substrate; Wherein, the sealing layer is provided with a through groove, and the packaging body further comprises: A rewiring layer, located on a side of the chip and the sealing layer away from the substrate, and electrically connected to the first signal transmission pad on the functional surface of the chip; A conductive column is disposed in the through groove, wherein a first end of the conductive column is electrically connected to the redistribution layer, and a second end of the conductive column is electrically connected to a second signal transmission pad on the substrate.

2. The package according to claim 1, It is characterized in that The conductive layer fills the first groove.

3. The package according to claim 2, It is characterized in that The package body further includes a first insulating layer, which is located between the conductive layer and the chip and has a first opening communicating with the first groove. The conductive layer extends from the first opening into the first groove.

4. The package according to claim 3, It is characterized in that The package body further includes a solder layer located between the conductive layer and the substrate, electrically connecting the conductive layer and the second ground pad on the substrate.

5. The package according to claim 4, It is characterized in that An orthographic projection of the second ground pad on the substrate is larger than an orthographic projection of the first ground pad on the substrate.

6. The package according to claim 1, It is characterized in that A first solder ball is disposed on the second end of the conductive column, and the first solder ball electrically connects the conductive column and the second signal transmission pad.

7. The package according to claim 6, It is characterized in that The package body further includes a first underfill filled in the gap between the sealing layer and the substrate.

8. The package according to claim 1, It is characterized in that A second solder ball is disposed on the first signal transmission pad of the chip, and the second solder ball electrically connects the redistribution layer and the first signal transmission pad.

9. The package according to claim 8, It is characterized in that The package further comprises: A second insulating layer, located between the chip and the rewiring layer, and having a second opening exposing the first signal transmission pad; A conductive block is disposed in the second opening and electrically connected to the first signal transmission pad, wherein the second solder ball is disposed on the conductive block.

10. The package according to claim 1, It is characterized in that The package further comprises: The protection layer is located on a side of the rewiring layer away from the substrate.

11. The package according to claim 10, It is characterized in that The package further comprises: The second underfill is filled in the gap between the chip and the protection layer.

12. A packaging method, It is characterized in that The method comprises: Placing a chip on a temporary carrier, with the functional surface of the chip facing the temporary carrier; forming a sealing layer on the periphery of the chip; A first groove is formed on the non-functional surface of the chip, wherein the first groove extends from the non-functional surface of the chip to a first ground pad on the functional surface of the chip; forming a conductive layer on the non-functional surface of the chip, wherein a portion of the conductive layer extends into the first groove, and a portion of the conductive layer extends from the non-functional surface of the chip to the sealing layer; removing the temporary carrier plate; electrically connecting the conductive layer to a second ground pad on the substrate, so that the first ground pad is electrically connected to the second ground pad through the conductive layer; Before placing the chip on the temporary carrier, the method further includes: forming a rewiring layer on the temporary carrier; The step of placing the chip on the temporary carrier includes: placing the chip on the side of the rewiring layer away from the temporary carrier, and electrically connecting the first signal transmission pad on the chip functional surface to the rewiring layer; The step of forming a sealing layer on the periphery of the chip comprises: forming the sealing layer at the periphery of the chip, wherein the orthographic projection of the sealing layer on the temporary carrier overlaps with the orthographic projection of the rewiring layer on the temporary carrier; After forming a conductive layer on the non-functional surface of the chip, the method further comprises: A through groove is formed on the sealing layer to expose the rewiring layer; A conductive column electrically connected to the redistribution layer is formed in the through groove, wherein the conductive column is subsequently electrically connected to a second signal transmission pad on the substrate.

13. The packaging method according to claim 12, It is characterized in that The step of opening a first groove on the non-functional surface of the chip comprises: forming a first insulating layer on a non-functional surface of the chip; forming a first opening on the first insulating layer to expose the non-functional surface of the chip, and forming the first groove on the exposed non-functional surface; The step of forming a conductive layer on the non-functional surface of the chip comprises: The conductive layer is formed on a side of the first insulating layer away from the chip.

14. The packaging method according to claim 12, It is characterized in that After forming a conductive layer on the non-functional surface of the chip, the method further comprises: forming a first solder ball on the conductive column, so that the conductive column is subsequently electrically connected to the second signal transmission pad through the first solder ball; and / or; forming a solder layer on a side of the conductive layer facing away from the chip; While electrically connecting the conductive layer to the second ground pad on the substrate, the method further includes: The conductive pillar is electrically connected to a second signal transmission pad on the substrate.

15. The packaging method according to claim 14, It is characterized in that The step of electrically connecting the conductive layer to the second ground pad on the substrate comprises: The solder layer is electrically connected to the second ground pad on the substrate.

16. The packaging method according to claim 15, It is characterized in that After the conductive pillar is electrically connected to the second signal transmission pad on the substrate, the method further includes: A first underfill is filled in the gap between the sealing layer and the substrate.

17. The packaging method according to claim 12, It is characterized in that Before placing the chip on the temporary carrier, the method further includes: A second solder ball is formed on the first signal transmission pad of the chip, and subsequently the chip is electrically connected to the redistribution layer through the second solder ball.

18. The packaging method according to claim 17, It is characterized in that Before forming a second solder ball on the first signal transmission pad of the chip, the method further includes: forming a second insulating layer on the functional surface of the chip; Opening a second opening on the second insulating layer to expose the first signal transmission pad; A conductive block electrically connected to the first signal transmission pad is formed in the second opening, wherein the second solder ball is subsequently formed on the conductive block.

19. The packaging method according to claim 12, It is characterized in that The temporary carrier plate includes a carrier sheet and a protective layer which are stacked; The step of removing the temporary carrier plate comprises: The slide is removed.

20. The packaging method according to claim 19, It is characterized in that After placing the chip on the side of the rewiring layer away from the temporary carrier and electrically connecting the first signal transmission pad on the chip functional surface to the rewiring layer, the method further includes: A second underfill is filled in the gap between the chip and the temporary carrier.

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