Shift register, gate driving circuit and display device
By optimizing the circuit structure and transistor type of the shift register, and combining noise reduction circuits and capacitor design, the problems of complexity and large space occupation of shift registers in the prior art have been solved, and the narrow bezel design of the display device and the stability of signal output have been achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2022-03-24
- Publication Date
- 2026-05-12
AI Technical Summary
The existing gate drive circuit for light emission control has a complex internal shift register circuit structure, occupies a large space, and is difficult to implement a narrow bezel design.
A shift register was designed, including an input circuit, a first control circuit, a second control circuit, and an output circuit. It adopts a simple transistor and capacitor structure, combined with noise reduction circuit and capacitor design, optimizes the transistor type to adapt to low-temperature polycrystalline oxide technology, reduces the number of signal terminals, and simplifies the circuit structure.
The shift register has a simple circuit structure and small footprint, which is beneficial for the narrow bezel design of display devices. Furthermore, the combination of capacitors and transistors ensures the stability and reliability of signal output.
Smart Images
Figure CN117413310B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display, and in particular to a shift register, a gate driving circuit, and a display device. Background Technology
[0002] With the development of display technology, pixel driving circuits typically include light-emitting control transistors (LEDs) to control whether the driving transistors output driving current. These LEDs are generally controlled by light-emitting control signal lines. Corresponding gate driving circuits are required for these light-emitting control signal lines.
[0003] In the existing technology, the Gate Driver on Array (GOA) technology is used to integrate the transistors in the gate driver circuit for light emission control onto the array substrate to scan and drive the light emission control signal lines in the display panel. This eliminates the need for a gate driver IC and is beneficial for achieving narrow bezels.
[0004] However, in practical applications, it has been found that the existing shift register circuit in the gate drive circuit for light emission control has a complex circuit structure and occupies a large space. Summary of the Invention
[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a shift register, a gate driving circuit and a display device.
[0006] In a first aspect, embodiments of this disclosure provide a shift register, wherein:
[0007] An input circuit, coupled to a signal input terminal, a first clock signal terminal, and a third node, is configured to control the writing of a signal provided by the signal input terminal to the third node in response to a signal provided by the first clock signal terminal.
[0008] A first control circuit is coupled to a first power supply terminal, a preset control signal terminal, a second clock signal terminal, and a first node, and is configured to control the writing of the voltage provided by the first power supply terminal to the first node in response to the signal provided by the preset control signal terminal and the signal provided by the second clock signal terminal.
[0009] A second control circuit, coupled to a second power supply terminal, the signal input terminal, and the first node, is configured to control the writing of the voltage provided by the second power supply terminal to the first node in response to a signal provided by the signal input terminal.
[0010] An output circuit, coupled to a signal output terminal, a first power supply terminal, a second power supply terminal, a first node, and a fourth node, is configured to write the voltage provided by the second power supply terminal to the signal output terminal in response to voltage control at the first node, and to write the voltage provided by the first power supply terminal to the signal output terminal in response to voltage control at the fourth node, wherein the third node is coupled to the fourth node.
[0011] In some embodiments, the first control circuit includes: a first transistor and a second transistor;
[0012] The control electrode of the first transistor is coupled to the preset control signal terminal, the first electrode of the first transistor is coupled to the first power supply terminal, and the second electrode of the first transistor is coupled to the first electrode of the second transistor.
[0013] The control electrode of the second transistor is coupled to the second clock signal terminal, and the second electrode of the second transistor is coupled to the first node.
[0014] In some embodiments, the first control circuit includes: a first transistor and a second transistor;
[0015] The control electrode of the first transistor is coupled to the preset control signal terminal, the first electrode of the first transistor is coupled to the second electrode of the second transistor, and the second electrode of the first transistor is coupled to the first node;
[0016] The control terminal of the second transistor is coupled to the second clock signal terminal, and the first terminal of the second transistor is coupled to the first power supply terminal.
[0017] In some embodiments, the preset control signal terminal is the third node.
[0018] In some embodiments, the preset control signal terminal is the signal input terminal.
[0019] In some embodiments, the first transistor is an N-type transistor, and all other transistors in the shift register, except for the first transistor, are P-type transistors.
[0020] In some embodiments, the first transistor is a metal-oxide-semiconductor transistor, and the other transistors in the shift register, excluding the first transistor, are all low-temperature polysilicon transistors.
[0021] In some embodiments, the second control circuit includes: a third transistor;
[0022] The control electrode of the third transistor is coupled to the signal input terminal, the first electrode of the third transistor is coupled to the second power supply terminal, and the second electrode of the third transistor is coupled to the first node.
[0023] In some embodiments, the input circuit includes: a fourth transistor;
[0024] The control electrode of the fourth transistor is coupled to the first clock signal terminal, the first electrode of the fourth transistor is coupled to the signal input terminal, and the second electrode of the fourth transistor is coupled to the third node.
[0025] In some embodiments, the output circuit includes a seventh transistor and an eighth transistor;
[0026] The control electrode of the seventh transistor is coupled to the fourth node, the first electrode of the seventh transistor is coupled to the first power supply terminal, and the second electrode of the seventh transistor is coupled to the signal output terminal.
[0027] The control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the signal output terminal, and the second electrode of the eighth transistor is coupled to the second power supply terminal.
[0028] In some embodiments, the shift register further includes: a noise reduction circuit coupled to the second power supply terminal, the first node, and the third node, configured to write the voltage provided by the second power supply terminal to the third node in response to control of the voltage at the first node.
[0029] In some embodiments, the noise reduction circuit includes: a fifth transistor;
[0030] The control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the third node, and the second electrode of the fifth transistor is coupled to the second power supply terminal.
[0031] In some embodiments, the shift register further includes: a first capacitor;
[0032] The first terminal of the first capacitor is coupled to the second clock signal terminal, and the second terminal of the first capacitor is coupled to the fourth node.
[0033] In some embodiments, the shift register further includes a sixth transistor located between the third node and the fourth node, the third node being coupled to the fourth node via the sixth transistor;
[0034] The control electrode of the sixth transistor is coupled to the first power supply terminal, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the fourth node.
[0035] In some embodiments, the shift register further includes a second capacitor;
[0036] The first end of the second capacitor is coupled to the first node, and the second end of the second capacitor is coupled to either the first power supply terminal or the second power supply terminal.
[0037] In a second aspect, embodiments of this disclosure also provide a gate driving circuit, comprising: a plurality of cascaded shift registers, wherein the shift registers are the shift registers provided in the first aspect above;
[0038] The signal input terminal of the shift register located in the first stage is coupled to the frame start signal terminal;
[0039] The signal input terminal of any shift register other than the first stage is coupled to the signal output terminal of the shift register of the previous stage.
[0040] Thirdly, embodiments of this disclosure also provide a display device, which includes: the gate driving circuit as described in the second aspect above. Attached Figure Description
[0041] Figure 1 A schematic diagram of the circuit structure of a shift register provided in an embodiment of this disclosure;
[0042] Figure 2 A schematic diagram of another specific circuit structure of the shift register provided in the embodiments of this disclosure;
[0043] Figure 3 A schematic diagram of another specific circuit structure of the shift register provided in the embodiments of this disclosure;
[0044] Figure 4 for Figure 3 The diagram shows a timing diagram of one type of shift register.
[0045] Figure 5 This is a schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;
[0046] Figure 6 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;
[0047] Figure 7 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;
[0048] Figure 8 A schematic diagram of the circuit structure of another shift register provided in an embodiment of this disclosure;
[0049] Figure 9 for Figure 8 The diagram shows a timing diagram of one type of shift register.
[0050] Figure 10 A schematic diagram of the circuit structure of another shift register provided in an embodiment of this disclosure;
[0051] Figure 11 for Figure 10 The diagram shows a timing diagram of one type of shift register.
[0052] Figure 12A A schematic diagram of the circuit structure of another shift register provided in an embodiment of this disclosure;
[0053] Figure 12B A schematic diagram of the circuit structure of another shift register provided in an embodiment of this disclosure;
[0054] Figure 13 This is a schematic diagram of the circuit structure of a gate driving circuit provided in an embodiment of the present disclosure. Detailed Implementation
[0055] To enable those skilled in the art to better understand the technical solution of the present invention, a shift register, gate driving circuit and display device provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0056] It should be noted that the transistor in this invention can be a thin-film transistor, a field-effect transistor, or other switching devices with the same characteristics. A transistor generally includes three terminals: a gate, a source, and a drain. The source and drain of a transistor are structurally symmetrical and can be interchanged as needed. In this invention, the control terminal refers to the gate of the transistor; one of the first and second terminals is the source, and the other is the drain.
[0057] Furthermore, based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is an N-type transistor, its on-state voltage is a high-level voltage and its off-state voltage is a low-level voltage. When a transistor is a P-type transistor, its on-state voltage is a low-level voltage and its off-state voltage is a high-level voltage.
[0058] Figure 1 A schematic diagram of the circuit structure of a shift register provided in an embodiment of this disclosure is shown below. Figure 1 As shown in the embodiment of this disclosure, the shift register in the gate driving circuit for light emission control is coupled to the corresponding row light emission control signal line in the display device to provide a corresponding light emission control signal to the coupled light emission control signal line. The shift register includes an input circuit 1, a first control circuit 2, a second control circuit 3, and an output circuit 4.
[0059] The input circuit 1 is coupled to the signal input terminal INPUT, the first clock signal terminal CK, and the third node N3. The input circuit 1 is configured to control the writing of the signal provided by the signal input terminal INPUT to the third node N3 in response to the signal provided by the first clock signal terminal CK.
[0060] The first control circuit 2 is coupled to a first power supply terminal, a preset control signal terminal CS, a second clock signal terminal CKB, and a first node N1, and is configured to control the writing of the voltage provided by the first power supply terminal to the first node N1 in response to the signal provided by the preset control signal terminal CS and the signal provided by the second clock signal terminal CKB.
[0061] The second control circuit 3 is coupled to the second power supply terminal, the signal input terminal INPUT, and the first node N1. The second control circuit 3 is configured to control the writing of the voltage provided by the second power supply terminal to the first node N1 in response to the signal provided by the signal input terminal INPUT.
[0062] Output circuit 4 is coupled to signal output terminal OUT, first power supply terminal, second power supply terminal, first node N1, and fourth node N4. Output circuit 4 is configured to write the voltage provided by the second power supply terminal to signal output terminal OUT in response to the control of the voltage at the first node N1, and to write the voltage provided by the first power supply terminal to signal output terminal OUT in response to the control of the voltage at the fourth node N4. Third node N3 is coupled to fourth node N4.
[0063] The shift register provided in this disclosure has the advantages of simple circuit structure and small space occupation, which is beneficial to the narrow bezel design of display devices.
[0064] Figure 2 A schematic diagram of another specific circuit structure of the shift register provided in this disclosure embodiment is shown below. Figure 2 As shown, in some embodiments, the shift register further includes: a noise reduction circuit 5 coupled to a second power supply terminal, a first node N1, and a third node N3, wherein the noise reduction circuit 5 is configured to write the voltage provided by the second power supply terminal to the third node N3 in response to control of the voltage at the first node N1.
[0065] In this embodiment of the disclosure, the noise reduction circuit 5 can be used to perform noise reduction processing on the third node N3 during the operation of the shift register.
[0066] Figure 3 A schematic diagram of another specific circuit structure of the shift register provided in the embodiments of this disclosure is shown below. Figure 3 As shown, Figure 3 The shift register shown is based on Figure 2 This is a specific implementation of the shift register shown.
[0067] In some embodiments, the first control circuit 2 includes a first transistor T1 and a second transistor T2, the second control circuit 3 includes a third transistor T3, the input circuit 1 includes a fourth transistor T4, the noise reduction circuit 5 includes a fifth transistor T5, and the output circuit 4 includes a seventh transistor T7 and an eighth transistor T8.
[0068] Among them, the control electrode of the first transistor T1 is coupled to the preset control signal terminal CS, the first electrode of the first transistor T1 is coupled to the first power supply terminal, and the second electrode of the first transistor T1 is coupled to the first electrode of the second transistor T2.
[0069] The control electrode of the second transistor T2 is coupled to the second clock signal terminal CKB, and the second electrode of the second transistor T2 is coupled to the first node N1.
[0070] The control electrode of the third transistor T3 is coupled to the signal input terminal INPUT, the first electrode of the third transistor T3 is coupled to the second power supply terminal, and the second electrode of the third transistor T3 is coupled to the first node N1.
[0071] The control electrode of the fourth transistor T4 is coupled to the first clock signal terminal CK, the first electrode of the fourth transistor T4 is coupled to the signal input terminal INPUT, and the second electrode of the fourth transistor T4 is coupled to the third node N3.
[0072] The control electrode of the fifth transistor T5 is coupled to the first node N1, the first electrode of the fifth transistor T5 is coupled to the third node N3, and the second electrode of the fifth transistor T5 is coupled to the second power supply terminal.
[0073] The control electrode of the seventh transistor T7 is coupled to the fourth node N4, the first electrode of the seventh transistor T7 is coupled to the first power supply terminal, and the second electrode of the seventh transistor T7 is coupled to the signal output terminal OUT.
[0074] The control electrode of the eighth transistor T8 is coupled to the first node N1, the first electrode of the eighth transistor T8 is coupled to the signal output terminal OUT, and the second electrode of the eighth transistor T8 is coupled to the second power supply terminal.
[0075] In some embodiments, the preset control signal terminal CS is the signal input terminal INPUT. In this embodiment of the disclosure, the signal input terminal INPUT is used as the preset control signal terminal CS, so there is no need to configure a new control signal terminal, thereby effectively reducing the number of signal terminals configured in the shift register and helping to reduce the control difficulty of the shift register.
[0076] In some embodiments, the first transistor T1 is an N-type transistor, and all other transistors in the shift register except for the first transistor T1 are P-type transistors.
[0077] Currently, pixel driving circuits in display devices are increasingly moving towards Low Temperature Polycrystalline Oxide (LTPO) technology. This means the pixel driving circuit includes two types of transistors: low-temperature polycrystalline silicon (LTPS) transistors and metal-oxide (MOD) transistors. Since the GoA circuit is fabricated synchronously with the pixel driving circuit using the same processes, to adapt to the fabrication process of the LTPO pixel driving circuit, the transistors in the shift register are also designed to include both LTPS transistors and MOD transistors. In some embodiments, the N-type transistor is a MOD transistor, and the P-type transistor is a LTPS transistor. That is, the first transistor T1 is a MOD transistor, and all other transistors in the shift register except for the first transistor T1 are LTPS transistors.
[0078] The following will be discussed in conjunction with the accompanying drawings. Figure 2 The operation of the shift register shown is described in detail. For example, the first transistor T1 is an N-type transistor, while the second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, seventh transistor T7, and eighth transistor T8 are all P-type transistors. The first power supply terminal provides a low-level voltage VGL, and the second power supply terminal provides a high-level voltage VGH.
[0079] Figure 4 for Figure 3 The following is a timing diagram of a shift register, such as... Figure 3 As shown, the operation of this shift register includes the following stages:
[0080] In the first stage t1, the signal provided by the signal input terminal INPUT is at a low level, the signal provided by the first clock signal terminal CK is at a high level, and the signal provided by the second clock signal terminal CKB is at a low level.
[0081] Since the signal provided by the second clock signal terminal CKB is at a low level, the second transistor T2 is turned on.
[0082] Since the signal provided by the signal input terminal INPUT is in a low-level state, the first transistor T1 is turned off, the third transistor T3 is turned on, and the high-level voltage VGH provided by the second power supply terminal is written to the first node N1 through the third transistor T3. The voltage at the first node N1 is in a high-level state, and the fifth transistor T5 and the eighth transistor T8 are both turned off.
[0083] Since the signal provided by the first clock signal terminal CK is at a high level, the fourth transistor T4 is turned off. At this time, both the third node N3 and the fourth node N4 are in a floating state. The voltage at the third node N3 and the fourth node N4 maintains the low level state of the previous stage. At this time, the seventh transistor T7 remains in the conducting state. The low-level signal provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7. Therefore, the signal output terminal OUT outputs a low-level signal.
[0084] In the second stage t2, the signal provided by the signal input terminal INPUT is at a high level, the signal provided by the first clock signal terminal CK is at a low level, and the signal provided by the second clock signal terminal CKB is at a high level.
[0085] Since the signal provided by the second clock signal terminal CKB is at a high level, the second transistor T2 is turned off.
[0086] Since the signal provided by the signal input terminal INPUT is at a high level, the first transistor T1 is turned on, and the third transistor T3 is turned off. At this time, the first node N1 is in a floating state and maintains the high level state of the previous stage. At this time, the fifth transistor T5 and the eighth transistor T8 are both turned off.
[0087] Since the signal provided by the first clock signal terminal CK is at a low level, the fourth transistor T4 is turned on. The high-level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4, and the voltages at the third node N3 and the fourth node N4 are at a high level. At this time, the seventh transistor T7 is in the off state. The signal output terminal OUT is in a floating state, maintaining the low-level state of the previous stage, that is, the signal output terminal OUT outputs a low-level signal.
[0088] In the third stage t3, the signal provided by the signal input terminal INPUT is at a high level, the signal provided by the first clock signal terminal CK is at a high level, and the signal provided by the second clock signal terminal CKB is at a low level.
[0089] Since the signal provided by the second clock signal terminal CKB is at a low level, the second transistor T2 is turned on.
[0090] Since the signal provided by the signal input terminal INPUT is in a high-level state, the first transistor T1 is turned on and the third transistor T3 is turned off. At this time, the low-level voltage VGL provided by the first power supply terminal is written to the first node N1 through the first transistor T1 and the second transistor T2. The voltage at the first node N1 is in a low-level state, and the fifth transistor T5 and the eighth transistor T8 are both turned on.
[0091] Since the signal provided by the first clock signal terminal CK is at a high level, the fourth transistor T4 is turned off. However, since the fifth transistor T5 is in the on state, the high-level voltage VGH provided by the second power supply terminal is written to the third node N3 through the fifth transistor T5 to achieve noise reduction of the voltage at the third node N3. At this time, the seventh transistor T7 remains off.
[0092] Since the eighth transistor T8 is turned on, the high-level voltage VGH provided by the second power supply terminal can be written to the signal output terminal OUT through the eighth transistor T8, so the signal output terminal OUT outputs a high-level signal.
[0093] As can be seen from the foregoing, the noise reduction circuit 5 (fifth transistor T5) can reduce the voltage at the third node N3 in the third stage t3. The noise reduction circuit 5 (fifth transistor T5) does not provide the necessary circuit structure in the shift register of the present disclosure embodiment. Therefore, in some embodiments, the noise reduction circuit 5 can be removed according to actual needs (e.g., simplifying the circuit structure and reducing the size occupied by the shift register).
[0094] In the fourth stage t4, the signal provided by the signal input terminal INPUT is at a high level, the signal provided by the first clock signal terminal CK is at a low level, and the signal provided by the second clock signal terminal CKB is at a high level.
[0095] Since the signal provided by the second clock signal terminal CKB is at a high level, the second transistor T2 is turned off.
[0096] Since the signal provided by the signal input terminal INPUT is at a high level, the first transistor T1 is turned on and the third transistor T3 is turned off. At this time, the first node N1 is in a floating state and maintains the low level state of the previous stage, while the fifth transistor T5 and the eighth transistor T8 remain turned on.
[0097] Since the signal provided by the first clock signal terminal CK is at a low level, the fourth transistor T4 is turned on. The high-level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4, and the voltages at the third node N3 and the fourth node N4 are at a high level. At this time, the seventh transistor T7 is in the off state. The signal output terminal OUT is in a floating state, maintaining the high-level state of the previous stage, that is, the signal output terminal OUT outputs a high-level signal.
[0098] It should be noted that, depending on the pulse width design of the input signal, there may be multiple third stages t3 and multiple fourth stages t4 within one cycle, with the third stage t3 and the fourth stage t4 alternating.
[0099] In the fifth stage t5, the signal provided by the signal input terminal INPUT is at a low level, the signal provided by the first clock signal terminal CK is at a low level, and the signal provided by the second clock signal terminal CKB is at a high level.
[0100] Since the signal provided by the second clock signal terminal CKB is at a high level, the second transistor T2 is turned off.
[0101] Since the signal provided by the signal input terminal INPUT is in a low-level state, the first transistor T1 is turned off and the third transistor T3 is turned on. At this time, the high-level voltage VGH provided by the second power supply terminal is written to the first node N1 through the third transistor T3. The voltage at the first node N1 is in a high-level state, and the fifth transistor T5 and the eighth transistor T8 are both turned off.
[0102] Since the signal provided by the first clock signal terminal CK is at a low level, the fourth transistor T4 is turned on. The low-level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4, and the voltages at the third node N3 and the fourth node N4 are at a low level. At this time, the seventh transistor T7 is turned on.
[0103] Because the seventh transistor T7 is turned on, the low-level voltage VGL provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so the signal output terminal OUT outputs a low-level signal. It should be noted that during the fifth stage, the voltages of the third node N3 and the fourth node N4 will slowly decrease, and the seventh transistor T7 will slowly switch from the off state to the on state. Therefore, the signal output by the signal output terminal OUT will slowly switch from a high-level state to a low-level state. In other words, during the fifth stage, the seventh transistor T7 actually outputs a high-level signal first, and then a low-level signal.
[0104] In the sixth stage t6, the signal provided by the signal input terminal INPUT is at a low level, the signal provided by the first clock signal terminal CK is at a high level, and the signal provided by the second clock signal terminal CKB is at a low level.
[0105] Since the signal provided by the second clock signal terminal CKB is at a low level, the second transistor T2 is turned on.
[0106] Since the signal provided by the signal input terminal INPUT is in a low-level state, the first transistor T1 is turned off and the third transistor T3 is turned on. At this time, the high-level voltage VGH provided by the second power supply terminal is written to the first node N1, and the voltage at the first node N1 is in a high-level state. The fifth transistor T5 and the eighth transistor T8 are both turned off.
[0107] Since the signal provided by the first clock signal terminal CK is at a high level, the fourth transistor T4 is turned off. At this time, the third node N3 and the fourth node N4 are in a floating state and maintain the low level of the previous stage. The seventh transistor T7 remains on.
[0108] Because the seventh transistor T7 is turned on, the low-level voltage VGL provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so the signal output terminal OUT outputs a low-level signal.
[0109] In the seventh stage t7, the signal provided by the signal input terminal INPUT is at a low level, the signal provided by the first clock signal terminal CK is at a low level, and the signal provided by the second clock signal terminal CKB is at a high level.
[0110] Since the signal provided by the second clock signal terminal CKB is at a high level, the second transistor T2 is turned off.
[0111] Since the signal provided by the signal input terminal INPUT is in a low-level state, the first transistor T1 is turned off and the third transistor T3 is turned on. At this time, the high-level voltage VGH provided by the second power supply terminal is written to the first node N1 through the third transistor T3. The voltage at the first node N1 is in a high-level state, and the fifth transistor T5 and the eighth transistor T8 are both turned off.
[0112] Since the signal provided by the first clock signal terminal CK is at a low level, the fourth transistor T4 is turned on. The low-level signal provided by the signal input terminal INPUT is written to the third node N3 through the fourth transistor T4 to perform noise reduction processing on the third node N3. The voltages at the third node N3 and the fourth node N4 are at a low level. At this time, the seventh transistor T7 is turned on.
[0113] Because the seventh transistor T7 is turned on, the low-level voltage VGL provided by the first power supply terminal is written to the signal output terminal OUT through the seventh transistor T7, so the signal output terminal OUT outputs a low-level signal.
[0114] It should be noted that, based on the design of one frame duration, there will be multiple sixth stages t6 and multiple seventh stages t7 within one cycle. The sixth stage t6 and the seventh stage t7 alternate until the first stage of the next cycle begins.
[0115] Based on the above, it can be seen that Figure 4 The shift register shown includes only 7 transistors: transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T7, and transistor T8, compared to the traditional 12T2C circuit (which includes 12 transistors and 2 capacitors). Figure 4The shift register shown has a simpler circuit structure, occupies a smaller size, and is more conducive to narrow bezel design.
[0116] Figure 5 This is a schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure, such as... Figure 5 As shown, unlike the previous embodiment where the preset control signal terminal CS was the signal input terminal INPUT, in this embodiment, the preset control signal terminal CS is the third node N3. Specifically, Figure 5 The control electrode of the first transistor T1 is coupled to the third node N3.
[0117] Figure 5 The timing diagram of the shift register shown can also be used. Figure 4 As shown, the specific working process can be found in the previous section. Figure 4 The relevant descriptions will not be repeated here. It should be noted that, based on... Figure 4 As shown, the signal waveform at the third node N3 is similar to the signal waveform at the signal input terminal INPUT. Therefore, when the control electrode of the first transistor T1 is connected to the third node N3, the working state of the first transistor T1 in each stage is the same as the working state of the first transistor T1 in each stage when the control electrode is connected to the signal input terminal INPUT.
[0118] Figure 6 This is a schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure. Figure 7 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure is shown below. Figure 6 and Figure 7 As shown, unlike the previous embodiments, Figure 6 and Figure 7 In the illustrated embodiment, the control electrode of the first transistor T1 is connected to the preset control signal terminal CS ( Figure 6 The preset control signal terminal CS is the signal input terminal INPUT. Figure 7 The preset control signal terminal CS is coupled to the third node N3. The first terminal of the first transistor T1 is coupled to the second terminal of the second transistor T2. The second terminal of the first transistor T1 is coupled to the first node N1. The control terminal of the second transistor T2 is coupled to the second clock signal terminal CKB. The first terminal of the second transistor T2 is coupled to the first power supply terminal.
[0119] Figure 6 and Figure 7 The timing diagram of the shift register shown can be found in [reference needed]. Figure 4 As shown, the specific details will not be repeated here.
[0120] exist Figure 3 , Figure 5 , Figure 6 , Figure 7 In the illustrated embodiment, the third node N3 and the fourth node N4 are directly connected. During the first and fifth stages, the signal input terminal INPUT writes a low-level signal to the third node N3 and the fourth node N4. The seventh transistor T7 is controlled by the low-level voltage at the fourth node N4 to output. Generally, to ensure that the seventh transistor T7 can be fully turned on in the first and fifth stages (the gate-source voltage of the seventh transistor T7 needs to be less than or equal to Vth_T7, where Vth_T7 is the threshold voltage of the seventh transistor T7, and Vth_T7≤0V), the voltage at the fourth node N4 needs to be less than or equal to VGL (VGL is generally a negative voltage, such as -9), so that the signal output terminal OUT can output a low-level voltage VGL. This also requires that the low-level voltage provided by the signal input terminal INPUT is less than or equal to VGL.
[0121] Generally, in a gate drive circuit, the signal input terminal INPUT of the first-stage shift register is coupled to the frame start signal terminal. For any shift register other than the first stage, the signal input terminal INPUT is coupled to the signal output terminal OUT of the previous stage shift register. That is, the low-level voltage at the signal output terminal OUT of the current stage shift register will serve as the low-level voltage input to the signal input terminal INPUT of the next stage shift register. Therefore, it is necessary to ensure that the low-level voltage provided by the frame start signal terminal is VGL to guarantee that the voltage at node N4 is VGL when each shift register operates in the first, fifth, and seventh stages, respectively. However, in practical applications, considering factors such as IR drop, it was found that when each shift register operates in the first, fifth, and seventh stages, the actual applied voltage VN4 > VGL. At this time, the voltage output by the signal output terminal OUT is VN4 - Vth_T7 (the seventh transistor T7 is turned on first, and when the voltage at the signal output terminal OUT discharges to VN4 - Vth_T7, the seventh transistor T7 is turned off). Since Vth_T7 ≤ 0, VN4 - Vth_T7 > VGL, meaning that the signal output terminal OUT cannot fully output VGL. Once VN4 is too large, the low-level voltage output by the signal output terminal OUT will also be too large, which may easily lead to the low-level voltage output by the signal output terminal OUT failing to effectively control the light-emitting control transistor in the pixel driving circuit.
[0122] To effectively improve the above-mentioned technical problems, this disclosure provides a new shift register. Figure 8 This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present disclosure. Figure 9 for Figure 8 The following is a timing diagram of a shift register, such as... Figure 8 and Figure 9 As shown, unlike the shift registers provided in the previous embodiments, Figure 8 The shift register unit shown includes not only the circuit structure in the previous shift register, but also a first capacitor C1; wherein, the first end of the first capacitor C1 is coupled to the second clock signal terminal CKB, and the second end of the first capacitor C1 is coupled to the fourth node N4.
[0123] Figure 8 The operation of the shift register shown also includes the first stage t1 to the seventh stage t7 as described above. In the first stage t1 and the fifth stage t5, since the third node N3 and the fourth node N4 are in a floating state, when the signal provided by the second clock signal terminal CKB switches from a high level to a low level, the third node N3 and the fourth node N4 will also be pulled down under the bootstrap effect of the first capacitor C1.
[0124] For example, assuming the voltage at the fourth node N4 is VN4 after the fifth stage t5 ends and before the sixth stage t6 begins, the voltage output by the signal output terminal OUT is VN4-Vth_T7. After the sixth stage begins, when the voltage provided by the second clock signal terminal CKB switches from a high level voltage Vgh_C to a low level voltage Vgl_C, the voltages at the third node N3 and the fourth node N4 will be pulled down to VN4-(Vgh_C-Vgl_C) by the first capacitor C1. By pre-designing the value of Vgh_C-Vgl_C so that VN4-(Vgh_C-Vgl_C) is less than VGL, the seventh transistor T7 will be in a fully turned-on state in the sixth stage, at which time the signal output terminal OUT can fully output a low level voltage VGL.
[0125] It should be noted that during the subsequent seventh stage t7, although the voltage at the fourth node N4 will also be pulled up to VN4 by the first capacitor C1, the seventh transistor T7 will be in the off state during the seventh stage t7 because the gate-source voltage of the seventh transistor T7 is greater than Vth_T7. The signal output terminal OUT will be in the floating state, maintaining the output low-level voltage VGL.
[0126] Similarly, at the first stage t1, the voltage at the fourth node N4 will be pulled down to VN4-(Vgh_C-Vgl_C) by the first capacitor C1, and the signal output terminal OUT will output a low-level voltage VGL.
[0127] As can be seen from the above, by setting the first capacitor C1, the signal output terminal OUT can stably output a low-level voltage VGL in the first, sixth and seventh stages.
[0128] Figure 10 This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present disclosure. Figure 11 for Figure 10 The following is a timing diagram of a shift register, such as... Figure 10 and Figure 11 As shown, in some embodiments, the shift register includes not only Figure 8 The first capacitor C1 in the circuit also includes a sixth transistor T6. The sixth transistor T6 is located between the third node N3 and the fourth node N4. The third node N3 is coupled to the fourth node N4 through the sixth transistor T6. The control terminal of the sixth transistor T6 is coupled to the first power supply terminal. The first terminal of the sixth transistor T6 is coupled to the third node N3, and the second terminal of the sixth transistor T6 is coupled to the fourth node N4.
[0129] pass Figure 9 As can be seen from the timing diagram, due to Figure 8 The third node N3 and the fourth node N4 are directly connected, so the signals applied to them are always consistent. During the first stage t1 and the sixth stage t6, the voltage at the third node N3 is in an extremely low state (extremely low negative voltage). At this time, the fourth transistor T4 and the fifth transistor T5 will be in a high voltage state (there is a large voltage difference between the first and second terminals of the transistors), which will affect the lifespan of the fourth transistor T4 and the fifth transistor T5.
[0130] To effectively improve the above-mentioned technical problems, in Figure 11 In the illustrated embodiment, a sixth transistor T6 is disposed between the third node N3 and the fourth node N4. The control electrode of the sixth transistor T6 is coupled to the first power supply terminal to receive a low-level voltage VGL. See also Figure 11 As shown, during the first stage t1 and the sixth stage t6, when the voltage at the fourth node N4 is pulled down to VN4 - (Vgh_C - Vgl_C) by the first capacitor C1, the gate-source voltage of the sixth transistor T6 will exceed its own threshold voltage. At this time, the sixth transistor T6 switches to the off state. Therefore, the extremely low negative voltage at the fourth node N4 cannot be written to the third node N3. At this time, the voltage at the third node N3 will maintain the state of the fifth stage (at this time, the third node N3 is in the floating state). Thus, it can effectively prevent the fourth transistor T4 and the fifth transistor T5 from being in a high-voltage state, thereby ensuring the service life of the fourth transistor T4 and the fifth transistor T5.
[0131] Figure 12A This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present disclosure. Figure 12B A schematic diagram of another shift register circuit structure provided in this disclosure embodiment is shown below. Figure 12A and Figure 12B As shown, unlike the previous embodiments, Figure 12A and Figure 12BThe shift register shown also includes a second capacitor C2. The first end of the second capacitor C2 is coupled to the first node N1, and the second end of the second capacitor C2 is coupled to either the first power supply terminal (not shown in the corresponding figure) or the second power supply terminal (…). Figure 12A and Figure 12B (As shown in the diagram) coupling.
[0132] In this embodiment of the disclosure, the first node N1 will be in a floating state during the second and fourth stages. In order to maintain the voltage stability of the first node N1 during the second and fourth stages, a second capacitor C2 is provided at the first node N1 to play a voltage stabilizing role.
[0133] Figure 12A and Figure 12B The shift register shown is an 8T2C circuit (including 8 transistors and 2 capacitors), compared to the traditional 12T2C circuit. Figure 12A and Figure 12B The shift register shown has a simpler circuit structure, occupies a smaller size, and is more conducive to narrow bezel design.
[0134] Based on the same inventive concept, this disclosure also provides a gate driving circuit. Figure 13 This is a schematic diagram of the circuit structure of a gate driving circuit provided in an embodiment of the present disclosure, as shown below. Figure 13 As shown, the gate drive circuit DC includes: multiple cascaded shift registers SR1 to SRm, and the shift registers SR1 to SRm are the shift registers provided in the previous embodiment.
[0135] Specifically, the signal input terminal INPUT of the first-stage shift register SR1 is coupled to the frame start signal terminal STV; the signal input terminal INPUT of any other shift register SR2 to SRm is coupled to the signal output terminal OUT of the previous-stage shift register. The signal output terminal OUT of each shift register SR1 to SRm is also coupled to the light emission control signal lines EM1 to EMm configured for the corresponding pixel units in the display device.
[0136] In some embodiments, the gate drive circuit DC is further configured with two clock signal lines CLK and CLKB: a first clock signal line CLK and a second clock signal line CLKB; wherein, the first clock signal terminal CK of the shift register located at odd-numbered levels is coupled to the first clock signal line CLK, and the second clock signal terminal CKB of the shift register located at odd-numbered levels is coupled to the second clock signal line CLKB; the first clock signal terminal CK of the shift register located at even-numbered levels is coupled to the second clock signal line CLKB, and the second clock signal terminal CKB of the shift register located at odd-numbered levels is coupled to the first clock signal line CLK.
[0137] This disclosure also provides a display device, which includes a display substrate and a counter substrate disposed opposite to the display substrate. The display substrate is the display substrate provided in the previous embodiments. For the description of the display substrate in this embodiment, please refer to the content in the previous embodiments, and it will not be repeated here.
[0138] It should be noted that the display device provided in this embodiment can be any product or component with display function, such as an OLED panel, OLED TV, QLED panel, QLED TV, mobile phone, tablet computer, laptop computer, digital photo frame, navigator, etc.; the display device may also include other components, such as data driving circuit, timing controller, etc., which are not limited in this disclosure embodiment.
[0139] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.
Claims
1. A shift register, wherein, include: An input circuit, coupled to a signal input terminal, a first clock signal terminal, and a third node, is configured to control the writing of a signal provided by the signal input terminal to the third node in response to a signal provided by the first clock signal terminal. A first control circuit, coupled to a first power supply terminal, a preset control signal terminal, a second clock signal terminal, and a first node, is configured to control the writing of the voltage provided by the first power supply terminal to the first node in response to a signal provided by the preset control signal terminal and a signal provided by the second clock signal terminal; wherein the preset control signal terminal is the third node or the signal input terminal; A second control circuit, coupled to a second power supply terminal, the signal input terminal, and the first node, is configured to control the writing of the voltage provided by the second power supply terminal to the first node in response to a signal provided by the signal input terminal. An output circuit, coupled to a signal output terminal, a first power supply terminal, a second power supply terminal, a first node, and a fourth node, is configured to write the voltage provided by the second power supply terminal to the signal output terminal in response to voltage control at the first node, and to write the voltage provided by the first power supply terminal to the signal output terminal in response to voltage control at the fourth node, wherein the third node is coupled to the fourth node. A sixth transistor is located between the third node and the fourth node, and the third node is coupled to the fourth node through the sixth transistor; the control terminal of the sixth transistor is coupled to a first power supply terminal, the first terminal of the sixth transistor is coupled to the third node, and the second terminal of the sixth transistor is coupled to the fourth node.
2. The shift register according to claim 1, wherein, The first control circuit includes: a first transistor and a second transistor; The control electrode of the first transistor is coupled to the preset control signal terminal, the first electrode of the first transistor is coupled to the first power supply terminal, and the second electrode of the first transistor is coupled to the first electrode of the second transistor. The control electrode of the second transistor is coupled to the second clock signal terminal, and the second electrode of the second transistor is coupled to the first node.
3. The shift register according to claim 1, wherein, The first control circuit includes: a first transistor and a second transistor; The control electrode of the first transistor is coupled to the preset control signal terminal, the first electrode of the first transistor is coupled to the second electrode of the second transistor, and the second electrode of the first transistor is coupled to the first node; The control terminal of the second transistor is coupled to the second clock signal terminal, and the first terminal of the second transistor is coupled to the first power supply terminal.
4. The shift register according to claim 2 or 3, wherein, The first transistor is an N-type transistor, and all other transistors in the shift register except the first transistor are P-type transistors.
5. The shift register according to claim 4, wherein, The first transistor is a metal-oxide-semiconductor transistor, and all other transistors in the shift register, except for the first transistor, are low-temperature polysilicon transistors.
6. The shift register according to claim 1, wherein, The second control circuit includes: a third transistor; The control electrode of the third transistor is coupled to the signal input terminal, the first electrode of the third transistor is coupled to the second power supply terminal, and the second electrode of the third transistor is coupled to the first node.
7. The shift register according to claim 1, wherein, The input circuit includes: a fourth transistor; The control electrode of the fourth transistor is coupled to the first clock signal terminal, the first electrode of the fourth transistor is coupled to the signal input terminal, and the second electrode of the fourth transistor is coupled to the third node.
8. The shift register according to claim 1, wherein, The output circuit includes a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is coupled to the fourth node, the first electrode of the seventh transistor is coupled to the first power supply terminal, and the second electrode of the seventh transistor is coupled to the signal output terminal. The control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the signal output terminal, and the second electrode of the eighth transistor is coupled to the second power supply terminal.
9. The shift register according to claim 1, wherein, The shift register further includes a noise reduction circuit coupled to the second power supply terminal, the first node, and the third node, configured to write the voltage provided by the second power supply terminal to the third node in response to voltage control at the first node.
10. The shift register according to claim 9, wherein, The noise reduction circuit includes: a fifth transistor; The control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the third node, and the second electrode of the fifth transistor is coupled to the second power supply terminal.
11. The shift register according to claim 1, characterized in that, Also includes: Second capacitor; The first end of the second capacitor is coupled to the first node, and the second end of the second capacitor is coupled to either the first power supply terminal or the second power supply terminal.
12. A gate driving circuit, wherein, include: A series of cascaded shift registers, wherein the shift registers are any of the shift registers described in claims 1 to 11 above; The signal input terminal of the shift register located in the first stage is coupled to the frame start signal terminal; The signal input terminal of any shift register other than the first stage is coupled to the signal output terminal of the shift register of the previous stage.
13. A display device, wherein, include: The gate drive circuit as described in claim 12 above.