A 3D memory and its fabrication method, and an electronic device.

Abstract

A 3D memory and its fabrication method are disclosed. The fabrication method of the 3D memory includes: forming a stacked structure comprising alternating sacrificial layers and conductive layers; forming vias penetrating the stacked structure, the vias including a plurality of first sub-vias located in the sacrificial layers and a plurality of second sub-vias located in the conductive layers, wherein the orthographic projection of the first sub-vias falls within the orthographic projection of the second sub-vias on a plane parallel to the substrate; forming a semiconductor layer, a gate insulating layer, and a gate electrode within the vias, wherein the gate electrode of the transistors in different layers is part of the word line; etching away the sacrificial layers to expose the semiconductor layers located within the first sub-vias; and etching away the semiconductor layers located within the first sub-vias. The solution provided in this embodiment, by setting sacrificial layers between layers, achieves etching of the semiconductor layers between layers, reducing parasitic capacitance and improving device performance.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, semiconductor technology, and particularly to a 3D memory and its fabrication method, and an electronic device. Background Technology

[0002] As Dynamic Random Access Memory (DRAM) technology enters the 10-nanometer (nm) node, the planar 1T1C structure has reached its limit. To achieve higher storage capacitance, lower leakage current, and higher integration density, DRAM memory is gradually evolving towards a three-dimensional (3D) structure. However, the development of 3D structures encounters various problems. With the increase in the number of stacked layers and the larger and denser the array, the presence of parasitic metal-oxide-semiconductor (MOS) capacitances between different layers has a significant impact on the retention force of the stored charge and the overall stability of the device. Therefore, in the research and development of 3D DRAM devices, while overcoming complex process structures, it is necessary to fully consider the optimization or even elimination of some parasitic capacitances. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a 3D memory and its fabrication method, as well as an electronic device, which can reduce parasitic capacitance and improve device performance.

[0005] This disclosure provides a method for fabricating a 3D memory. The 3D memory includes multiple layers of memory cells stacked along a direction perpendicular to a substrate, word lines, and each memory cell including a transistor and a capacitor. The transistor includes a first electrode, a second electrode, a gate electrode extending along a direction perpendicular to the substrate, and a semiconductor layer surrounding and insulated from the gate electrode. The capacitor includes a first plate and a second plate. The method for fabricating the 3D memory includes:

[0006] A substrate is provided, and a sacrificial layer thin film and a conductive thin film are sequentially and alternately deposited on the substrate to form a stacked structure. The stacked structure includes an alternating stack of sacrificial and conductive layers, and the conductive layer includes a preset electrode pattern.

[0007] A via is formed through the stacked structure in a direction perpendicular to the substrate, the sidewalls of the via exposing each of the conductive layers, and the via causes the preset electrode pattern to form at least one pair of first electrodes and second electrodes that are separated from each other; the via includes a plurality of first sub-vias respectively located in the sacrificial layer and a plurality of second sub-vias respectively located in the conductive layer, and on a plane parallel to the substrate, the orthographic projection of the first sub-via falls into the orthographic projection of the second sub-via;

[0008] A semiconductor thin film and a gate insulating thin film are sequentially deposited on the sidewall of the via to form a multilayer semiconductor layer and a gate insulating layer of the transistor. The semiconductor layer is in contact with the first electrode and the second electrode. The channel between the first electrode and the second electrode in the same transistor is a horizontal channel. A gate electrode thin film is deposited in the via to fill the via to form a multilayer gate electrode of the transistor. The gate electrodes of the transistors in different layers are part of the word line.

[0009] The sacrificial layer is etched away to expose the semiconductor layer located within the first sub-via.

[0010] In one exemplary embodiment, the pattern forming a stacked structure includes:

[0011] The sacrificial layer film and the conductive film are etched using a dry etching method to remove the sacrificial layer film and the conductive film located in a predetermined isolation area, so as to form the stack of the alternately arranged sacrificial layer and conductive layer;

[0012] A first insulating film is deposited in the predetermined isolation area to form a first insulating layer, wherein the first insulating film is made of a different material than the sacrificial layer film.

[0013] In one exemplary embodiment, after the stacked structure is patterned and formed, and before forming a via penetrating the stacked structure in a direction perpendicular to the substrate, the method further includes:

[0014] Etching removes the first insulating layer and sacrificial layer located in the preset capacitor region to expose one end of the first electrode of each transistor layer;

[0015] A second insulating film and a conductor material are sequentially deposited in the preset capacitor region to form a second insulating layer and a second electrode of the capacitor. The second insulating layer covers the area where the first electrode is exposed, and the second electrode is isolated from the first electrode through the second insulating layer.

[0016] In one exemplary embodiment, the via formed through the stacked structure in a direction perpendicular to the substrate includes:

[0017] The stacked structure is etched to form an initial via through the stacked structure in a direction perpendicular to the substrate. The initial via includes a first sub-via and a second initial sub-via located in the conductive layer. The conductive layer is etched in a direction away from the initial via to enlarge the second initial sub-via to form the second sub-via.

[0018] In one exemplary embodiment, the sacrificial layer film comprises polycrystalline silicon.

[0019] In one exemplary embodiment, the first insulating film comprises silicon nitride.

[0020] In one exemplary embodiment, after etching away the semiconductor layer located within the first sub-hole, the method further includes etching away at least a portion of the gate insulating layer located within the first sub-hole.

[0021] In one exemplary embodiment, the conductive layer further includes a bit line connected to the second electrode.

[0022] This disclosure provides a 3D memory, which is fabricated using the fabrication method of the 3D memory described in any of the above embodiments.

[0023] This disclosure provides an electronic device including the 3D memory described above.

[0024] This disclosure includes a 3D memory and its fabrication method, and an electronic device. The 3D memory includes multiple layers of memory cells stacked in a direction perpendicular to a substrate, word lines, and each memory cell including a transistor and a capacitor. The transistor includes a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding and insulated from the gate electrode. The capacitor includes a first plate and a second plate. The fabrication method of the 3D memory includes: providing a substrate; sequentially and alternately depositing a sacrificial layer thin film and a conductive thin film on the substrate to form a stacked structure, the stacked structure including an alternating stack of sacrificial and conductive layers, the conductive layer including a predetermined electrode pattern; forming a via penetrating the stacked structure in a direction perpendicular to the substrate, the sidewalls of the via exposing each conductive layer, and the via causing the predetermined electrode pattern to be formed to... The via includes a pair of separate first and second electrodes; the via comprises multiple first sub-vias located on the sacrificial layer and multiple second sub-vias located on the conductive layer, wherein the orthographic projection of the first sub-via falls within the orthographic projection of the second sub-via on a plane parallel to the substrate; a semiconductor thin film and a gate insulating thin film are sequentially deposited on the sidewalls of the via to form a multilayer semiconductor layer and a gate insulating layer of the transistor, wherein the semiconductor layer is in contact with the first and second electrodes, and the channel between the first and second electrodes in the same transistor is a horizontal channel; a gate electrode thin film is deposited to fill the via to form a multilayer gate electrode of the transistor, wherein the gate electrodes of the transistors in different layers are part of the word line; the sacrificial layer is etched away to expose the semiconductor layer located in the first sub-via, and the semiconductor layer located in the first sub-via is etched away. The solution provided in this embodiment reduces the parasitic capacitance between transistors in different layers and improves device performance by setting a sacrificial layer between conductive layers and exposing the semiconductor layer between conductive layers by etching the sacrificial layer, thereby reducing the parasitic capacitance between transistors in different layers.

[0025] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0027] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions.

[0028] Figure 1AA schematic cross-sectional view of a 3D memory provided in an exemplary embodiment, along a direction parallel to the substrate;

[0029] Figure 1B A schematic cross-sectional view of a 3D memory along the aa' direction, provided as an exemplary embodiment;

[0030] Figure 2 A cross-sectional schematic diagram of the stacked structure provided as an exemplary embodiment;

[0031] Figure 3A A cross-sectional view along the direction parallel to the substrate after forming a conductive layer pattern, provided for an exemplary embodiment;

[0032] Figure 3B A cross-sectional view along the bb' direction after the formation of a conductive layer pattern, provided as an exemplary embodiment;

[0033] Figure 4A A cross-sectional view along the direction parallel to the substrate after opening a preset capacitor region, as provided in an exemplary embodiment;

[0034] Figure 4B A cross-sectional view along the aa' direction after opening a preset capacitor region, provided as an exemplary embodiment;

[0035] Figure 5A A cross-sectional view along the direction parallel to the substrate after the formation of the second electrode plate, provided for an exemplary embodiment;

[0036] Figure 5B A cross-sectional view along the aa' direction after the formation of the second electrode plate, provided as an exemplary embodiment;

[0037] Figure 5C A cross-sectional view along the bb' direction after the formation of the second electrode plate, provided as an exemplary embodiment;

[0038] Figure 6A A cross-sectional view along the direction parallel to the substrate after forming a via is provided for an exemplary embodiment;

[0039] Figure 6B A cross-sectional view along the aa' direction after the via is formed, provided as an exemplary embodiment;

[0040] Figure 6C A cross-sectional view along the bb' direction after the via is formed, provided for an exemplary embodiment;

[0041] Figure 7A A cross-sectional view along the direction parallel to the substrate after enlarging the via, provided for an exemplary embodiment;

[0042] Figure 7B A cross-sectional view along the aa' direction after enlarging the via, provided for an exemplary embodiment;

[0043] Figure 7C A cross-sectional view along the bb' direction after enlarging the via, provided for an exemplary embodiment;

[0044] Figure 8A A cross-sectional view along the direction parallel to the substrate after the formation of the gate electrode, provided for an exemplary embodiment;

[0045] Figure 8B A cross-sectional view along the aa' direction after the formation of the gate electrode, provided for an exemplary embodiment;

[0046] Figure 8C A cross-sectional view along the bb' direction after the formation of the gate electrode, provided for an exemplary embodiment;

[0047] Figure 9A A cross-sectional view along the direction parallel to the substrate after removal of the sacrificial layer, provided as an exemplary embodiment;

[0048] Figure 9B A cross-sectional view along the aa' direction after removing the sacrificial layer, provided as an exemplary embodiment;

[0049] Figure 9C A cross-sectional view along the bb' direction after removing the sacrificial layer, provided as an exemplary embodiment;

[0050] Figure 10A A cross-sectional view along the direction parallel to the substrate after etching a semiconductor layer, provided as an exemplary embodiment;

[0051] Figure 10B A cross-sectional view along the aa' direction after etching a semiconductor layer, provided as an exemplary embodiment;

[0052] Figure 10C A cross-sectional view along the bb' direction after etching the semiconductor layer, provided as an exemplary embodiment;

[0053] Figure 11A A cross-sectional view along the direction parallel to the substrate after the formation of the third insulating layer, provided for an exemplary embodiment;

[0054] Figure 11B A cross-sectional view along the aa' direction after the formation of the third insulating layer, provided as an exemplary embodiment;

[0055] Figure 11C A cross-sectional view along the bb' direction after the formation of the third insulating layer, provided as an exemplary embodiment;

[0056] Figure 12 A flowchart of a 3D memory fabrication method provided as an exemplary embodiment. Detailed Implementation

[0057] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0058] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0059] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0060] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0061] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0062] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0063] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0064] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0065] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0066] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0067] The statement in this disclosure that "the orthographic projection of B lies within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A.

[0068] In this embodiment of the disclosure, the parasitic capacitance of the parasitic MOS can be reduced or eliminated by etching away the semiconductor layers between the layers.

[0069] Figure 1A A schematic cross-sectional view of a 3D memory provided in an exemplary embodiment, along a direction parallel to the substrate. Figure 1B A schematic cross-sectional view of a 3D memory along the aa' direction, provided for an exemplary embodiment. Figure 1A and Figure 1B As shown, the 3D memory provided in this embodiment may include: multiple layers of memory cells stacked along a direction perpendicular to the substrate 1, and word lines 40, wherein the word lines 40 extend along a direction perpendicular to the substrate 1 and penetrate the memory cells of different layers;

[0070] The memory cell may include a transistor and a capacitor. The transistor may include a first electrode 51, a second electrode 52, a gate electrode 25 extending in a direction perpendicular to the substrate, and a semiconductor layer 23 surrounding and insulated from the gate electrode 25. The channel between the first electrode 51 and the second electrode 52 may be a horizontal channel. The semiconductor layers 23 of the transistors of different layers of the memory cell are spaced apart in a direction perpendicular to the substrate. The capacitor includes a first electrode 41 and a second electrode 42. The first electrode 41 is connected to the first electrode 51, and the gate electrode 25 is connected to the word line 40.

[0071] The 3D memory provided in this embodiment has semiconductor layers of transistors in different layers spaced apart, which can reduce or eliminate parasitic MOS capacitance between layers and improve device stability.

[0072] A horizontal channel is defined as a channel in which the carrier transport direction lies in a plane parallel to the substrate, but this direction is not limited to a single direction. In practical applications, the carrier transport direction generally extends in one direction, but locally it depends on the shape of the semiconductor layer. In other words, a horizontal channel does not necessarily mean that it must extend in one direction within a horizontal plane; it may extend in different directions. For example, when the semiconductor layer is ring-shaped, the source and drain contact regions on the ring-shaped semiconductor layer are part of the ring. In this case, the carriers generally extend in one direction from the source contact region to the drain contact region, but locally it may not be in a single direction. Of course, the carrier transport direction lying in a plane parallel to the substrate is a macroscopic concept and is not limited to absolute parallelism to the substrate. This application protects the channel between the first and second electrodes as a channel that is not perpendicular to the substrate.

[0073] In an exemplary embodiment, the first electrode plate 41 may be all or part of the first electrode 51.

[0074] In one exemplary embodiment, the transistor may further include a gate insulating layer 24 surrounding the gate electrode 25.

[0075] In an exemplary embodiment, the semiconductor layer 23 may be a fully encircling type, completely surrounding the sidewalls of the gate electrode 25; that is, the cross-section of the semiconductor layer 23 along the direction parallel to the substrate is a closed loop. Exemplarily, the semiconductor layer 23 is annular, and the annular shape conforms to the outer contour shape of the cross-section of the gate electrode 25. Exemplarily, the cross-section of the gate electrode 25 may be, for example, circular, elliptical, or square.

[0076] In an exemplary embodiment, the first electrode 51 and the second electrode 52 may be located in the same conductive film layer along a direction perpendicular to the substrate. This can be understood as the first electrode 51 and the second electrode 52 being located in the same metal film layer, patterned from a conductive film layer that is approximately parallel to the upper surface of the substrate.

[0077] In one exemplary embodiment, the gate insulating layer 24 is exposed between the spaced semiconductor layers 23.

[0078] In one exemplary embodiment, the gate electrode 25 of a transistor in a different layer is part of the word line 40.

[0079] In one exemplary embodiment, such as Figure 1A As shown, the memory cells in the same layer form an array distributed along the first direction X and the second direction Y respectively. Each layer of memory cells also includes a bit line 30, which is connected to the second electrode 52 of the transistor in the same column of the same layer. Figure 1A The illustration shows that each layer includes three rows and two columns of storage units, but the embodiments of this disclosure are not limited to this. Each layer may include storage units with other numbers of rows and columns, for example, it may include only one storage unit.

[0080] In one exemplary embodiment, the second electrode 52 of the transistors in two adjacent columns of memory cells is connected to the same bit line 30.

[0081] In one exemplary embodiment, the second electrode 52 of the transistor may be a part of the bit line 30 to which the second electrode 52 is connected.

[0082] In one exemplary embodiment, the bit line 30 may extend along the second direction Y.

[0083] In one exemplary embodiment, the first electrode 51 may extend along a first direction X.

[0084] In one exemplary embodiment, the second plates 42 of the capacitors in the same column of different layers can be connected as a single structure. For example... Figure 1A and Figure 1B As shown, the second plates 42 of the capacitors in the first column of different layers are connected as a single unit. Similarly, the second plates 42 of the capacitors in the second column of different layers are connected as a single unit, meaning that capacitors in the same column of different layers share the same second plate 42.

[0085] In one exemplary embodiment, the capacitor may further include a second insulating layer 13 disposed between the first electrode 41 and the second electrode 42. The second insulating layer 13 serves as a dielectric layer between the first electrode 41 and the second electrode 42.

[0086] The technical solution of this embodiment is further illustrated below through the fabrication process of the 3D memory in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0087] In this embodiment, each layer includes multiple storage units, but this embodiment is not limited to this, and each layer may include one storage unit.

[0088] In one exemplary embodiment, the fabrication process of the 3D memory may include:

[0089] S101) A sacrificial layer film 9 and a conductive film 11 are sequentially and alternately deposited on the substrate 1 to form a stacked structure, such as Figure 2 As shown.

[0090] In one exemplary embodiment, the sacrificial layer film 9 and the conductive film 11 can be deposited using a plasma-enhanced chemical vapor deposition (PECVD) method.

[0091] In one exemplary embodiment, the substrate 1 may be a semiconductor substrate, such as a silicon substrate.

[0092] In one exemplary embodiment, the sacrificial layer film 9 may be polysilicon.

[0093] In one exemplary embodiment, the conductive thin film 11 may include, but is not limited to, a multilayer structure of titanium nitride (TiN) / tungsten (W).

[0094] Figure 2 The stacked structure shown includes four sacrificial film layers 9 and three conductive film layers 11. This is merely an example; in other embodiments, the stacked structure may include more or fewer layers of sacrificial film layers 9 and conductive film layers 11 arranged alternately.

[0095] (S102) The stacked structure is patterned to form a sacrificial layer 10 and a conductive layer 12. The conductive layer 12 may include a preset electrode pattern and a bit line 30. The preset electrode pattern may include a plurality of first sub-parts 21 and a plurality of second sub-parts 22. The bit line 30 connects the first sub-parts 21 and the second sub-parts 22. The first sub-parts 21 may extend along a first direction X, the second sub-parts 22 may extend along the first direction X, and the bit line 30 may extend along a second direction Y. The first sub-parts 21 subsequently form the first electrode 51 and the second electrode 52 of a transistor, and the second sub-parts 22 subsequently form the first electrode 51 and the second electrode 52 of an adjacent transistor. The sacrificial layer film 9 and the conductive film 11 located in the preset isolation region may be etched away to form the sacrificial layer 10 and the conductive layer 12.

[0096] A first insulating film is filled into the predetermined isolation area to form a first insulating layer 2, thereby isolating different devices, such as... Figure 3A and Figure 3B As shown, where, Figure 3A The image shown is a cross-sectional view parallel to the direction of the substrate (a cross-sectional view of the region where the conductive layer 12 is located; all subsequent cross-sectional views parallel to the direction of the substrate 1 will be cross-sectional views of the region where the conductive layer 12 is located, and will not be described again). Figure 3B This is a cross-sectional view in the bb' direction.

[0097] In an exemplary embodiment, the stacked structure can be etched using a dry etching method to form the first conductive layer 12.

[0098] In one exemplary embodiment, the first insulating film may be silicon nitride (SiN).

[0099] S103) Open the preset capacitor area 100, including:

[0100] Dry etching is used to remove the first insulating layer 2 located in the preset capacitance region 100, exposing one end of the first sub-part 21 away from the bit line 30 (including the end face of the first sub-part 21 away from the bit line 30 and the side face of the first sub-part 21 located in the preset capacitance region 100 perpendicular to the substrate 1), and exposing one end of the second sub-part 22 away from the bit line 30 (including the end face of the second sub-part 22 and the side face of the second sub-part 22 located in the preset capacitance region 100 perpendicular to the substrate 1).

[0101] The sacrificial layer 10 located in the preset capacitance region 100 of the stacked structure is etched laterally using wet etching, exposing the side surface of the first sub-part 21 of the preset capacitance region 100 parallel to the substrate 1, and exposing the side surface of the second sub-part 22 of the preset capacitance region 100 parallel to the substrate 1, as shown. Figure 4A and Figure 4B As shown, where, Figure 4A This is a cross-sectional view parallel to the direction of the substrate 1 (a cross-sectional view of the region where the conductive layer 12 is located). Figure 4B The diagram shows a cross-sectional view along the direction aa', where the direction aa' can be parallel to the extension direction of the first sub-part 21.

[0102] (S104) A second insulating film and a conductor material are sequentially deposited in the preset capacitor region 100 to form a second insulating layer 13 and a second electrode plate 42, respectively. The second insulating layer 13 covers the exposed area of ​​the first sub-part 21, that is, the second insulating layer 13 covers the end face of the first sub-part 21 away from the bit line 30 and part of the sidewall, such as... Figure 5A , Figure 5B and Figure 5C As shown, where, Figure 5A This is a cross-sectional view parallel to the direction of the substrate. Figure 5B This is a cross-sectional view in the aa' direction. Figure 5C This is a cross-sectional view in the bb' direction.

[0103] In this configuration, the second insulating layer 13 serves as the dielectric between the capacitor plates, the second plate 42 serves as one electrode of the capacitor, and the first sub-part 21 or the second sub-part 22 serves as the other electrode of the capacitor, namely the first plate 41.

[0104] In one exemplary embodiment, the second insulating film and conductor material can be deposited by atomic layer deposition (ALD).

[0105] In one exemplary embodiment, the second insulating film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The High-K dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide (Al₂O₃), and hafnium oxide.

[0106] In one exemplary embodiment, the conductor material includes, but is not limited to, at least one or a combination of the following: doped semiconductor, conductive metal nitride, metal, metal silicide, conductive oxide. Examples include polycrystalline silicon, tungsten, titanium nitride, etc.

[0107] In one exemplary embodiment, before depositing the second insulating film, TiN or the like can be deposited in the preset capacitor region 100, together with a portion of the first sub-part 21 or the second sub-part 22, to serve as the first electrode 41 of the capacitor.

[0108] S105) forms multiple initial vias K0;

[0109] The formation of multiple initial vias K0 may include: etching the stacked structure using dry etching to form multiple initial vias K0 penetrating the multiple conductive layers, wherein the sidewalls of the initial vias K0 expose each of the conductive layers 12, and both the first sub-part 21 and the second sub-part 22 are provided with the vias K0, such as... Figure 6A , Figure 6B and Figure 6C As shown, where, Figure 6A This is a cross-sectional view parallel to the direction of the substrate. Figure 6B This is a cross-sectional view in the aa' direction. Figure 6C This is a cross-sectional view along the bb' direction. The bb' direction can be perpendicular to the aa' direction. The initial via K0 can extend along a direction perpendicular to the substrate. The initial via K0 includes a first sub-via K11 located in the sacrificial layer 10 and a second initial sub-via K12 located in the conductive layer 12.

[0110] In an exemplary embodiment, when dry etching is performed on the stacked structure, a high aspect ratio etching (HARET) method is used, wherein the aspect ratio is, for example, >6:1.

[0111] In an exemplary embodiment, the orthographic projection of the initial via K0 onto a plane parallel to the substrate can be circular or elliptical, but is not limited thereto; it can be square, hexagonal, etc.

[0112] In an exemplary embodiment, the orthographic projection of the initial via K0 on a plane parallel to the substrate 1 lies within the orthographic projection of the conductive layer 12. For example, on a plane parallel to the substrate 1, the orthographic projection of the initial via K0 penetrating the first sub-part 21 lies within the orthographic projection of the first sub-part 21, and the orthographic projection of the initial via K0 penetrating the second sub-part 22 lies within the orthographic projection of the second sub-part 22.

[0113] S106) The conductive layer 12 is etched in a direction away from the initial via K0, so that the second initial sub-via K12 of the initial via K0 located in the conductive layer 12 is expanded in a direction away from the initial via K0 to form a second sub-via K12', such that the orthographic projection of the first sub-via K11 located in the sacrificial layer 10 falls within the orthographic projection of the second sub-via K12' located in the conductive layer 12 on a plane parallel to the substrate 1, and such that the conductive layer 12 forms a first electrode 51 and a second electrode 52 that are separated from each other; Figure 7A , Figure 7B and Figure 7C As shown, where, Figure 7A This is a cross-sectional view parallel to the direction of the substrate. Figure 7B This is a cross-sectional view in the aa' direction. Figure 7C This is a cross-sectional view in the bb' direction. Multiple first sub-holes K11 and multiple second sub-holes K12' constitute a via K1, which forms multiple dumbbell-shaped structures.

[0114] In an exemplary embodiment, wet etching can be used, employing an acid solution with a high etching selectivity for both the sacrificial layer 10 and the conductive layer 12. The conductive layer 12 is etched laterally to a predetermined thickness L in the direction away from the via K0. Due to the high etching selectivity, the sacrificial layer 10 is almost completely etched. Taking a circular cross-section of the via K1 parallel to the substrate as an example, the diameter of the via K1 located in the conductive layer 12 is D, and the diameter of the via K1 located in the sacrificial layer 10 is d, where D = d + 2 * L. In an exemplary embodiment, D is, for example, 80 nm to 110 nm, d is, for example, 50 nm ± 10%, and L is, for example, 15 nm to 30 nm. For instance, D can be 80 nm and L can be 15 nm, or D can be 90 nm and L can be 20 nm, or D can be 100 nm and L can be 25 nm, or D can be 110 nm and L can be 30 nm.

[0115] S107) forms a semiconductor layer 23, a gate insulating layer 24 and a gate electrode 25.

[0116] The formation of the semiconductor layer 23, the gate insulating layer 24, and the gate electrode 25 includes:

[0117] A semiconductor thin film and a gate insulating thin film are sequentially deposited on the sidewall of the via K1 to form a semiconductor layer 23 and a gate insulating layer 24. After the semiconductor layer 23 and the gate insulating layer 24 are deposited, the size of the via K1 located in the parasitic MOS region 300 is smaller than the size of the via K1 located in the MOS channel region 200 in the first direction X.

[0118] A gate electrode film is deposited in the via K1 to form a gate electrode 25, which fills the via K1. Figure 8A , Figure 8Band Figure 8C As shown, where, Figure 8A This is a cross-sectional view parallel to the direction of the substrate 1. Figure 8B This is a cross-sectional view in the aa' direction. Figure 8C This is a cross-sectional view in the bb' direction.

[0119] In an exemplary embodiment, the semiconductor thin film, the gate insulating film, and the gate electrode thin film can be deposited by ALD.

[0120] In one exemplary embodiment, the semiconductor thin film includes, but is not limited to, at least one of the following: indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO). Using IGZO as the semiconductor layer offers advantages such as low leakage current and short refresh time.

[0121] In one exemplary embodiment, the gate insulating film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The High-K dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide (Al₂O₃), and hafnium oxide.

[0122] In one exemplary embodiment, the gate electrode film includes, but is not limited to, at least one of the following: indium tin oxide (ITO), TiN / W, aluminum-doped zinc oxide (AZO), and indium zinc oxide (IZO).

[0123] In an exemplary embodiment, the thickness of the semiconductor layer 23 along the radial direction of the via K1 can be 3 nm ± 10%, and the thickness of the gate insulating layer 24 along the radial direction of the via K1 can be 10 nm ± 10%. This is only an example, and the thicknesses of the semiconductor layer 23 and the gate insulating layer 24 can be other values.

[0124] S108) Etching removes the sacrificial layer 10.

[0125] The etching removal of the sacrificial layer 10 includes: dry etching a portion of the first insulating layer 2 near the capacitor side to expose the sacrificial layer 10 between the conductive layers without exposing the semiconductor layer 23; then, using an etchant with a high etch selectivity ratio for the semiconductor layer 23 and the gate insulating layer 24 compared to the sacrificial layer 10, lateral etching of the sacrificial layer 10 is performed to remove the sacrificial layer 10 between the conductive layers; and the sacrificial layer 10 located between two word lines can be etched away around the via K1. Figure 9AAs shown in 9B and 9C, where, Figure 9A This is a cross-sectional view parallel to the direction of the substrate. Figure 9B This is a cross-sectional view in the aa' direction. Figure 9C This is a cross-sectional view in the bb' direction.

[0126] In one exemplary embodiment, the etching solution is, for example, an acid solution, such as nitric acid (HNO3).

[0127] S109) Removing the semiconductor layer 23 of the via K1 located in the sacrificial layer 10 includes: etching the semiconductor layer 23 of the via K1 located in the sacrificial layer 10 using a hydrofluoric acid (HF) solution of a preset concentration, that is, etching the semiconductor layer 23 of the via K1 located in the parasitic MOS region 300, such as... Figure 10A As shown in 10B and 10C, where, Figure 10A This is a cross-sectional view parallel to the direction of the substrate. Figure 10B This is a cross-sectional view in the aa' direction. Figure 10C This is a cross-sectional view in the bb' direction.

[0128] In an exemplary embodiment, to ensure complete removal of the parasitic capacitance semiconductor layer 23, part or all of the gate insulating layer 24 of the via K1 located in the parasitic MOS region 300 can be etched away. Etching away the gate insulating layer 24 helps reduce parasitic capacitance. The solution provided in this embodiment can sufficiently remove the semiconductor layer 23 of the via K1 located in the parasitic MOS region 300, thus reducing parasitic capacitance and contributing to device stability.

[0129] In this embodiment, since the semiconductor layer 23 located in the channel region 200 is protected by the conductive layer 10 and the first insulating layer 2, there will be little etching of the semiconductor layer 23 in the channel region 200. Therefore, the effective length of the channel is not significantly affected.

[0130] S110) Remove the first insulating layer 2, deposit the third insulating film to form the third insulating layer 3, and achieve isolation between different devices, such as Figure 11A As shown in 11B and 11C, where, Figure 11A This is a cross-sectional view parallel to the direction of the substrate 1. Figure 11B This is a cross-sectional view in the aa' direction. Figure 11C This is a cross-sectional view in the bb' direction.

[0131] In one exemplary embodiment, the first insulating layer 2 can be removed using either dry or wet etching.

[0132] In one exemplary embodiment, the third insulating film can be deposited using an ALD method.

[0133] In an exemplary embodiment, the third insulating film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0134] The solution provided in this embodiment can effectively reduce or eliminate MOS parasitic capacitance and increase device stability by etching away the interlayer semiconductor layer and gate insulating layer.

[0135] Figure 12 This is a flowchart illustrating a method for fabricating a 3D memory according to an embodiment of the present disclosure. In this embodiment, the 3D memory includes multiple layers of memory cells stacked along a direction perpendicular to the substrate, word lines, and each memory cell including a transistor and a capacitor. The transistor includes a first electrode, a second electrode, a gate electrode extending along a direction perpendicular to the substrate, and a semiconductor layer surrounding and insulated from the gate electrode. The capacitor includes a first plate and a second plate, as shown below. Figure 12 As shown, the method for fabricating the 3D memory may include:

[0136] Step 1201: Provide a substrate, and sequentially deposit sacrificial layer thin films and conductive thin films on the substrate to form a stacked structure. The stacked structure includes an alternating stack of sacrificial layers and conductive layers, and the conductive layers include a preset electrode pattern.

[0137] Step 1202: Forming a via through the stacked structure in a direction perpendicular to the substrate, the sidewalls of the via exposing each of the conductive layers, and the via causing the preset electrode pattern to form at least one pair of first electrodes and second electrodes separated from each other; the via includes a plurality of first sub-vias respectively located in the sacrificial layer and a plurality of second sub-vias respectively located in the conductive layer, and on a plane parallel to the substrate, the orthographic projection of the first sub-via falls within the orthographic projection of the second sub-via;

[0138] Step 1203: A semiconductor thin film and a gate insulating thin film are sequentially deposited on the sidewall of the via to form a multilayer semiconductor layer and a gate insulating layer of the transistor. The semiconductor layer is in contact with the first electrode and the second electrode. The channel between the first electrode and the second electrode in the same transistor is a horizontal channel. A gate electrode thin film is deposited in the via to fill the via to form a multilayer gate electrode of the transistor. The gate electrodes of the transistors in different layers are part of the word line.

[0139] Step 1204: Etch away the sacrificial layer to expose the semiconductor layer located within the first sub-via, and etch away the semiconductor layer located within the first sub-via.

[0140] The solution provided in this embodiment reduces the parasitic capacitance between transistors in different layers and improves device performance by setting a sacrificial layer between conductive layers and exposing the semiconductor layer between the conductive layers by etching the sacrificial layer.

[0141] In one exemplary embodiment, the channel between the first electrode and the second electrode can be a horizontal channel.

[0142] In one exemplary embodiment, the pattern forming a stacked structure may include:

[0143] The sacrificial layer film and the conductive film are etched using a dry etching method to remove the sacrificial layer film and the conductive film located in a predetermined isolation area, so as to form the stack of the alternately arranged sacrificial layer and conductive layer;

[0144] A first insulating film is deposited in the predetermined isolation area to form a first insulating layer, wherein the first insulating film is made of a different material than the sacrificial layer film.

[0145] In an exemplary embodiment, after the patterning of the stacked structure is formed, before forming the via penetrating the stacked structure in a direction perpendicular to the substrate, the process may further include:

[0146] Etching removes the first insulating layer and sacrificial layer located in the preset capacitor region to expose one end of the first electrode of each transistor layer;

[0147] A second insulating film and a conductor material are sequentially deposited in the preset capacitor region to form a second insulating layer and a second electrode of the capacitor. The second insulating layer covers the area where the first electrode is exposed, and the second electrode is isolated from the first electrode through the second insulating layer.

[0148] In one exemplary embodiment, the via formed through the stacked structure in a direction perpendicular to the substrate may include:

[0149] The stacked structure is etched to form an initial via through the stacked structure in a direction perpendicular to the substrate. The initial via includes a first sub-via and a second initial sub-via located in the conductive layer. The conductive layer is etched in a direction away from the initial via to enlarge the second initial sub-via to form the second sub-via.

[0150] In one exemplary embodiment, the sacrificial layer film may include polycrystalline silicon.

[0151] In one exemplary embodiment, the first insulating film may include silicon nitride.

[0152] In an exemplary embodiment, after etching away the semiconductor layer located within the first sub-via, the method further includes etching away at least a portion of the gate insulating layer located within the first sub-via. The solution provided in this embodiment ensures complete etching away of the semiconductor layer located within the first sub-via, minimizing parasitic capacitance, and etching away a portion of the gate insulating layer also helps reduce parasitic capacitance.

[0153] In an exemplary embodiment, when etching away the semiconductor layer located within the first sub-hole, the portion of the semiconductor layer located within the second sub-hole adjacent to the first sub-hole is also etched.

[0154] In one exemplary embodiment, the conductive layer may further include bit lines connected to the second electrode. Each layer of the 3D memory may include a plurality of memory cells, the second electrodes of which are connected to the bit lines.

[0155] This disclosure provides a 3D memory, which is fabricated using the 3D memory fabrication method described above.

[0156] This disclosure also provides an electronic device, including the 3D memory described in the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0157] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A method for fabricating a 3D memory, characterized in that, The 3D memory includes multiple layers of memory cells stacked along a direction perpendicular to the substrate, word lines, and each memory cell including a transistor and a capacitor. The transistor includes a first electrode, a second electrode, a gate electrode extending along a direction perpendicular to the substrate, and a semiconductor layer surrounding and insulated from the gate electrode. The capacitor includes a first plate and a second plate. The method for fabricating the 3D memory includes: A substrate is provided, and a sacrificial layer thin film and a conductive thin film are sequentially and alternately deposited on the substrate to form a stacked structure. The stacked structure includes an alternating stack of sacrificial and conductive layers, and the conductive layer includes a preset electrode pattern. A via is formed through the stacked structure in a direction perpendicular to the substrate, the sidewalls of the via exposing each of the conductive layers, and the via causes the preset electrode pattern to form at least one pair of first electrodes and second electrodes that are separated from each other; the via includes a plurality of first sub-vias respectively located in the sacrificial layer and a plurality of second sub-vias respectively located in the conductive layer, and on a plane parallel to the substrate, the orthographic projection of the first sub-via falls into the orthographic projection of the second sub-via; A semiconductor thin film and a gate insulating thin film are sequentially deposited on the sidewall of the via to form a multilayer semiconductor layer and a gate insulating layer of the transistor. The semiconductor layer is in contact with the first electrode and the second electrode. The channel between the first electrode and the second electrode in the same transistor is a horizontal channel. A gate electrode thin film is deposited in the via to fill the via to form a multilayer gate electrode of the transistor. The gate electrodes of the transistors in different layers are part of the word line. The sacrificial layer is etched away to expose the semiconductor layer located within the first sub-via.

2. The method for fabricating a 3D memory according to claim 1, characterized in that, The configuration forming the stacked structure includes: The sacrificial layer film and the conductive film are etched using a dry etching method to remove the sacrificial layer film and the conductive film located in a predetermined isolation area, so as to form the stack of the alternately arranged sacrificial layer and conductive layer; A first insulating film is deposited in the predetermined isolation area to form a first insulating layer, wherein the first insulating film is made of a different material than the sacrificial layer film.

3. The method for fabricating a 3D memory according to claim 2, characterized in that, After the pattern is formed into a stacked structure, before forming a via through the stacked structure in a direction perpendicular to the substrate, the method further includes: Etching removes the first insulating layer and sacrificial layer located in the preset capacitor region to expose one end of the first electrode of each transistor layer; A second insulating film and a conductor material are sequentially deposited in the preset capacitor region to form a second insulating layer and a second electrode of the capacitor. The second insulating layer covers the area where the first electrode is exposed, and the second electrode is isolated from the first electrode through the second insulating layer.

4. The method for fabricating a 3D memory according to claim 1, characterized in that, The via formed in a direction perpendicular to the substrate through the stacked structure includes: The stacked structure is etched to form an initial via through the stacked structure in a direction perpendicular to the substrate. The initial via includes a first sub-via and a second initial sub-via located in the conductive layer. The conductive layer is etched in a direction away from the initial via to enlarge the second initial sub-via to form the second sub-via.

5. The method for fabricating a 3D memory according to claim 1, characterized in that, The sacrificial layer film comprises polycrystalline silicon.

6. The method for fabricating a 3D memory according to claim 2, characterized in that, The first insulating film comprises silicon nitride.

7. The method for fabricating a 3D memory according to claim 1, characterized in that, After etching away the semiconductor layer located within the first sub-hole, the method further includes etching away at least a portion of the gate insulating layer located within the first sub-hole.

8. The method for fabricating a 3D memory according to claim 2, characterized in that, The conductive layer further includes bit lines that are connected to the second electrode.

9. A 3D memory, characterized in that, The 3D memory is prepared using the method for preparing a 3D memory as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Including the 3D memory as described in claim 9.

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