Integrated circuit and method of its layout

Abstract

An integrated circuit and a layout method thereof, the integrated circuit includes a functional circuit and a first power switch chain. The first power switch chain includes a first power switch circuit and a second power switch circuit and is coupled between a power source and the functional circuit. The first power switch chain is configured to receive a first control signal, and the first control signal is configured to control whether the first power switch circuit and the second power switch circuit are turned on. A first resistance value of the first power switch circuit is different from a second resistance value of the second power switch circuit.

Description

Technical Field

[0001] This disclosure relates to a power switch chain technology. In particular, it relates to an integrated circuit comprising a non-uniform architecture power switch chain and a layout method thereof. Background Technology

[0002] With the advancement of technology and manufacturing processes, the impact of leakage current on the overall power consumption of circuits is becoming increasingly significant. To reduce leakage current power consumption, for specific circuits in integrated circuits with high leakage current power consumption, the corresponding power switching circuit can be controlled to stop supplying power to them during their idle periods. Summary of the Invention

[0003] Some embodiments of this disclosure relate to an integrated circuit. The integrated circuit includes a functional circuit and a first power switch chain. The first power switch chain includes a first power switch circuit and a second power switch circuit and is coupled between a power supply and the functional circuit. The first power switch chain is used to receive a first control signal, and the first control signal is used to control whether the first power switch circuit and the second power switch circuit are turned on or off. A first resistance value of the first power switch circuit is different from a second resistance value of the second power switch circuit.

[0004] Some embodiments of this disclosure relate to a layout method for an integrated circuit. The layout method includes the following operations: determining the positions of a first power switch circuit and a second power switch circuit in a first power switch chain by a processor; generating layout information for a functional circuit by the processor, wherein the first power switch circuit and the second power switch circuit are coupled between a power supply and the functional circuit; generating a simulation result by the processor based on the layout information of the functional circuit; and determining a first resistance value for the first power switch circuit and a second resistance value for the second power switch circuit by the processor based on the simulation result, wherein the first resistance value is different from the second resistance value.

[0005] In summary, in this disclosure, the power switch chain consists of at least two power switch circuits with different resistance values ​​to form a non-uniform architecture. This balances circuit performance and circuit area. Attached Figure Description

[0006] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0007] Figure 1 This is a schematic diagram of a design system shown in accordance with some embodiments of the present disclosure;

[0008] Figure 2 This is a functional block diagram of an integrated circuit shown in some embodiments of the present disclosure;

[0009] Figure 3 This is a flowchart illustrating a layout method according to some embodiments of the present disclosure;

[0010] Figure 4 This is a schematic diagram of a preset power switch chain and a functional circuit according to some embodiments of the present disclosure;

[0011] Figure 5 This is a schematic diagram illustrating a simulation result according to some embodiments of the present disclosure;

[0012] Figure 6A These are schematic diagrams of different sub-circuits shown according to some embodiments of this disclosure;

[0013] Figure 6B These are schematic diagrams of different sub-circuits shown according to some embodiments of this disclosure;

[0014] Figure 6C These are schematic diagrams of different sub-circuits shown according to some embodiments of this disclosure;

[0015] Figure 7 As shown in some embodiments of this disclosure Figure 5 A schematic diagram of different regions of the simulation results;

[0016] Figure 8 This is a schematic diagram of an integrated circuit shown according to some embodiments of the present disclosure; and

[0017] Figure 9 This is a schematic diagram of an integrated circuit shown according to some embodiments of the present disclosure.

[0018] Symbol Explanation

[0019] 100: Design System

[0020] 110: Processor

[0021] 120: Memory

[0022] 130: Input / Output Interface

[0023] 200, 800, 900: Integrated Circuits

[0024] 210: Power supply

[0025] 220, 220A, 220B, 220C, 220D: Power switch chain

[0026] 230: Functional Circuit

[0027] 300: Layout Method

[0028] 500: Simulation Results

[0029] PS, PS1, PS2, PS3: Power switch circuit

[0030] DX, DY: Distance

[0031] C1, C2, C3, C4, C5, C6, C7, C8, C9: Sub-circuits

[0032] A, B, C, D: Circuit regions

[0033] CS, CS1, CS2: Control signals

[0034] S310, S320, S330, S340: Operation Detailed Implementation

[0035] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to two or more components cooperating or interacting with each other.

[0036] refer to Figure 1 . Figure 1 This is a schematic diagram of a design system 100 shown according to some embodiments of the present disclosure.

[0037] by Figure 1 For example, the design system 100 includes a processor 110, a memory 120, and multiple input / output interfaces 130. The processor 110 is coupled to the memory 120 and the multiple input / output interfaces 130.

[0038] In some embodiments, the processor 110 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or other circuits with similar functions.

[0039] In some embodiments, the memory 120 may be implemented using a non-transitory computer-readable recording medium, such as a read-only memory, flash memory, floppy disk, hard disk, optical disk, flash drive, USB flash drive, magnetic tape, a database readable from a network, or any recording medium with the same functionality that can be conceived by one of ordinary skill in the art to which this disclosure pertains. The memory 120 may store a computer program to execute a layout program for an integrated circuit or to simulate or verify the layout information of an integrated circuit.

[0040] In some embodiments, the input / output interface 130 may be a display panel, keyboard, mouse, touch panel, or other device with similar functions. The input / output interface 130 is used to receive various inputs or instructions.

[0041] During the circuit design process, the user can operate the input / output interface 130. Then, the processor 110 can receive corresponding instructions and execute the computer program stored in the memory 120 according to these instructions, thereby performing some corresponding operations (e.g.: Figure 3 Layout method 300 in the middle.

[0042] refer to Figure 2 . Figure 2 This is a functional block diagram of an integrated circuit 200 shown in some embodiments of the present disclosure.

[0043] by Figure 2 For example, integrated circuit 200 includes a power supply 210, a power switch chain 220, and a functional circuit 230. Generally, the power supply 210 is coupled to the power switch chain 220 via a power mesh. The power switch chain 220 is coupled to the functional circuit 230 via a metal rail. That is, the power switch chain 220 is coupled between the power supply 210 and the functional circuit 230. In some embodiments, the power switch chain 220, the functional circuit 230, and the metal rail between them may be disposed in a first metal layer, while the power mesh may be disposed in a second metal layer above the first metal layer.

[0044] The power switch chain 220 can receive a control signal (e.g., from a control circuit (not shown)). Figure 8 The control signal CS in the power switch chain 220 can be used to turn on or off multiple power switch circuits in the power switch chain 220 (e.g., CS). Figure 8 The power switch circuits PS1-PS3 in the power switch chain 220 supply or stop supplying power from the power supply 210 to the various sub-circuits in the functional circuit 230. Specifically, when a power switch circuit in the power switch chain 220 is turned on, power from the power supply 210 can be sequentially transmitted through the power grid, the power switch circuit, and the metal rail to a corresponding sub-circuit in the functional circuit 230. When a power switch circuit in the power switch chain 220 is turned off, power from the power supply 210 cannot be supplied to the corresponding sub-circuit in the functional circuit 230 through that power switch circuit. In some embodiments, the power switch circuit can be turned off during the idle period of the corresponding sub-circuit to stop supplying power from the power supply 210 to that sub-circuit. This reduces the leakage current power consumption of the corresponding sub-circuit.

[0045] refer to Figure 3 . Figure 3This is a flowchart illustrating a layout method 300 according to some embodiments of this disclosure. Figure 3 For example, layout method 300 includes operations S310, S320, S330 and S340.

[0046] The following paragraphs will be paired Figures 4 to 8 The layout method 300 is described. Figure 4 This is a schematic diagram of a preset power switch chain 220A and a functional circuit 230 as shown in some embodiments of this disclosure. Figure 5 This is a schematic diagram of simulation results 500 shown according to some embodiments of the present disclosure. Figures 6A to 6C These are schematic diagrams of different sub-circuits C4-C9 shown in some embodiments of this disclosure. Figure 7 These are schematic diagrams of different regions in simulation results 500 shown according to some embodiments of this disclosure. Figure 8 This is a schematic diagram of an integrated circuit 800 shown according to some embodiments of the present disclosure.

[0047] In operation S310, the processor 110 determines the positions of multiple power switch circuits PS in the preset power switch chain 220A. Figure 4 For example, a preset power switch chain 220A includes multiple power switch circuits PS. The multiple power switch circuits PS are sequentially coupled to form a chain. Each power switch circuit PS may include one or more switches. In some embodiments, the switches in each power switch circuit PS may be implemented using multi-threshold CMOS (MTCMOS). Using the center point of the multiple power switch circuits PS as a reference, the processor 110 may predetermine the spacing distance between the multiple power switch circuits PS in direction X (e.g., distance DX) and the spacing distance between them in direction Y perpendicular to direction X (e.g., distance DY), thereby determining the position of the multiple power switch circuits PS.

[0048] In operation S320, the processor 110 generates layout information for the functional circuit 230. As previously mentioned, the processor 110 can first determine the positions of the plurality of power switch circuits PS in the preset power switch chain 220A. Furthermore, the processor 110 can pre-determine the type of power switch circuit PS. For example, the processor 110 can pre-determine that the plurality of power switch circuits PS are power switch circuits with the lowest resistance but the largest area (e.g.,...). Figure 7The power switch circuit PS1 is mentioned here. The resistance value of a power switch circuit PS refers to the overall equivalent resistance value of that power switch circuit PS. The area of ​​a power switch circuit PS refers to the area occupied by the layout of that power switch circuit PS. Next, the processor 110 can determine the portions that all power switch circuits PS may occupy based on the positions of the plurality of power switch circuits PS and the preset areas of the plurality of power switch circuits PS. Then, the processor 110 can arrange the functional circuit 230 in other portions not occupied by the power switch circuits PS to generate layout information for the functional circuit 230.

[0049] Generally, functional circuit 230 may contain one or more sub-circuits. Some sub-circuits are standard cell circuits, while others are non-standard cell circuits. Standard cell circuits, as referred to herein, include, for example, flip-flops, combinational logic, buffers, or inverters. Non-standard cell circuits, as referred to herein, include, for example, static random access memory (SRAM), analog blocks, or digital blocks.

[0050] For ease of understanding, Figure 4 The functional circuit 230 shown in the figure only shows sub-circuits C1-C3 as examples, while other sub-circuits in the functional circuit 230 are omitted. Figure 4 Sub-circuits C1-C3 in Figures 6A to 6C The sub-circuits C4-C9 in the circuit can be standard component circuits respectively.

[0051] In operation S330, the processor 110 generates a simulation result 500 based on the layout information of the functional circuit 230. For example, the processor 110 can execute a computer program stored in the memory 120 to simulate voltage drop (IR drop, or voltage drop) on the layout information generated in operation S320 to generate the simulation result 500. That is, the simulation result 500 is voltage drop information, and the simulation result 500 can reflect the voltage drop status of each sub-circuit in the functional circuit 230.

[0052] by Figure 6AFor example, the distance between sub-circuit C5 and the power supply pad is greater than the distance between sub-circuit C4 and the power supply pad. Assuming other conditions (e.g., component density, computational load) are the same or roughly similar for sub-circuit C4 and sub-circuit C5, the voltage drop of sub-circuit C5 will be greater than the voltage drop of sub-circuit C4 because the distance between sub-circuit C5 and the power supply pad is greater than the distance between sub-circuit C4 and the power supply pad.

[0053] In addition, with Figure 6B For example, suppose the component density of sub-circuit C6 is 90%, the component density of sub-circuit C7 is 40%, and other conditions of sub-circuit C6 and sub-circuit C7 (e.g., distance from the power pad, computational load) are the same or approximately similar. Since the component density of sub-circuit C6 is greater than that of sub-circuit C7, the voltage drop of sub-circuit C6 will be greater than that of sub-circuit C7.

[0054] Furthermore, with Figure 6C For example, suppose sub-circuit C8 is a computationally intensive circuit, sub-circuit C9 is a circuit with a long idle time, and other conditions of sub-circuit C8 and sub-circuit C9 (e.g., distance from the power supply pad, component density) are the same or roughly similar. Since the computational load of sub-circuit C8 is greater than that of sub-circuit C9, the voltage drop of sub-circuit C8 will be greater than that of sub-circuit C9.

[0055] In the above embodiments, the power pad PAD can be coupled to a power supply or a ground terminal to receive a power supply voltage or a ground voltage. It should be noted that although the above paragraphs illustrate the effect of a single condition on the voltage drop of a sub-circuit, in practical applications, the voltage drop of a sub-circuit may be caused by a combination of multiple conditions.

[0056] In operation S340, processor 110 determines the type of the plurality of power switch circuits PS based on simulation results 500 (e.g., determining the resistance value and area of ​​the plurality of power switch circuits PS). Figure 5 as well as Figure 7 For example, simulation result 500 can be divided into circuit region A, circuit region B, circuit region C, and circuit region D. Circuit region A is the region without standard component circuits. Circuit region B is the region with standard component circuits and its voltage drop is less than y%. Circuit region C is the region with standard component circuits and its voltage drop is greater than or equal to y% and less than x%. Circuit region D is the region with standard component circuits and its voltage drop is greater than or equal to x%.

[0057] First, since no standard component circuits are set in circuit area A, no power switch circuit PS will be laid out.

[0058] Furthermore, since the voltage drop in circuit region D is greater than that in circuit region C, the processor 110 will place power switch circuit PS1 at the location corresponding to circuit region D and power switch circuit PS2 at the location corresponding to circuit region C. The resistance value of power switch circuit PS1 is less than that of power switch circuit PS2, but the area of ​​power switch circuit PS1 is greater than that of power switch circuit PS2.

[0059] Similarly, since the voltage drop in circuit region C is greater than the voltage drop in circuit region B, the processor 110 will place power switch circuit PS2 at the location corresponding to circuit region C, and power switch circuit PS3 at the location corresponding to circuit region B. The resistance of power switch circuit PS2 is less than the resistance of power switch circuit PS3, but the area of ​​power switch circuit PS2 is greater than the area of ​​power switch circuit PS3.

[0060] In other words, the resistance values ​​of power switch circuits PS1, PS2, and PS3 are different from each other. The areas of power switch circuits PS1, PS2, and PS3 are also different from each other.

[0061] Based on the above principles, the processor 110 can... Figure 5 The simulation results 500 determine the types of the multiple power switch circuits PS. Figure 8 For example, in power switch chain 220B, power switch circuit PS1 will be set at the position corresponding to sub-circuit C1 (adjacent to sub-circuit C1), power switch circuit PS2 will be set at the position corresponding to sub-circuit C2 (adjacent to sub-circuit C2), and power switch circuit PS3 will be set at the position corresponding to sub-circuit C3 (adjacent to sub-circuit C3).

[0062] In some embodiments, after determining the location and type (resistance value and area) of the plurality of power switch circuits PS, the processor 110 can perform design rule check (DRC), layout versus schematic (LVS), or other verifications on the layout information of the entire integrated circuit 800 (including the power switch chain 220B and functional circuits 230). Once these verifications are passed, the integrated circuit 800 can be manufactured using semiconductor processes based on its layout information.

[0063] In some related technologies, the power switch chain is configured with a uniform architecture. That is, all power switch circuits in the chain are identical (all have the same resistance value and the same area). However, when configuring a power switch chain with only a single type of power switch circuit, users will select a power switch circuit with a small resistance value but a large area (e.g., power switch circuit PS1) to ensure that the overall voltage drop in the maximum voltage drop region meets design requirements. Because all power switch circuits are selected with small resistance values ​​but large areas, this power switch chain will occupy a large circuit area overall.

[0064] Compared to the aforementioned related technologies, in this disclosure, the power switch chain 220B includes different power switch circuits PS1-PS3, and the different power switch circuits PS1-PS3 (with different resistance values ​​and different areas) are appropriately configured in corresponding positions based on the simulation results 500 (e.g., voltage drop information). In this way, not only can the overall voltage drop of each circuit region meet the design requirements, but circuit area can also be saved.

[0065] It should be noted here that, although Figure 8 The present invention uses three power switch circuits PS1-PS3 as examples, but this disclosure is not limited to this number.

[0066] refer to Figure 9 . Figure 9 This is a schematic diagram of an integrated circuit 900 shown in accordance with some embodiments of the present disclosure.

[0067] Figure 9 The integrated circuit 900 in the system can be, for example, a multi-core system. That is, the integrated circuit 900 includes core circuit 910 and core circuit 920. The integrated circuit 900 may also include power switch chains 220C and 220D. Power switch chain 220C is located at a position corresponding to (adjacent to) core circuit 910, and power switch chain 220D is located at a position corresponding to (adjacent to) core circuit 920, and power switch chains 220C and 220D are independently controlled. That is, power switch chains 220C and 220D are controlled by different control signals. Figure 9For example, control signal CS1 is used to turn on or off multiple power switches in power switch chain 220C, while control signal CS2 is used to turn on or off multiple power switches in power switch chain 220C. Control signal CS1 or control signal CS2 may originate from one or more control circuits (not shown). When core circuit 910 is not operating (during the idle period of core circuit 910), control signal CS1 can turn off the multiple power switch circuits in power switch chain 220C to stop power supply to core circuit 910. When core circuit 910 is operating (during the operation of core circuit 910), control signal CS1 can turn on the multiple power switch circuits in power switch chain 220C to supply power to core circuit 910. Similarly, when core circuit 920 is not operating (during the idle period of core circuit 920), control signal CS2 can turn off the multiple power switch circuits in power switch chain 220D to stop power supply to core circuit 920. When the core circuit 920 is running (during operation of the core circuit 920), the control signal CS2 can turn on the plurality of power switch circuits in the power switch chain 220D to supply power to the core circuit 920.

[0068] The configurations of power switch chains 220C and 220D are similar. Figure 8 The power switch chain 220B is described above. That is, power switch chain 220C or power switch chain 220D contains power switch circuits with different resistance values ​​(different areas), and these multiple power switch circuits are sequentially coupled to form a chain. Further details can be found in the paragraphs related to power switch chain 220B, and will not be repeated here.

[0069] In summary, in this disclosure, the power switch chain consists of at least two power switch circuits with different resistance values ​​to form a non-uniform architecture. This balances circuit performance and circuit area.

[0070] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various changes and modifications without departing from the concept and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the claims.

Claims

1. An integrated circuit, comprising: A functional circuit; and A first power switch chain includes a first power switch circuit and a second power switch circuit and is coupled between a power supply and the functional circuit, wherein the first power switch chain is used to receive a first control signal, and the first control signal is used to turn on or off the first power switch circuit and the second power switch circuit. The first resistance value of the first power switch circuit is different from the second resistance value of the second power switch circuit.

2. The integrated circuit of claim 1, wherein the functional circuit comprises a first sub-circuit and a second sub-circuit, the position of the first power switch circuit corresponds to the first sub-circuit, the position of the second power switch circuit corresponds to the second sub-circuit, a first voltage drop of the first sub-circuit is greater than a second voltage drop of the second sub-circuit, and the first resistance value is less than the second resistance value.

3. The integrated circuit of claim 2, wherein the area of ​​the first power switch circuit is larger than the area of ​​the second power switch circuit.

4. The integrated circuit of claim 2, wherein the functional circuit further includes a third sub-circuit, the first power switch chain further includes a third power switch circuit, and the position of the third power switch circuit corresponds to the third sub-circuit. The second voltage drop is greater than a third voltage drop of the third sub-circuit, and the second resistance value is less than a third resistance value of the third power switch circuit.

5. The integrated circuit of claim 4, wherein the area of ​​the second power switch circuit is larger than the area of ​​the third power switch circuit.

6. The integrated circuit of claim 2, wherein a first distance between the first sub-circuit and a power pad is greater than a second distance between the second sub-circuit and the power pad, a first element density of the first sub-circuit is greater than a second element density of the second sub-circuit, or a first computational power of the first sub-circuit is greater than a second computational power of the second sub-circuit.

7. The integrated circuit of claim 1, further comprising: A second power switch chain, comprising a third power switch circuit and a fourth power switch circuit and coupled between the power supply and the functional circuit, wherein the second power switch chain is used to receive a second control signal, and the second control signal is used to control whether the third power switch circuit and the fourth power switch circuit are turned on or off. The third resistor value of the third power switch circuit is different from the fourth resistor value of the fourth power switch circuit.

8. The integrated circuit of claim 7, wherein the functional circuit comprises a first core circuit and a second core circuit, the position of the first power switch chain corresponds to the first core circuit, and the position of the second power switch chain corresponds to the second core circuit.

9. A layout method for an integrated circuit, comprising: The positions of a first power switch circuit and a second power switch circuit in a first power switch chain are determined by a processor. The processor generates layout information for a functional circuit, wherein the first power switch circuit and the second power switch circuit are coupled between a power supply and the functional circuit. The processor generates a simulation result based on the layout information of the functional circuit; and Based on the simulation results, the processor determines a first resistance value for the first power switch circuit and a second resistance value for the second power switch circuit. The first resistance value is different from the second resistance value.

10. The layout method of claim 9, wherein the simulation result is a voltage drop information.

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