Display panel

Abstract

The present application discloses a display panel, comprising a thin film transistor array substrate, a liquid crystal layer, and an opposing substrate; the thin film transistor array substrate comprising: a control device layer comprising a plurality of control devices; a color filter layer disposed on the control device layer, the color filter layer comprising a plurality of color resist portions of different colors; a first planarization layer disposed on a surface of the color filter layer close to the opposing substrate; a first passivation layer disposed on the first planarization layer; a pixel electrode disposed between the first planarization layer and the first passivation layer; a first common electrode disposed on the first passivation layer; and a first light shielding layer disposed on a surface of the first common electrode close to or away from the opposing substrate, the first light shielding layer covering at least the partially overlapping portion of two adjacent color resist portions of different colors. The present application can effectively improve the problem of low yield of the display panel and the problem of severe color shift at large viewing angles caused by large errors in the alignment accuracy of the thin film transistor array substrate and the opposing substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] Liquid crystal display panels are typically composed of a thin film transistor array substrate and a color filter substrate. During the manufacturing process, the thin film transistor array substrate and the color filter substrate need to be precisely assembled (aligned), and the alignment accuracy requirements increase with the increase in pixel density.

[0003] For display panels used in mobile phones and flat-panel displays, alignment accuracy is typically around 2 microns. However, for display panels used in virtual reality (VR) products, alignment accuracy is required to be even higher due to the very small pixel pitch, which can easily lead to larger alignment errors.

[0004] Too large an alignment error can easily cause serious product yield issues.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0006] The purpose of this application is to provide a display panel to avoid serious product yield problems caused by excessive alignment errors.

[0007] To solve the above problems, the technical solutions of this application are as follows:

[0008] The present application proposes a display panel, which includes a thin film transistor array substrate, a liquid crystal layer and an opposing substrate, wherein the liquid crystal layer is arranged between the thin film transistor array substrate and the opposing substrate; the thin film transistor array substrate includes: a control device layer, wherein the control device layer includes multiple control devices; a color filter layer, wherein the color filter layer is arranged on the control device layer, the color filter layer includes multiple color resist portions of different colors, and two adjacent color resist portions of different colors partially overlap; a first planarization layer, wherein the first planarization layer is arranged on a surface of the color filter layer close to the opposing substrate; a first passivation layer, wherein the first passivation layer is arranged on the first planarization layer; a pixel electrode, wherein the pixel electrode is arranged between the first planarization layer and the first passivation layer; a first common electrode, wherein the first common electrode is arranged on the first passivation layer; and a first light-shielding layer, wherein the first light-shielding layer is arranged on a surface of the first common electrode close to or away from the opposing substrate, and the first light-shielding layer at least covers the partially overlapping portion of two adjacent color resist portions of different colors.

[0009] In the display panel of the present application, a second light-shielding layer is provided in the counter substrate, and the light-shielding range of the first light-shielding layer is different from the light-shielding range of the second light-shielding layer.

[0010] In the display panel of the present application, the control device layer also includes multiple gate lines, the first shading layer includes multiple first shading strips parallel to each other, and the length direction of the first shading strips is perpendicular to the length direction of the gate lines; the second shading layer includes multiple second shading strips parallel to each other, and the length direction of the second shading strips is parallel to the length direction of the gate lines.

[0011] In the display panel of the present application, the width of the first light-shielding strip is smaller than the width of the second light-shielding strip.

[0012] In the display panel of the present application, the edge portion of the color resist portion is located within the light shielding range of the first light shielding strip, and the gate line is located within the light shielding range of the second light shielding strip.

[0013] In the display panel of the present application, a first groove is provided between two adjacent color resist portions in a direction perpendicular to the length direction of the gate line, and the length direction of the first groove is parallel to the length direction of the gate line; a second groove is provided on the first planarization layer, and the second groove is arranged in the first groove; a portion of the pixel electrode is provided in the first groove and is electrically connected to the control device; a portion of the first passivation layer is provided on the surface of the portion of the pixel electrode located in the first groove.

[0014] In the display panel of the present application, a second common electrode and a second passivation layer are arranged between the first planarization layer and the first passivation layer, the second common electrode is arranged on the first planarization layer, a portion of the second passivation layer is arranged between the second common electrode and the pixel electrode, and another portion of the second passivation layer is arranged between the second common electrode and the first passivation layer; wherein, the second common electrode and the second passivation layer are disconnected at the first groove.

[0015] In the display panel of the present application, a portion of the first common electrode is arranged in the second groove; the thin film transistor array substrate also includes a second planarization layer, and a portion of the second planarization layer is arranged on the portion of the first common electrode located in the second groove; a support member is provided on a surface of the opposing substrate close to the thin film transistor array substrate, and the end of the support member away from the opposing substrate is in contact with the second planarization layer.

[0016] In the display panel of the present application, the thickness of the first light-shielding layer is 700 angstroms to 2000 angstroms, and the thickness of the second light-shielding layer is 10000 angstroms to 30000 angstroms.

[0017] In the display panel of the present application, the first light-shielding layer is a metal layer, a metal oxide layer, or a stack of both, and the second light-shielding layer is a resin layer.

[0018] The display panel provided by the present application adopts a technical solution of transferring the color filter layer and the light shielding layer to the thin film transistor array substrate, which can effectively improve the low yield problem and the serious color deviation problem of large viewing angle caused by large alignment accuracy error in the high pixel density display panel in the prior art. In the display panel provided by the present application, firstly, the color filter layer and the first light shielding layer are transferred to the side of the thin film transistor array substrate, so that the color filter layer and the first light shielding layer can be self-aligned in the same machine. Compared with the solution of aligning the thin film transistor array substrate and the color filter substrate provided with the color filter, the alignment accuracy of the light shielding layer can be greatly improved. At the same time, the color filter layer and the first light shielding layer are transferred to the thin film transistor array substrate, which can eliminate the influence of the alignment error of the thin film transistor array substrate and the opposing substrate in the length direction of the gate line on the product yield, thereby improving the product yield. Secondly, because the dimensional accuracy of the components made of metal or metal oxide by the mask process and the etching process is greater than that by the mask process, the dimensional accuracy of the components made of metal or metal oxide by the mask process is greater than that by the mask process. and the dimensional accuracy of the parts made of resin by the etching process, therefore, in the present application, the first light-shielding layer is made of metal or metal oxide material, which can make the shape and size of the first light-shielding layer more consistent with the shape and size of the light-transmitting hole of the mask plate, and the line width of the first light-shielding layer is smaller and the line width uniformity is higher, so that the opening of the pixel is larger, thereby increasing the aperture ratio and improving the display quality of the display panel; thirdly, since the color filter layer and the first light-shielding layer are transferred to the thin film transistor array substrate, the optical path difference of light passing through the display panel at different viewing angles can be reduced, the color deviation at a large viewing angle can be reduced, and the viewing angle range can be expanded; finally, since the gate line is shielded by the second light-shielding layer, the dark area caused by the electric field region of the gate line can be prevented from appearing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a first embodiment of a display panel provided in this application.

[0020] Figure 2 yes Figure 1 Schematic diagram of the positional relationship among the color filter layer, the first groove and the second groove in the display panel shown.

[0021] Figure 3 is a schematic diagram of a second embodiment of a display panel provided in this application.

[0022] Figure 4 yes Figure 3 Schematic diagram of the positional relationship among the first light shielding layer, the second light shielding layer and the first common electrode in the display panel shown.

[0023] Figure 5 is a schematic diagram of a third embodiment of a display panel provided in this application.

[0024] Figure 6 is a schematic diagram of a fourth embodiment of a display panel provided in this application. DETAILED DESCRIPTION

[0025] The meanings of the terms used in this specification and claims correspond to those commonly understood by persons of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are intended solely to facilitate the description and understanding of this application and are not intended to limit this application to the narrow interpretations of the specific terms used in the specification and claims.

[0026] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0027] The present application is described in detail below with reference to specific embodiments. It should be noted that the following embodiments are only used to illustrate the present application and do not limit the scope of protection of the present application.

[0028] This application is aimed at improving the display panels of VR products with high PPI (Pixels Per Inch).

[0029] like Figure 1 and Figure 2 As shown, in a first embodiment of a display panel provided in this application, the display panel is a liquid crystal display panel, comprising a thin film transistor array substrate, a liquid crystal layer, and an opposing substrate. The thin film transistor array substrate and the opposing substrate are integrated into one body, and the liquid crystal layer is disposed between the thin film transistor array substrate and the opposing substrate. The liquid crystal layer comprises liquid crystal molecules.

[0030] In this embodiment, the color filter layer 111 and the first light shielding layer of the display panel are disposed in the thin film transistor array substrate.

[0031] The thin film transistor array substrate includes: a first substrate 101, a light blocking layer 102, a buffer layer 103, a semiconductor layer 104, a gate insulating layer 105, a gate electrode 106, a first interlayer insulating layer 107, a second interlayer insulating layer 110, a source electrode 108, a drain electrode 109, a color filter layer 111, a first planarization layer 112, a pixel electrode 113, a first passivation layer 114, a first common electrode 116, a first light blocking layer (metal light blocking layer), and a second planarization layer 117. The light blocking layer 102, the buffer layer 103, the semiconductor layer 104, the gate insulating layer 105, the gate electrode 106, the first interlayer insulating layer 107, the second interlayer insulating layer 110, the source electrode 108, and the drain electrode 109 constitute a control device layer, which includes a plurality of control devices, which may be, for example, thin film transistors including a gate, a source electrode, and a drain electrode.

[0032] In the thin film transistor array substrate, the light-blocking layer 102 is arranged on the first substrate 101, the buffer layer 103 is arranged on the first substrate 101 and covers the light-blocking layer 102, the semiconductor layer 104 is arranged on the buffer layer 103, and the semiconductor layer 104 is located within the light-blocking range of the light-blocking layer 102, the gate insulating layer 105 is arranged on the buffer layer 103 and covers the semiconductor layer 104, the gate 106 is arranged on the gate insulating layer 105, the first interlayer insulating layer 107 is arranged on the gate insulating layer 105 and covers the gate 106, the source 108 is arranged on the first interlayer insulating layer 107, the second interlayer insulating layer 110 is arranged on the first interlayer insulating layer 107 and covers the source 108, and the drain 109 is arranged on the second interlayer insulating layer 110.

[0033] In the present application, the color filter layer 111 is arranged on the control device layer. Specifically, the color filter layer 111 is arranged on the second interlayer insulating layer 110 and is located below the first planarization layer 112. The color filter layer 111 is made of a low-thickness and high-color gamut material, which can reduce the thickness of the liquid crystal box and reduce the path that light must pass through, thereby reducing the optical path difference. The color filter layer 111 adopts an island-shaped design. The color filter layer 111 includes a plurality of color resist portions (islands) of different colors. Two adjacent color resist portions of different colors partially overlap at the junction of the two color resist portions. The partially overlapping portion of two adjacent color resist portions in the color filter layer 111 is located within the shading range of the first shading layer.

[0034] The first planarization layer 112 is arranged on the color filter layer 111. Specifically, the first planarization layer 112 is arranged on a surface of the color filter layer 111 close to the opposing substrate. The first planarization layer 112 covers the color filter layer 111, and the difference in film thickness of the color filter layer 111 is filled by the first planarization layer 112. That is, the first planarization layer 112 fills the depression at the junction (partial overlap) of the color filter layer 111 to reduce the impact of the uneven surface (depression) of the color filter layer 111 on the image quality.

[0035] The first passivation layer 114 is disposed on the first planarization layer 112 and covers the pixel electrode 113 .

[0036] The pixel electrode 113 is arranged between the first planarization layer 112 and the first passivation layer 114. A portion of the pixel electrode is arranged in the first groove and is electrically connected to the control device, that is, the pixel electrode 113 is connected to the drain electrode 109 in the thin film transistor array substrate.

[0037] The first common electrode 116 is disposed on the first passivation layer 114. A portion of the first common electrode 116 is located above a portion of the pixel electrode 113. The first common electrode 116 overlaps with the pixel electrode 113, i.e., the first common electrode 116 and the pixel electrode 113 form a capacitor. Both the first common electrode 116 and the pixel electrode 113 are made of ITO (Indium Tin Oxide).

[0038] The first light-shielding layer is disposed above or below the first common electrode 116. Specifically, the first light-shielding layer is disposed on a surface of the first common electrode that is close to or away from the counter substrate. For example, the first light-shielding layer is disposed on a surface of the first passivation layer 114, the first common electrode 116 covers the first light-shielding layer, and an insulating layer is disposed between the first light-shielding layer and the first common electrode 116. Alternatively, the first light-shielding layer is disposed on the first common electrode 116, and an insulating layer is disposed between the first light-shielding layer and the first common electrode 116. The first light-shielding layer at least covers the overlapping portion of two adjacent color-resist portions of different colors.

[0039] The first light-shielding layer includes a plurality of mutually parallel first light-shielding strips 115 and a plurality of mutually parallel second light-shielding strips 122. The overlapping portions of two adjacent color-blocking portions are located within the light-shielding range of the first light-shielding strips 115, i.e., the edges of the color-blocking portions are located within the light-shielding range of the first light-shielding strips, and the gate lines are located within the light-shielding range of the second light-shielding strips 122. The length of the first light-shielding strips 115 is perpendicular to the length of the gate lines of the control device layer, while the length of the second light-shielding strips 122 is parallel to the length of the gate lines. The thickness of the first light-shielding layer ranges from 700 angstroms to 2000 angstroms to prevent the surface of the thin-film transistor array substrate from being uneven due to excessive thickness, thereby causing dark areas in the liquid crystal. The first light-shielding layer is a laminate of one or both of a metal layer and a metal oxide layer. The first light-shielding layer can be a metal layer, a metal oxide layer, or a composite laminate of a metal and a metal oxide.

[0040] The width of the first light-shielding strip is smaller than the width of the second light-shielding strip.

[0041] The metal may be, for example, chromium, aluminum, or silver. The metal oxide may be, for example, chromium oxide (CrOx), aluminum oxide (AlOx), titanium nitride (TiN), titanium oxide (TiOx), silver oxide (Ag2O), or nickel oxide (NiO). The first light-shielding layer is formed by evaporating or sputtering a light-shielding metal layer, followed by patterning and etching to obtain the desired light-shielding shape.

[0042] Grooves are provided on the color filter layer and the first planarization layer. The grooves penetrate the color filter layer and the first planarization layer. The length of the grooves is parallel to the length of the gate lines. The grooves are located within the light shielding range of the second light shielding strips 122. The grooves include a first groove 121 and a second groove 120.

[0043] The color filter layer 111 is provided with a first groove 121. Figure 2As shown, in a direction perpendicular to the length direction of the gate line of the thin film transistor array substrate, a first groove is provided between two adjacent color resist portions. The length direction of the first groove is parallel to the length direction of the gate line. The width w2 of the first groove 121 is 2 μm to 6 μm. For example, the width of the first groove 121 is 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3 μm, 3.2 μm, 3.4 μm, 3.6 μm, 3.8 μm, 4 μm, 4.2 μm, 4.4 μm, 4.6 μm, 4.8 μm, 4.9 μm, 5.0 μm, 5.1 μm, 5.2 μm, 5.3 μm, 5.6 μm, 5.8 μm, 5.9 ... The color resist portions of the first groove 121 are spaced from 2 to 6 microns, for example, the spacing is 2 microns, 2.2 microns, 2.4 microns, 2.6 microns, 2.8 microns, 3 microns, 3.2 microns, 3.4 microns, 3.6 microns, 3.8 microns, 4 microns, 4.2 microns, 4.4 microns, 4.6 microns, 4.8 microns, 5 microns, 5.2 microns, 5.4 microns, 5.6 microns, 5.8 microns, and 6 microns.

[0044] In traditional VA (Vertical Alignment) display panels, due to ample space, through-holes are generally used. However, for display panels for VR products, due to material and equipment process limitations, through-holes are not practical. Therefore, the color filter layer 111 of this application adopts a horizontally disconnected design, that is, the color filter layer 111 is arranged in an island shape. Preferably, the spacing between the color filter portions of the islands in the color filter layer 111 is controlled to 4-5 microns.

[0045] The first planarization layer 112 is provided with a second groove 120. Specifically, the first planarization layer 112 is provided with the second groove 120 in the longitudinal direction of the gate line. The second groove 120 overlaps with the first groove 121, that is, the second groove is nested within the first groove. The second groove 120 of the first planarization layer 112 is nested with the first groove 121 of the color filter layer 111, that is, the second groove 120 that passes through the first planarization layer 112 is located within the first groove 121 that passes through the color filter layer 111. The width w1 of the second groove 120 is 1.6 microns to 6.4 microns. For example, the width w1 of the second groove 120 is 1.6 microns, 1.8 microns, 2.0 microns, 2.2 microns, 2.4 microns, 2.6 microns, 2.8 microns, 3 microns, 3.2 microns, 3.4 microns, 3.6 microns, 3.8 microns, 4 microns, 4.2 microns, 4.4 microns, 4.6 microns, 4.8 microns, 5 microns, 5.2 microns, 5.4 microns, 5.6 microns, 5.8 microns, 6.0 microns, 6.2 microns, and 6.4 microns.

[0046] The length direction of the first groove 121 is parallel to the length direction of the second shading strip 122. The first groove 121 and the second groove 120 are located within the shading range of the second shading strip 122. The length direction of the second groove 120 is parallel to the length direction of the first groove 121.

[0047] A portion of the first passivation layer 114 is disposed on the portion of the pixel electrode located in the groove, that is, a portion of the first passivation layer 114 is disposed on the surface of the portion of the pixel electrode 113 located in the first groove 121. A portion of the first common electrode is disposed in the second groove, and the portion of the first passivation layer 114 located in the first groove 121 / the second groove 120 forms a first recessed portion. A portion of the first common electrode 116 is disposed on the portion of the first passivation layer 114 located in the groove, that is, a portion of the first common electrode 116 is disposed in the first recessed portion, and the portion of the first common electrode 116 disposed in the first recessed portion forms a second recessed portion. The second planarization layer 117 is disposed in the second recessed portion, that is, a portion of the second planarization layer is disposed on the portion of the first common electrode located in the second groove.

[0048] In the display panel of the VR product, the second planarization layer 117 fills the disconnection between the color filter layer 111 and the first planarization layer 112 (the first groove 121 and the second groove 120 ), which is beneficial to the liquid crystal efficiency and the positioning of the support member 203 .

[0049] A portion of the pixel electrode is electrically connected to the source electrode in the control device layer exposed in the groove. That is, the pixel electrode 113 passes through the second groove 120 of the first planarizing layer 112 and the first groove 121 of the color filter layer 111, and is connected to the drain electrode 109 in the thin film transistor array substrate. Specifically, a portion of the pixel electrode 113 is disposed within the first groove 121, and the portion of the pixel electrode 113 disposed within the first groove 121 is connected to the drain electrode 109. The pixel electrode 113 is connected to the drain electrode 109 through the first groove 121 and the second groove 120, which are nested in each other, of the first planarizing layer 112 and the color filter layer 111.

[0050] The second planarization layer 117 is disposed on the portion of the first common electrode 116 located in the groove, that is, the second planarization layer 117 is disposed on the second depressed portion of the first common electrode 116 located in the first groove 121 .

[0051] At least a portion of the second light-shielding strip 122 is located below the portion of the first common electrode 116 disposed in the groove, or at least a portion of the second light-shielding strip 122 is disposed on the second planarization layer 117 .

[0052] A supporting member is provided on a surface of the opposing substrate close to the thin film transistor array substrate, and an end of the supporting member away from the opposing substrate is in contact with the second planarization layer, that is, the opposing substrate includes a second substrate 201 and a supporting member 203, the supporting member 203 is provided on the second substrate 201, and an end of the supporting member 203 away from the second substrate 201 is in contact with the second planarization layer 117.

[0053] In the present application, the color filter layer 111 and the first light-shielding layer located in the original opposing substrate are transferred to the thin film transistor array substrate, wherein the first light-shielding layer is arranged near (above or below) the first common electrode 116, and the first light-shielding layer is used to shield the partially overlapping portion of the two adjacent color resistance portions at their junction and the color deviation of the two adjacent color filter layers 111, and the material of the first light-shielding layer is metal and / or metal oxide.

[0054] By arranging the first light-shielding strip 115 whose length direction is perpendicular to the length direction of the gate line of the control device layer and the second light-shielding strip 122 whose length direction is parallel to the length direction of the gate line on the thin film transistor array substrate, and the first light-shielding strip 115 and the second light-shielding strip 122 are both made of metal and / or metal oxide, the first light-shielding strip 115 and the second light-shielding strip 122 can be directly used to block the partially overlapping portion of two adjacent color-blocking portions at their junction and the gate line of the thin film transistor array substrate, thereby effectively improving the accuracy of the first light-shielding strip 115 and the second light-shielding strip 122 in blocking the gate line of the thin film transistor array substrate and the partially overlapping portion of two adjacent color-blocking portions at their junction, thereby avoiding serious product yield problems caused by alignment errors between the thin film transistor array substrate and the opposing substrate.

[0055] Since the first light-shielding layer is made of metal and / or metal oxide, its line width can be made smaller and the line width uniformity is improved, which is of great help in improving the aperture ratio of the display panel and the display quality.

[0056] The large viewing angle color deviation of the display panel is strongly related to the first light shielding layer located on the original opposing substrate side. In the present application, since the first light shielding layer and the color filter layer 111 are arranged in the thin film transistor array substrate, the color deviation is greatly improved.

[0057] Because the color filter layer 111 and the first light-shielding layer are both disposed on the thin-film transistor array substrate, the formation processes of the color filter layer 111 and the first light-shielding layer are both self-aligned within the same machine. This significantly improves the alignment accuracy compared to conventional processes that align the thin-film transistor array substrate with the color filter substrate on which the color filter layer 111 is disposed. Specifically, because the color filter layer 111 and the first light-shielding layer are both formed within the same machine, the effects of misalignment between the thin-film transistor array substrate and the color filter substrate can be avoided, thereby improving process accuracy and product yield.

[0058] Since the first light-shielding layer is arranged in the thin film transistor array substrate and the material of the first light-shielding layer is metal and / or metal oxide, the line width of the first light-shielding layer can be made smaller and more precise, thereby improving the aperture ratio of the pixels of the display panel.

[0059] The large viewing angle color deviation of the display panel is strongly related to the first light-shielding layer located in the original color filter substrate. The present application transfers the first light-shielding layer and the color filter layer 111 to the thin film transistor array substrate, and uses thinner materials to effectively reduce the optical path difference, thereby improving the large viewing angle color deviation and reducing the risk of large viewing angle color deviation.

[0060] like Figure 3 and Figure 4 As shown, the second embodiment of the display panel provided in this application is similar to the first embodiment described above, except that:

[0061] A second light-shielding layer is provided in the opposing substrate. That is, the color filter layer 111 and the first light-shielding layer of the display panel are provided in the thin-film transistor array substrate, while the second light-shielding layer 202 of the display panel is provided in the opposing substrate. The light-shielding range of the first light-shielding layer is different from the light-shielding range of the second light-shielding layer. For example, the light-shielding range of the first light-shielding layer is outside the light-shielding range of the second light-shielding layer.

[0062] Since the display panel of the VR product adopts a structure in which the common electrode is located on the pixel electrode 113, in order to prevent the end portion of the common electrode's slit 1161 from being blocked by the second light-shielding layer 202, resulting in the end portion of the common electrode's slit 1161 being shielded, the length of the common electrode's slit 1161 is reduced from a to b in disguise, thereby causing a loss of transmittance of the display panel of the VR product. In this embodiment, in the length direction of the gate line, the second light-shielding layer 202 is arranged in the opposing substrate and is made of resin. Therefore, the end portion of the common electrode's slit 1161 will not be shielded, and the length of the common electrode's slit 1161 remains a.

[0063] The counter substrate includes a second substrate 201, a second light-shielding layer 202 (resin light-shielding layer), and a support member 203. In the counter substrate, the second light-shielding layer 202 is disposed on the second substrate 201, and the support member 203 is disposed on the second light-shielding layer 202. The end of the support member 203 closest to the second substrate 201 abuts against the second light-shielding layer 202. The second light-shielding layer 202 is a resin layer made of conventional resin, and its thickness is greater than or equal to that of the first light-shielding layer. In particular, the thickness of the second light-shielding layer is 10,000 angstroms to 30,000 angstroms. For example, the thickness of the second light-shielding layer 202 is 10,000 angstroms, 12,000 angstroms, 14,000 angstroms, 16,000 angstroms, 18,000 angstroms, 20,000 angstroms, 22,000 angstroms, 24,000 angstroms, 26,000 angstroms, 28,000 angstroms, or 30,000 angstroms.

[0064] The first light shielding layer includes at least two third light shielding strips, and the overlapping portion of two adjacent color resist portions is located within the light shielding range of the third light shielding strips. The length direction of the third light shielding strips is perpendicular to the length direction of the gate lines of the control device layer.

[0065] The second light-shielding layer 202 is used to shield the display panel from dark electric fields and metal traces along the lengthwise direction of the gate lines. The gate lines in the thin-film transistor array substrate are located within the light-shielding range of the second light-shielding layer 202. Specifically, the second light-shielding layer includes at least two fourth light-shielding strips, and the gate lines of the control device layer are located within the light-shielding range of the fourth light-shielding strips. The lengthwise direction of the fourth light-shielding strips is parallel to the lengthwise direction of the gate lines.

[0066] The groove is located within the light-shielding range of the fourth light-shielding strip. The length direction of the first groove 121 is parallel to the length direction of the second light-shielding layer 202. The first groove 121 and the second groove 120 are located within the light-shielding range of the second light-shielding layer 202, and the length direction of the second groove 120 is parallel to the length direction of the first groove 121.

[0067] like Figure 3 As shown, in this embodiment, at least a portion of the first light-shielding layer is in the shape of an elongated strip, and the straight line corresponding to the elongated portion of the first light-shielding layer is perpendicular to the length direction of the gate line. At least a portion of the second light-shielding layer 202 is in the shape of an elongated strip, and the straight line corresponding to the elongated portion of the second light-shielding layer 202 is parallel to the length direction of the gate line. For example, the first light-shielding strip 115 is in the shape of an elongated strip and extends in a direction perpendicular to the length direction of the gate line, and the second light-shielding strip 122 is in the shape of an elongated strip and extends in the length direction of the gate line.

[0068] Since the second light-shielding strips 122 are transferred to the opposite substrate and are made of resin, the second light-shielding strips 122 made of resin will not shield the electric field region of the common electrode.

[0069] like Figure 5 As shown, the third embodiment of the display panel provided in this application is similar to the first embodiment described above, and the fourth embodiment is similar to the second embodiment, except that:

[0070] A second common electrode 118 and a second passivation layer 119 are arranged between the first planarization layer and the first passivation layer. The second common electrode 118 is arranged on the first planarization layer 112. A portion of the second passivation layer 119 is arranged between the second common electrode 118 and the pixel electrode 113, and another portion of the second passivation layer 119 is arranged between the second common electrode 118 and the first passivation layer 114.

[0071] That is, the display panel further includes a second common electrode 118 and a second passivation layer 119. The second common electrode 118 is disposed on the first planarization layer 112, the second passivation layer 119 is disposed on the second common electrode 118, the pixel electrode 113 is disposed on the second passivation layer 119, the first passivation layer 114 is disposed on the second passivation layer 119, and the first passivation layer 114 covers the pixel electrode 113. The first common electrode 116 is disposed on the first passivation layer 114. Since the pixel electrode 113 is disposed between the first common electrode 116 and the second common electrode 118, the capacitance of the capacitor formed by the pixel electrode 113 and the common electrodes can be increased.

[0072] The second common electrode 118 and the second passivation layer 119 are disconnected at the first groove.

[0073] The second common electrode 118 is made of ITO.

[0074] As an improvement, a metal bridge portion is added between the first common electrode 116 and the second common electrode 118 . The material of the metal bridge portion is ITO, and the cross-sectional areas of the metal bridge portion in different areas of the display panel are different.

[0075] As another improvement, a switching transistor is added to the display panel, the source of the switching transistor is connected to an adjustment voltage output end, and the adjustment voltage output end can be, for example, one end of the data line. The drain of the switching transistor is connected to the first common electrode 116 or the second common electrode 118, and the gate of the switching transistor is connected to a control signal output end. By controlling the switching state of the switching transistor to adjust the capacitive coupling effect between the first and second common electrodes, the response speed of the liquid crystal molecules in the liquid crystal layer can be improved.

[0076] As another improvement, multiple micropores are laser-drilled in the first common electrode 116 and the second common electrode 118. By adjusting the diameter and density of each micropore, the capacitive coupling effect between the first common electrode 116 and the second common electrode 118 is controlled, thereby optimizing the charging uniformity and response speed of the liquid crystal molecules in the display panel. The diameter of the micropores is 0.5 to 2 microns, for example, 0.5 microns, 0.7 microns, 0.9 microns, 1.1 microns, 1.3 microns, 1.5 microns, 1.7 microns, 1.9 microns, and 2.0 microns. This can generate a certain degree of capacitive coupling to accelerate the response speed of the local liquid crystal, while meeting the requirements of fast and uniform pixel charging.

[0077] Since the gate line is shielded by the second light shielding layer 202 , the dark area caused by the electric field area of ​​the gate line can be prevented from appearing.

[0078] The display panel provided by the present application adopts a technical solution of transferring the color filter layer 111 and the light shielding layer to the thin film transistor array substrate, which can effectively improve the problem of low yield of the display panel and severe color shift at large viewing angles caused by large alignment accuracy errors in high pixel density display panels in the prior art. In the display panel provided by the present application, firstly, by transferring the color filter layer 111 and the first light shielding layer to the thin film transistor array substrate, the formation processes of the color filter layer 111 and the first light shielding layer can be accurately self-aligned in the same machine. Compared with the solution of aligning the thin film transistor array substrate and the color filter substrate provided with the color filter layer 111, the alignment accuracy can be greatly improved. At the same time, by transferring the color filter layer 111 and the first light shielding layer to the thin film transistor array substrate, the influence of the alignment error between the thin film transistor array substrate and the opposing substrate in the longitudinal direction of the gate line on the product yield can be eliminated, thereby improving the product yield. Secondly, because the dimensional accuracy of the components made of metal or metal oxide materials formed by the mask process and etching process is greater than that of the components made by the mask process, the dimensional accuracy of the components made of metal or metal oxide materials is greater than that of the components made by the mask process. and the dimensional accuracy of the parts made of resin by the etching process, therefore, in the present application, the first light-shielding layer is made of metal or metal oxide material, which can make the shape and size of the first light-shielding layer more consistent with the shape and size of the light-transmitting hole of the mask template, and the line width of the first light-shielding layer is smaller and the line width uniformity is higher, so that the opening of the pixel is larger, thereby increasing the aperture ratio and improving the display quality of the display panel; thirdly, since the color filter layer 111 and the first light-shielding layer are transferred to the thin film transistor array substrate, the optical path difference can be reduced, thereby reducing the optical path difference that light needs to pass through the display panel under different viewing angles, reducing color deviation under large viewing angles, and expanding the viewing angle range; finally, since the gate line is shielded by the second light-shielding layer 202, the dark area caused by the electric field region of the gate line can be prevented from appearing.

[0079] The above describes the specific embodiments of the present application in detail. The above specific embodiments disclosed in this specification are merely preferred embodiments of the present application and are not intended to limit the scope of the present application. Those skilled in the art will appreciate that many variations and improvements can be made without departing from the spirit of the present application. Such variations and improvements fall within the scope of protection defined by the claims of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a thin film transistor array substrate, a liquid crystal layer and an opposite substrate, wherein the liquid crystal layer is arranged between the thin film transistor array substrate and the opposite substrate; The thin film transistor array substrate comprises: a control device layer, the control device layer comprising a plurality of control devices; a color filter layer, the color filter layer being disposed on the control device layer, the color filter layer comprising a plurality of color resist portions of different colors, wherein two adjacent color resist portions of different colors partially overlap; a first planarization layer, the first planarization layer being disposed on a surface of the color filter layer close to the opposing substrate; a first passivation layer, the first passivation layer being disposed on the first planarization layer; a pixel electrode, the pixel electrode being disposed between the first planarization layer and the first passivation layer; a first common electrode, the first common electrode being disposed on the first passivation layer; and a first light-shielding layer, the first light-shielding layer being disposed on a surface of the first common electrode close to or away from the counter substrate, the first light-shielding layer at least covering a portion where two adjacent color-resist portions of different colors overlap; In a direction perpendicular to the length direction of the gate line, a first groove is provided between two adjacent color resist portions, and the length direction of the first groove is parallel to the length direction of the gate line; A second groove is provided on the first planarization layer, and the second groove is sleeved in the first groove; A portion of the pixel electrode is disposed in the first groove and electrically connected to the control device; A portion of the first passivation layer is disposed on a surface of a portion of the pixel electrode located in the first groove; A second common electrode and a second passivation layer are provided between the first planarization layer and the first passivation layer, the second common electrode is provided on the first planarization layer, a portion of the second passivation layer is provided between the second common electrode and the pixel electrode, and another portion of the second passivation layer is provided between the second common electrode and the first passivation layer; The second common electrode and the second passivation layer are disconnected at the first groove.

2. The display panel according to claim 1, wherein A second light-shielding layer is provided in the counter substrate, and a light-shielding range of the first light-shielding layer is different from a light-shielding range of the second light-shielding layer.

3. The display panel according to claim 2, wherein: The control device layer further includes a plurality of gate lines, the first light shielding layer includes a plurality of first light shielding strips parallel to each other, and the length direction of the first light shielding strips is perpendicular to the length direction of the gate lines; The second light-shielding layer includes a plurality of second light-shielding strips parallel to each other, and the length direction of the second light-shielding strips is parallel to the length direction of the gate lines.

4. The display panel according to claim 3, wherein: The width of the first light-shielding strip is smaller than the width of the second light-shielding strip.

5. The display panel according to claim 3, wherein: The edge of the color resist portion is located within the light-shielding range of the first light-shielding strip, and the gate line is located within the light-shielding range of the second light-shielding strip.

6. The display panel according to claim 2, wherein: The thickness of the first light shielding layer is 700 angstroms to 2000 angstroms, and the thickness of the second light shielding layer is 10000 angstroms to 30000 angstroms.

7. The display panel according to claim 2, wherein: The first light-shielding layer is a metal layer, a metal oxide layer, or a stack of both layers, and the second light-shielding layer is a resin layer.

8. The display panel according to claim 1, wherein: A portion of the first common electrode is disposed in the second groove; The thin film transistor array substrate further includes a second planarization layer, a portion of the second planarization layer is disposed on a portion of the first common electrode located in the second groove; A support member is provided on a surface of the counter substrate close to the thin film transistor array substrate, and an end of the support member away from the counter substrate contacts the second planarization layer.

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