Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system, and the semiconductor device comprises a transistor array which comprises a plurality of semiconductor main bodies; the conductive contact structure is positioned at one end of the semiconductor main body along the first direction and is coupled with the semiconductor main body; the first direction is the extension direction of the semiconductor main body; the conductive contact structure comprises a first contact structure and a second contact structure; the first contact structure comprises a first metal layer, and the second contact structure comprises a second metal layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor device, a manufacturing method thereof, and a memory system. BACKGROUND

[0002] Semiconductor devices, such as dynamic random access memory (DRAM), are one of the most important access components in electronic systems, and usually adopt a transistor and a capacitor to form a 1T1C structure as a memory cell. The 1T1C structure makes the dynamic random access memory have high integration and low cost, and has an irreplaceable position in computer access devices. With the rapid development of semiconductor technology, dynamic random access memory is rapidly developing towards high density and high quality. SUMMARY

[0003] Embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and a memory system.

[0004] In a first aspect, embodiments of the present disclosure provide a semiconductor device, including: a transistor array including a plurality of semiconductor bodies; a conductive contact structure, the conductive contact structure being located at one end of the semiconductor body along a first direction and coupled with the semiconductor body; the first direction being an extension direction of the semiconductor body; the conductive contact structure including a first contact structure and a second contact structure; the first contact structure including a first metal layer, and the second contact structure including a second metal layer.

[0005] In an optional implementation, the first metal layer and the second metal layer are made of the same material.

[0006] In an optional implementation, a thickness of the second metal layer in the first direction is greater than a thickness of the first metal layer in the first direction.

[0007] In an optional implementation, a thickness of the first metal layer in the first direction is less than 20 nm.

[0008] In an optional implementation, a thickness of the second metal layer in the first direction is greater than 50 nm.

[0009] In an optional implementation, the first contact structure further includes a first semiconductor layer, a first conductive layer, and a first contact layer; the first semiconductor layer, the first conductive layer, the first contact layer, and the first metal layer are sequentially stacked along the first direction; the first semiconductor layer is in contact with the semiconductor body, and the first metal layer is in contact with the second contact structure.

[0010] In an optional implementation, the second contact structure further includes a second contact layer, the second contact layer being located at least between the first metal layer and the second metal layer.

[0011] In an optional implementation, the method further includes: forming a plurality of storage capacitors, each storage capacitor being coupled to the semiconductor body through the conductive contact structure.

[0012] In an optional implementation, the first contact structure is in contact with the semiconductor body, and the second contact structure is in contact with the storage capacitor.

[0013] In an optional implementation, the first contact layer and the second contact layer are made of the same material.

[0014] In an optional implementation, the method further includes:

[0015] An alignment mark, the alignment mark being disposed in the transistor array.

[0016] In a second aspect, the embodiments of the present disclosure provide a method for manufacturing a semiconductor device, the method comprising: providing a transistor array, the transistor array comprising a plurality of semiconductor bodies; sequentially forming a to-be-etched stack and a conductive mask layer on the transistor array; etching the to-be-etched stack using the conductive mask layer to form a first contact structure; and retaining the conductive mask layer on the first contact structure to form a second contact structure.

[0017] In an optional implementation, the first contact structure includes a first metal layer; and the conductive mask layer includes a second metal layer.

[0018] In an optional implementation, the first metal layer and the second metal layer are made of the same material.

[0019] In an optional implementation, a thickness of the second metal layer in a first direction is greater than a thickness of the first metal layer in the first direction; the first direction being an extension direction of the semiconductor body.

[0020] In an optional implementation, the thickness of the first metal layer in the first direction is less than 20 nm.

[0021] In an optional implementation, the thickness of the second metal layer in the first direction is greater than 50 nm.

[0022] In an optional implementation, the to-be-etched stack is formed by:

[0023] The first semiconductor layer, the first conductive layer, the first contact layer, and the first metal layer are sequentially formed on the transistor array.

[0024] In an optional embodiment, alignment marks are provided in the transistor array; the conductive mask layer is formed by: forming a first mask layer and a photoresist layer on the layer to be etched; taking the alignment marks as a reference, forming a patterned photoresist layer; taking the patterned photoresist layer as a mask, forming a contact hole in the first mask layer by a self-aligned double patterning (SADP) process; and forming the conductive mask layer in the contact hole.

[0025] In an optional embodiment, the conductive mask layer is formed in the contact hole by: sequentially forming a second contact layer and a second metal layer in the contact hole, the second contact layer covering the bottom and sidewall of the contact hole; and the second metal layer filling the contact hole; and removing the first mask layer to form the conductive mask layer.

[0026] In an optional embodiment, the first contact structure and the second contact structure form a conductive contact structure, and the method further comprises: depositing an insulating material to form an insulating structure between the conductive contact structures; and the surface of the insulating structure is flush with the surface of the conductive contact structure.

[0027] In an optional embodiment, the method further comprises: forming a storage capacitor coupled to the contact structure, the storage capacitor being coupled to the semiconductor body through the first contact structure and the second contact structure.

[0028] In a second aspect, the embodiments of the present disclosure provide a memory system, comprising: the semiconductor device according to any one of the first aspect; and a memory controller connected to the semiconductor device and configured to control the semiconductor device.

[0029] The embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and a memory system. The semiconductor device comprises: a transistor array comprising a plurality of semiconductor bodies; a conductive contact structure located at one end of the semiconductor body along a first direction and coupled to the semiconductor body; the first direction is the extension direction of the semiconductor body; the conductive contact structure comprises a first contact structure and a second contact structure; the first contact structure comprises a first metal layer, and the second contact structure comprises a second metal layer. The conductive contact structure in the embodiments of the present disclosure is composed of two parts, each part has a metal layer for realizing conductive connection, thereby increasing the thickness of the conductive contact structure in the first direction, and improving the landing window of the subsequent etching process. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A structure diagram of a semiconductor device provided by the embodiments of the present disclosure Figure 1 ;

[0031] Figure 2 A flowchart of a manufacturing method of a semiconductor device provided by the embodiments of the present disclosure

[0032] Figures 3a to 3d A cross-sectional view of a process for forming a transistor array according to an embodiment of the present disclosure;

[0033] Figures 4a to 4e A cross-sectional view of a process for forming a conductive contact structure according to an embodiment of the present disclosure;

[0034] Figure 5 A structure of a semiconductor device according to an embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present disclosure will be clearly and completely described with reference to the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present disclosure.

[0036] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present disclosure, some technical features known in the art are not described; that is, not all features of the actual embodiments are described here, and well-known functions and structures are not described in detail.

[0037] In the drawings, the sizes of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference signs represent the same elements throughout.

[0038] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0039] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0042] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements of dynamic random access memory for ions and leakage current, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0043] In some embodiments of this disclosure, whether planar transistors or buried transistors, the dynamic random access memory is composed of multiple memory cells. Each memory cell consists of a transistor and a capacitor controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0044] The following is combined Figure 1 One architecture of dynamic random access memory is described in detail. In the introduction... Figure 1 Before illustrating the semiconductor device, we first define the various directions that may be used in the following description. The extension direction of the semiconductor body is defined as the first direction (i.e., the Z-axis direction). In a plane perpendicular to the Z-axis direction, we define the intersecting second direction (i.e., the X-axis direction) and the third direction (i.e., the Y-axis direction). In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction can be mutually perpendicular.

[0045] A cross-sectional view of a semiconductor device 100 including a vertical transistor is provided in this embodiment of the disclosure; as shown... Figure 1As shown, the semiconductor device 100 includes a second semiconductor structure 102 and a first semiconductor structure 104 stacked on the second semiconductor structure 102 along a Z-axis direction, the second semiconductor structure 102 and the first semiconductor structure 104 are connected through a bonding interface 106; the second semiconductor structure 102 and the first semiconductor structure 104 can be connected through hybrid bonding or the like. In some embodiments, the first semiconductor structure 104 can be bonded on the top of the second semiconductor structure 102 in a face-to-face manner at the bonding interface 106. The second semiconductor structure 102 can include a first substrate 1010, a peripheral circuit 1012 located on one side of the first substrate 1010, and a first interconnection layer 1016 located on the side of the peripheral circuit 1012 away from the first substrate 1010, the first interconnection layer 1016 is used to transmit electrical signals of the peripheral circuit 1012. The peripheral circuit 1012 can include a plurality of transistors 1014. In some embodiments, trench isolation (such as shallow trench isolation STI) and doped regions (such as wells, sources and drains of the transistors 1014) can also be formed on or in the first substrate 1010.

[0046] The second semiconductor structure 102 can also include a first bonding layer 1018 at the bonding interface 106 and located on the side of the first interconnection layer 1016 away from the peripheral circuit 1012. The first bonding layer 1018 can include a plurality of first bonding contacts 1019 and a dielectric electrically isolating the first bonding contacts 1019. The first bonding contacts 1019 and the surrounding dielectric in the first bonding layer 1018 can be used for hybrid bonding. Conversely, the first semiconductor structure 104 can also include a second bonding layer 1020 at the bonding interface 106 and located on the side of the first bonding layer 1018 away from the first interconnection layer 1016. The second bonding layer 1020 can include a plurality of second bonding contacts 1021 and a dielectric electrically isolating the second bonding contacts 1021. The second bonding contacts 1021 and the surrounding dielectric in the second bonding layer 1020 can be used for hybrid bonding. Here, the second bonding contacts 1021 contact the first bonding contacts 1019 at the bonding interface 106.

[0047] In some embodiments, the peripheral circuitry 1012 may further include word lines (WL) and word line drivers / row decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. In other embodiments, the peripheral circuitry 1012 may further include bit lines 1023 (BL) and bit line drivers / column decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. Here, the second interconnect layer 1022 includes bit lines 1023 above the second bonding layer 1020, and the bit lines 1023 are used to transmit electrical signals. In other embodiments, the stacked second semiconductor structure 102 and the first semiconductor structure 104 may not be connected by bonding, but rather integrated on the same substrate (only the first substrate, no second substrate), and directly connected through one or more interconnect layers between the second semiconductor structure 102 and the first semiconductor structure 104. In this case, the second semiconductor structure 102 does not have the first bonding layer 1018 and the first bonding contact 1019; the first semiconductor structure 104 does not have the second bonding layer 1020 and the second bonding contact 1019; and the bonding interface 106 between the second semiconductor structure 102 and the first semiconductor structure 104 also does not exist.

[0048] refer to Figure 1 The first semiconductor structure 104 further includes a memory cell array located on the second interconnect layer 1022. The memory cell array may include a plurality of memory cells 1024 arranged in an array along the X-axis and Y-axis directions, a second substrate 1048 located on the memory cells 1024, and a third interconnect layer 1050 located on the second substrate 1048. Figure 1 The cross section of the dynamic random access memory 100 can be cut along the bit line direction (X-axis direction), and a bit line 1023 in the second interconnect layer 1022 extending in the X-axis direction can be coupled to a column of memory cells 1024.

[0049] Here, each memory cell 1024 may include a vertical transistor 1026 and a capacitor structure 1028 coupled to the vertical transistor 1026; the vertical transistor 1026 includes a semiconductor body 1030 extending vertically (in the Z-axis direction) and a gate structure 1036 contacting at least a portion of the side surface of the semiconductor body 1030 in the bit line direction (X-axis direction); in other embodiments, the gate structure may also completely surround the semiconductor body, partially surround the semiconductor body, or be located on two opposite sides of the semiconductor body, etc., which will not be elaborated here. Here, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 located between the gate electrode 1034 and the semiconductor body 1030 in the bit line direction (X-axis direction). In some embodiments, the gate dielectric 1032 is adjacent to one side surface of the semiconductor body 1030, and the gate electrode 1034 is adjacent to the gate dielectric 1032.

[0050] In some embodiments, the semiconductor body 1030 has two ends (upper end and lower end) in the vertical direction (Z-axis direction), and one end (e.g. Figure 1 The lower end of the semiconductor body 1030 extends in the vertical direction (Z-axis direction) beyond the gate dielectric 1032 into the interlayer dielectric (ILD) layer, while the other end of the semiconductor body 1030 (such as...) Figure 1 The upper end of the semiconductor body 1030 is flush with the corresponding end of the gate dielectric 1032. In other embodiments, both ends (upper and lower) of the semiconductor body 1030 extend in the vertical direction (Z-axis direction) beyond the gate electrode 1034 into the ILD layer. In other words, the semiconductor body 1030 may have a larger vertical dimension than the vertical dimension (e.g., depth in the Z-axis direction) of the gate electrode 1034, and neither the upper nor lower end of the semiconductor body 1030 is flush with the corresponding end of the gate electrode 1034. This avoids short circuits between the bit line 1023 and the word line / gate electrode 1034 or between the word line / gate electrode 1034 and the capacitor structure 1028.

[0051] The vertical transistor 1026 may further include a source 1038 and a drain 1040 respectively disposed at both ends (upper and lower ends) of the semiconductor body 1030 in the vertical direction (Z-axis direction). (The positions of the source and drain can be interchanged; here and below, the upper end is the source 1038 and the lower end is the drain 1040 as an example.) In some embodiments, the source 1038 is coupled to the capacitor 1028, and the drain 1040 is coupled to the bit line 1023.

[0052] Since the gate electrode can be part of a word line or extend as a word line in the word line direction, the first semiconductor structure 104 of the dynamic random access memory 100 can also include multiple word lines, each extending in the word line direction (Y-axis direction). Here, each word line 1034 can be coupled to a row of memory cells 1024.

[0053] Vertical transistor 1026 extends vertically through and contacts word line 1034, and its drain 1040 at its lower end contacts bit line 1023. Therefore, due to the vertical arrangement of vertical transistor 1026, word line 1034 and bit line 1023 can be arranged in different planes in the vertical direction, simplifying the wiring of word line 1034 and bit line 1023. Here, vertical transistor 1026 can be arranged in a mirror-symmetric manner to increase the density of memory cells 1024 in the bit line direction (X-axis direction). Two adjacent vertical transistors 1026 in the bit line direction are mirror-symmetric with respect to the first isolation structure 1060; that is, the first semiconductor structure 104 may include a plurality of first isolation structures 1060, each extending parallel to word line 1034 in the word line direction (Y-axis direction) and disposed between semiconductor bodies 1030 of two adjacent rows of vertical transistor 1026. In some embodiments, the rows of vertical transistors 1026 separated by the first isolation structure 1060 are mirror-symmetrical to each other with respect to the first isolation structure 1060. It should be understood that the first isolation structure 1060 may include air gaps, each air gap being laterally disposed between adjacent semiconductor bodies 1030. The first semiconductor structure 104 also includes a plurality of second isolation structures 1062, each second isolation structure 1062 extending parallel to the word line 1034 in the word line direction (Y-axis direction) and disposed between the word lines 1034 of two adjacent rows of vertical transistors 1026. It should be understood that the dimensions of the second isolation structure 1062 and word line 1034 in the bit line direction (X-axis direction) may be the same as or different from the dimensions of the first isolation structure 1060 in the bit line direction (X-axis direction). When the dimensions of the two in the bit line direction (X-axis direction) are different, the spacing between the multiple semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) is different, that is, the multiple semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) are not uniformly arranged.

[0054] like Figure 1 As shown, the capacitor structure 1028 is located above and in contact with the source 1038 (i.e., the upper end of the semiconductor body 1030) of the vertical transistor 1026. The capacitor structure 1028 can be a vertical capacitor.

[0055] In some embodiments, a contact structure 1064 is formed between the capacitor structure 1028 and the vertical transistor 1026 to reduce contact resistance. For example... Figure 1 As shown, the contact structure 1064 may include a first conductive layer and a second conductive layer stacked sequentially from bottom to top. The first conductive layer includes a metal semiconductor compound, and the second conductive layer includes a metal. Figure 1 As shown, the first semiconductor structure 104 may further include a capacitor contact 1047 that contacts a common plate of the second electrode for coupling the second electrode of the capacitor structure 1028 to the peripheral circuit 1012 or directly to ground. In some embodiments, the ILD layer forming the capacitor structure 1028 has the same dielectric material, such as silicon oxide, as the two ILD layers into which the semiconductor body 1030 extends. The construction of the capacitor structure 1028 may include any suitable structure and construction, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-planar capacitor.

[0056] like Figure 2 As shown, the vertical transistor 1026 extends vertically through and contacts the word line 1034. The drain 1040 at its lower end contacts the bit line 1023, and the source 1038 at its upper end contacts the capacitor structure 1028. That is, due to the vertical arrangement of the vertical transistor 1026, the bit line 1023 and the capacitor structure 1028 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 1026 of the memory cell 1024. In some embodiments, the bit line 1023 and the capacitor structure 1028 are arranged on opposite sides of the vertical transistor 1026 in the vertical direction. Compared to conventional memory cells where the bit line and capacitor structure are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 1023 and reduces the coupling capacitance between the bit line 1023 and the capacitor structure 1028.

[0057] In some embodiments, the vertical transistor 1026 is vertically disposed between the capacitor structure 1028 and the bonding interface 106. That is, the vertical transistor 1026 can be arranged closer to the peripheral circuitry 1012 and the bonding interface 106 of the second semiconductor structure 102 than the capacitor structure 1028. Since the bit line 1023 and the capacitor structure 1028 are coupled to opposite ends of the vertical transistor 1026, the bit line 1023 (as part of the second interconnect layer 1022) is vertically disposed between the vertical transistor 1026 and the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0058] In some embodiments, the first semiconductor structure 104 further includes a second substrate 1048 disposed above the memory cell 1024, and a third interconnect layer 1050 with pads leading out above the memory cell 1024. The third interconnect layer 1050 with pads leading out may include interconnects in one or more ILD layers, such as contact pads 1054.

[0059] In some embodiments, the first semiconductor structure 104 further includes one or more contacts 1052 extending through a portion of the third interconnect layer 1050 and a second substrate 1048 to couple the pads out of the third interconnect layer 1050 to the memory cell 1024 and the second interconnect layer 1022. Thus, the peripheral circuitry 1012 can be coupled to the memory cell 1024 via the first interconnect layer 1016 and the second interconnect layer 1022, as well as the second bonding layer 1020 and the first bonding layer 1018, and the peripheral circuitry 1012 and the memory cell 1024 can be coupled to external circuitry via the contacts 1052 and the pads out of the third interconnect layer 1050.

[0060] As mentioned above, in order to reduce the contact resistance between the capacitor structure 1028 and the vertical transistor 1026, a contact structure 1064 is provided between the capacitor structure 1028 and the vertical transistor 1026.

[0061] This disclosure provides a method for fabricating a semiconductor device. (See also...) Figure 2 , Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure; the method includes:

[0062] Step S201: Provide a transistor array, the transistor array comprising a plurality of semiconductor bodies;

[0063] Step S202: Sequentially form the stack to be etched and the conductive mask layer on the transistor array;

[0064] Step S203: Use a conductive mask layer to etch the stack to be etched to form the first contact structure;

[0065] Step S204: Retain the conductive mask layer on the first contact structure to form the second contact structure.

[0066] It should be understood that Figure 2 The steps shown are not exclusive, and other steps may be performed before, after, or between any step in the shown manufacturing method; Figure 1 The steps shown can be adjusted in order according to actual needs.

[0067] In some embodiments, the first contact structure and the second contact structure constitute a conductive contact structure.

[0068] It should be noted that a semiconductor device may include a conductive contact structure, a semiconductor body and a storage capacitor, or multiple conductive contact structures, multiple semiconductor bodies and multiple storage capacitors. Here and below, the example is a semiconductor device that includes multiple conductive contact structures, multiple semiconductor bodies and multiple storage capacitors.

[0069] As mentioned earlier, there can be various relative positions between the gate structure and the semiconductor body in a semiconductor device, and different relative positions correspond to different specific fabrication methods. In this embodiment of the present disclosure, two gate structures corresponding to two adjacent semiconductor bodies are respectively arranged back-to-back. Figures 3a to 3d The example shown is a back-to-back arrangement. Based on this, a semiconductor device may include multiple contact structures, multiple semiconductor bodies, and multiple storage capacitors arranged in an array along the X-axis and Y-axis directions. However, it should be understood that the following methods for forming semiconductor structures are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0070] There are various methods for forming contact structures and semiconductor bodies. Several methods are illustrated by way of example in the embodiments of this disclosure. The formation process of multiple contact structures and multiple semiconductor bodies will be described in detail below with reference to the accompanying drawings.

[0071] Figure 3c This is a cross-sectional schematic diagram illustrating the process of forming a transistor array according to an embodiment of this disclosure. It should be noted that... Figure 3b for Figure 3a A cross-sectional schematic diagram along the AA' direction is shown below; the formation process of multiple transistor arrays is described in detail below with reference to the accompanying drawings.

[0072] refer to Figure 3b A substrate 300 is provided, the material of which may be a semiconductor material, such as silicon; more specifically, the material of the substrate 300 may be monocrystalline silicon.

[0073] refer to Figure 3c , Figure 3b A plurality of semiconductor bodies 310 arranged in an array are formed in a substrate 300. In some embodiments, the formation of the semiconductor bodies 310 may include: first forming a plurality of trenches extending along the X-axis in the substrate 300, filling the trenches with an insulating material (such as silicon oxide), and then forming a plurality of trenches extending along the Y-axis in the substrate 300, wherein the trenches extending along the Y-axis are adjusted according to the relative position between the gate structure and the semiconductor bodies. Figure 3c The diagram shows that when two gate structures corresponding to two adjacent semiconductor bodies are arranged back to back, the trenches extending along the Y-axis include alternately arranged trenches of different sizes. The remaining insulating material that was previously used to fill the trenches is removed, thus forming an array of semiconductor bodies 310.

[0074] It should be noted that, Figure 3d The initial semiconductor body shown in the figure has a square shape in the cross section along the X and Y axes. This shape is only for example and is not intended to limit the shape of the semiconductor body in this cross section. The shape of the semiconductor body in this cross section may also include circles, ellipses, and approximate shapes of these shapes.

[0075] In other embodiments, the method of forming the semiconductor body 310 may also include: first forming a plurality of trenches extending along the Y-axis in the substrate 300, filling the trenches with an insulating material (such as silicon oxide), and then forming a plurality of trenches extending along the X-axis in the substrate 300.

[0076] In some specific embodiments, trenches along the X-axis and / or Y-axis can be formed by photolithography (here and hereinafter, this can be understood as lithography-etching (LE)). Methods for filling the trenches with insulating material include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0077] Next, refer to Figure 1 Based on the requirements of subsequent semiconductor device manufacturing processes, a first isolation structure 320 and a second isolation structure 330 are formed in trenches extending along the Y-axis to form a transistor array 340. It can be understood that the first isolation structure 3020 here is similar to... Figure 1 The first isolation structure 1060 serves a similar function to the second isolation structure 3030. Figure 3d The role of the second isolation structure 1062 in the middle.

[0078] In some embodiments, such as Figure 3d As shown, the first isolation structure 3020 may include an isolation layer 321 and a capping layer 322, wherein the isolation layer 321 may include an air gap, such as air; the material of the capping layer 322 includes, but is not limited to, silicon oxide. In other embodiments, the first isolation structure 320 may also include a conductive material layer and a protective layer (…). Figure 3d(Not shown in the diagram), the conductive material layer can provide good electrostatic shielding. However, it should be noted that when the first isolation structure 3020 includes a conductive material layer, the protective layer must surround the conductive material layer to prevent the conductive material layer from contacting the semiconductor substrate. In some specific embodiments, the methods for forming the first isolation structure 3020 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD) processes.

[0079] In some embodiments, such as Figure 3a As shown, the second isolation structure 330 may include a gate structure 331 and a dielectric layer 332 surrounding the gate structure. The gate structure 331 may include a gate electrode and a gate dielectric. Optionally, the gate structure 331 may further include a barrier layer located between the gate electrode and the gate dielectric. The material of the gate electrode may include, but is not limited to, tungsten; the material of the gate dielectric may include, but is not limited to, silicon oxide; and the material of the barrier layer may include, but is not limited to, titanium nitride. Exemplarily, the dielectric layer 332 is made of silicon oxide. In some specific embodiments, the method for forming the gate structure 331 in the second isolation structure 330 includes, but is not limited to, deposition, etching, and other processes; the method for forming the dielectric layer 332 in the second isolation structure 330 includes, but is not limited to, deposition, etching, CMP, and other processes.

[0080] It should be noted that, from the appendix Figures 4a to 4e The cross-sectional diagrams shown later in the diagrams are all intermediate stages of the manufacturing process. Some of the structural features shown in the diagrams may not be the final product form of the semiconductor device. For example, the lower ends of the word lines (gate electrodes) shown in the diagram are connected together, while in the final product of the semiconductor device, the lower ends of the word lines (gate electrodes) are disconnected, forming a back-to-back structure.

[0081] Figure 4a This is a cross-sectional schematic diagram of the process of forming a conductive contact structure according to an embodiment of the present disclosure.

[0082] refer to Figure 4b An etchable stack 350 and a first mask layer 360 are sequentially formed on the transistor array 340.

[0083] The etchable stack 350 includes a first semiconductor layer 351, a first conductive layer 352, a first contact layer 353 and a first metal layer 354 stacked sequentially from bottom to top.

[0084] In some embodiments, forming the etchable stack 350 includes: sequentially forming a first semiconductor layer 351, a first conductive layer 352, a first contact layer 353, and a first metal layer 354 on the transistor array 340.

[0085] In some embodiments, the first semiconductor layer 351 is formed by a deposition process, and the material of the first semiconductor layer 351 includes a polycrystalline material, such as polycrystalline silicon. In other embodiments, the first semiconductor layer 351 is formed by an epitaxial process, and the material of the first semiconductor layer 351 includes a monocrystalline material, such as monocrystalline silicon.

[0086] In some specific embodiments, the first conductive layer 352 comprises a metal semiconductor compound, wherein the metal element in the metal semiconductor compound includes, but is not limited to, tungsten, nickel, cobalt, or titanium. In some embodiments, the first conductive layer can be formed by metallizing the first semiconductor layer.

[0087] In some specific embodiments, forming the first conductive layer 352 includes: forming an initial metal layer covering the first semiconductor layer 351; and annealing the first semiconductor layer 351 on which the initial metal layer is formed to form the first conductive layer 352.

[0088] It should be noted that during the metallization process, the proportion of the metal semiconductor compound layer in the semiconductor material can vary depending on the degree of metallization.

[0089] In some specific embodiments, the material of the first contact layer 353 includes, but is not limited to, titanium or titanium nitride, and the method of forming the first contact layer 353 includes, but is not limited to, PVD, CVD, ALD and other processes.

[0090] In some specific embodiments, the material of the first metal layer 354 includes, but is not limited to, tungsten or copper.

[0091] refer to Figure 4c Contact holes 361 are formed in the first mask layer 360 by a self-aligned double patterning SADP process.

[0092] In some embodiments, alignment marks are provided in the transistor array 340; a photoresist layer is formed on the first mask layer; a patterned photoresist layer is formed with the alignment marks as a reference; and contact holes are formed in the first mask layer using a self-aligned double patterning (SADP) process, with the patterned photoresist layer as a mask. In the photolithography patterning process, in order to ensure accurate alignment for subsequent photolithography, alignment marks are typically provided in the previous layer. Then, with the alignment marks as a reference, the alignment marks in the photomask are aligned with the alignment marks of the previous layer to perform the photolithography process and form a patterned photoresist layer.

[0093] In this embodiment of the disclosure, since the conductive mask layer will be retained as part of the conductive contact structure, the thickness of the first metal layer can be set to be thinner, which is beneficial for photolithographic alignment with alignment marks set in the transistor array.

[0094] In some embodiments, the orthographic projections of the contact hole 361 and the semiconductor body 310 in a cross section perpendicular to the first direction overlap.

[0095] refer to Figure 4d A conductive mask layer 370 is formed inside the contact hole 361, and the first mask layer 360 is removed to form the conductive mask layer 370.

[0096] In some embodiments, the conductive mask layer 370 includes a second contact layer 371 and a second metal layer 372.

[0097] In some embodiments, forming a conductive mask layer within a contact hole includes: sequentially forming a second contact layer 371 and a second metal layer 372 within the contact hole, wherein the second contact layer 371 covers the bottom and sidewalls of the contact hole; the second metal layer 372 fills the contact hole; and removing the first mask layer 360 to form the conductive mask layer 370. It should be noted that the conductive mask layer 370 formed after removing the first mask layer 360 is a patterned conductive mask layer.

[0098] In some specific embodiments, the material of the second contact layer 371 includes, but is not limited to, titanium or titanium nitride, and the method of forming the second contact layer 371 includes, but is not limited to, PVD, CVD, ALD and other processes.

[0099] In some specific embodiments, the material of the second metal layer 372 includes, but is not limited to, tungsten or copper.

[0100] In some embodiments, the first metal layer 354 and the second metal layer 372 are made of the same material. In one example, both the first metal layer 354 and the second metal layer 372 are made of tungsten.

[0101] In one example, the second metal layer 372 is made of tungsten, and the second contact layer 371 is made of titanium nitride. The second contact layer 371 surrounding the second metal layer 372 can act as a barrier layer to prevent erosion of the first mask layer 360 during the formation of the second metal layer 372. Furthermore, the second contact layer 371 can also serve as an adhesive layer to enhance the adhesion between the second metal layer 372 and the first metal layer 354.

[0102] In some embodiments, the thickness of the second metal layer 372 in the first direction is greater than the thickness of the first metal layer 354 in the first direction.

[0103] In this embodiment of the disclosure, since the conductive mask layer will be retained as part of the conductive contact structure, the thickness of the second metal layer can be set to be thicker, thereby increasing the landing window of the subsequent etching process of the storage capacitor.

[0104] In some embodiments, the thickness of the first metal layer 354 in the first direction is less than 20 nm.

[0105] In this embodiment of the disclosure, the first metal layer can be made thinner so that the alignment marks are more visible when alignment is performed using alignment marks in the transistor array, which is beneficial for photolithographic alignment.

[0106] In some embodiments, the thickness of the second metal layer 372 in the first direction is greater than 50 nm.

[0107] In this embodiment of the disclosure, the second metal layer can be made thicker to increase the overall thickness of the conductive contact structure, thereby increasing the landing window for the subsequent etching process of the storage capacitor.

[0108] It should be noted that the thicknesses of the first and second metal layers defined here refer to the thicknesses in the final device structure.

[0109] refer to Figure 4d The conductive mask layer 370 is used to etch the stack 350 to be etched in order to form the first contact structure 380.

[0110] In some embodiments, the conductive mask layer 370 on the first contact structure 380 is retained to form the second contact structure. In other words, the conductive mask layer 370 after etching to form the first contact structure 380 is the second contact structure.

[0111] In some embodiments, reference Figure 4e The first contact structure 380 and the second contact structure (conductive mask layer 370) constitute the conductive contact structure 400.

[0112] refer to Figure 5 An insulating material is deposited to form an insulating structure 390 between the conductive contact structure 400 and the conductive contact structure 400; the surface of the insulating structure 390 is flush with the surface of the conductive contact structure 400.

[0113] In some embodiments, the method further includes: forming a storage capacitor coupled to a second contact structure, the storage capacitor being coupled to a semiconductor body through a first contact structure and a second contact structure.

[0114] In some specific embodiments, forming a storage capacitor coupled to the second contact structure includes forming a cup-shaped storage capacitor (CUP), a cylindrical storage capacitor (CYL), or a pillar-shaped storage capacitor (PIL). The shape of the storage capacitor can be selected according to actual needs, and this disclosure does not limit it.

[0115] In some embodiments, forming the first semiconductor structure further includes forming a capacitor contact coupled to a storage capacitor. The capacitor contact is coupled to a second electrode of the storage capacitor for coupling the second electrode of the storage capacitor to an external circuit or directly to ground.

[0116] In some embodiments, the method further includes forming word lines on at least one side of the semiconductor body. Here, the word lines may extend in a third direction.

[0117] In some specific embodiments, forming word lines on at least one side of the semiconductor body includes: forming word lines located on one side of the semiconductor body; or forming word lines located on two opposite sides of the semiconductor body; or forming word lines surrounding the side of the semiconductor body.

[0118] It is understood that the contact structure in this disclosure can be applied to different word line (gate structure) scenarios. For example, the contact structure in this disclosure can be applied to a scenario where two word line structures corresponding to two adjacent semiconductor bodies are arranged back-to-back. The accompanying drawings in this disclosure illustrate a back-to-back arrangement scenario.

[0119] In some embodiments, the method further includes forming a source electrode at one end corresponding to the upper surface of the semiconductor body. It should be noted that the positions of the source and drain electrodes can be interchanged; here, the upper end of the semiconductor body is taken as the source electrode and the lower end as the drain electrode for illustration.

[0120] In some embodiments, the method further includes: forming a second doped layer at an opposite end of the upper surface of the semiconductor body; and forming a bit line coupled to the second doped layer, the bit line extending along a second direction. Here, the bit line is coupled to the drain of the semiconductor body.

[0121] In some embodiments, the method further includes: forming a bit line lead-out structure coupled to a bit line.

[0122] In some embodiments, the method further includes: forming a second interconnect layer coupled to the bit line lead structure and the capacitive contacts; and forming a second bonding layer coupled to the second interconnect layer. The second bonding layer may include a plurality of second bonding contacts and a dielectric material for electrically isolating the second bonding contacts.

[0123] In this embodiment, a conductive mask layer is used as a mask to etch and form a first contact structure, while the conductive mask layer is retained as a second contact structure. This forms a conductive contact structure through the first and second contact structures. This increases the thickness of the conductive contact structure while avoiding the problem of excessive thickness of the first metal layer in the first contact structure affecting photolithographic alignment. On one hand, the increased thickness of the conductive contact structure improves the landing window for subsequent etching processes. On the other hand, because the conductive mask layer is retained as the second contact structure, the thickness of the first metal layer in the first contact structure can be thinner, thus avoiding the problem of excessive thickness of the first metal layer affecting photolithographic alignment. Finally, the metal-semiconductor compound, as the material for the contact structure between the semiconductor host and the storage capacitor, has low resistivity, enabling better electrical connection between the semiconductor host and the storage capacitor and improving the reliability of the semiconductor device.

[0124] In this embodiment, the top dimension of the conductive contact structure along the X-axis is larger than the top dimension of the semiconductor body along the X-axis, thereby further increasing the connection window between the conductive contact structure and the storage capacitor, and also further reducing the contact resistance.

[0125] Figure 2 A schematic diagram of the structure of a semiconductor device provided in this disclosure embodiment. Figure 5 ;like Figure 5 As shown, a semiconductor device 100 includes a second semiconductor structure 102 and a first semiconductor structure 104 stacked on the second semiconductor structure 102 along a first direction; wherein, the first semiconductor structure 104 includes: a transistor array including a plurality of semiconductor bodies 1030; a conductive contact structure 1064 located at one end of the semiconductor body 1030 along the first direction and coupled to the semiconductor body 1030; the first direction is the extension direction of the semiconductor body 1030; the conductive contact structure 1064 includes a first contact structure and a second contact structure; the first contact structure includes a first metal layer, and the second contact structure includes a second metal layer.

[0126] In some specific embodiments, the material of the first metal layer includes, but is not limited to, tungsten or copper. The material of the second metal layer includes, but is not limited to, tungsten or copper.

[0127] In some embodiments, the first metal layer and the second metal layer are made of the same material. In one example, both the first metal layer and the second metal layer are made of tungsten.

[0128] In some embodiments, the thickness of the second metal layer in the first direction is greater than the thickness of the first metal layer in the first direction.

[0129] In some embodiments, the thickness of the first metal layer in the first direction is less than 20 nm.

[0130] In some embodiments, the thickness of the second metal layer in the first direction is greater than 50 nm.

[0131] In some embodiments, a semiconductor body 1030 extending along a first direction and a gate structure 1036 in contact with at least a portion of the side of the semiconductor body 1030 constitute a vertical transistor 1026.

[0132] In some embodiments, the top dimension of the conductive contact structure 1064 along the second direction is larger than the top dimension of the semiconductor body 1030 along the second direction. This increases the connection window between the conductive contact structure and the storage capacitor, and can also further reduce the contact resistance.

[0133] In some embodiments, the first contact structure further includes a first semiconductor layer, a first conductive layer, and a first contact layer; the first semiconductor layer, the first conductive layer, the first contact layer, and the first metal layer are stacked sequentially along a first direction; the first semiconductor layer is in contact with the semiconductor body, and the first metal layer is in contact with the second contact structure.

[0134] In some embodiments, the material of the first semiconductor layer includes a polycrystalline material, such as polycrystalline silicon. In other embodiments, the material of the first semiconductor layer includes a monocrystalline material, such as monocrystalline silicon.

[0135] In some specific embodiments, the first conductive layer includes a metal semiconductor compound, wherein the metal element in the metal semiconductor compound includes, but is not limited to, tungsten, nickel, cobalt, or titanium.

[0136] In some specific embodiments, the material of the first contact layer includes, but is not limited to, titanium or titanium nitride.

[0137] In some embodiments, the second contact structure further includes a second contact layer, which is located at least between the first metal layer and the second metal layer.

[0138] In some specific embodiments, the material of the second contact layer includes, but is not limited to, titanium or titanium nitride.

[0139] In some embodiments, the first contact layer and the second contact layer are made of the same material. In one example, both the first contact layer and the second contact layer are made of titanium nitride.

[0140] In some embodiments, the first contact structure is in contact with the semiconductor body, and the second contact structure is in contact with the storage capacitor.

[0141] In some embodiments, the method further includes: alignment marks disposed in the transistor array.

[0142] In this embodiment of the disclosure, since the conductive mask layer is retained as part of the conductive contact structure, the thickness of the first metal layer can be set to be thinner, which is beneficial for photolithographic alignment with alignment marks provided in the transistor array.

[0143] In some embodiments, the system further includes: a plurality of bit lines 1023 extending along the second direction and coupled to the other end of the vertical transistor 1026; and a plurality of isolation structures located between adjacent groups of vertical transistors along the third direction and extending along the third direction.

[0144] In some embodiments, the plurality of isolation structures include: a first isolation structure 1060 and a second isolation structure 1062 alternately arranged along the second direction.

[0145] In some embodiments, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 between the gate electrode 1034 and the semiconductor body 1030 in the second direction and the third direction.

[0146] In some embodiments, the vertical transistor 1026 further includes a source 1038 and a drain 1040 respectively disposed at two ends of the semiconductor body 1030 in a first direction; one of the source 1038 and the drain 1040 of the vertical transistor 1026 is coupled to the storage capacitor 1028 in a corresponding memory cell; the other of the source 1038 and the drain 1040 of the vertical transistor 1026 is coupled to a corresponding bit line 1023. In some embodiments, the source 1038 is coupled to the storage capacitor 1028, and the drain 1040 is coupled to the bit line 1023.

[0147] In some embodiments, the vertical transistor 1026 includes at least one of a gate-all-around (GAA) transistor, a tri-gate transistor, a dual-gate transistor, or a single-gate transistor.

[0148] In some embodiments, the storage capacitor 1028 includes at least one of a capacitor, a ferroelectric capacitor, or a phase change memory (PCM) element.

[0149] In some embodiments, the storage capacitor 1028 is a capacitor including a first electrode, a second electrode, and a capacitor dielectric.

[0150] In some embodiments, the second semiconductor structure 102 and the first semiconductor structure 104 are connected by a bonding interface 106, and the second semiconductor structure 102 includes peripheral circuitry 1012.

[0151] It should be noted that, Figure 1 Other structures shown in the image can be referenced. ​ To understand it.

[0152] In this embodiment, a conductive mask layer is used as a mask for etching to form a first contact structure, while the conductive mask layer is retained as a second contact structure. This forms a conductive contact structure through the first and second contact structures. This increases the thickness of the conductive contact structure while avoiding the problem of excessive thickness of the first metal layer in the first contact structure affecting photolithographic alignment. On one hand, the increased thickness of the conductive contact structure improves the landing window for subsequent etching processes. On the other hand, because the conductive mask layer is retained as the second contact structure, the thickness of the first metal layer in the first contact structure can be thinner, thus avoiding the problem of excessive thickness of the first metal layer affecting photolithographic alignment. Finally, the metal-semiconductor compound, as the material for the contact structure between the semiconductor host and the storage capacitor, has low resistivity, enabling better electrical connection between the semiconductor host and the storage capacitor and improving the reliability of the semiconductor device.

[0153] This disclosure provides another memory system, including: a semiconductor device as described in the above embodiments; and a memory controller connected to the semiconductor device and used to control the semiconductor device.

[0154] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0155] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0156] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a transistor array comprising a plurality of semiconductor bodies; a conductive contact structure, the conductive contact structure being located at one end of the semiconductor bodies along a first direction, the first direction being an extension direction of the semiconductor bodies, and coupled with the semiconductor bodies; the conductive contact structure comprises a first contact structure and a second contact structure; the first contact structure comprises a first metal layer, and the second contact structure comprises a second metal layer.

2. The semiconductor device of claim 1, wherein: the first metal layer and the second metal layer are made of the same material.

3. The semiconductor device of claim 1, wherein: a thickness of the second metal layer in the first direction is greater than a thickness of the first metal layer in the first direction.

4. The semiconductor device of claim 3, wherein: the thickness of the first metal layer in the first direction is less than 20 nm.

5. The semiconductor device of claim 3, wherein: the thickness of the second metal layer in the first direction is greater than 50 nm.

6. The semiconductor device of claim 1, wherein: the first contact structure further comprises a first semiconductor layer, a first conductive layer, and a first contact layer; the first semiconductor layer, the first conductive layer, the first contact layer, and the first metal layer are sequentially stacked along the first direction; the first semiconductor layer is in contact with the semiconductor bodies, and the first metal layer is in contact with the second contact structure.

7. The semiconductor device of claim 6, wherein: the second contact structure further comprises a second contact layer, the second contact layer being located at least between the first metal layer and the second metal layer.

8. The semiconductor device of claim 1, wherein Further comprising: a plurality of storage capacitors, each of the storage capacitors being coupled to the semiconductor bodies through the conductive contact structure.

9. The semiconductor device of claim 8, wherein: the first contact structure is in contact with the semiconductor bodies, and the second contact structure is in contact with the storage capacitors.

10. The semiconductor device of claim 7, wherein: the first contact layer and the second contact layer are made of the same material.

11. The semiconductor device of claim 6, wherein, Further comprising: an alignment mark, the alignment mark being disposed in the transistor array.

12. A method of fabricating a semiconductor device, characterized by, The method comprises: providing a transistor array, the transistor array comprising a plurality of semiconductor bodies; sequentially forming a to-be-etched stack and a conductive mask layer on the transistor array; etching the to-be-etched stack using the conductive mask layer to form a first contact structure; retaining the conductive mask layer on the first contact structure to form a second contact structure.

13. The method of claim 12, wherein, The first contact structure comprises a first metal layer; and the conductive mask layer comprises a second metal layer.

14. The method of claim 13, wherein, The first metal layer and the second metal layer are made of the same material.

15. The method of claim 13, wherein, A thickness of the second metal layer in a first direction is greater than a thickness of the first metal layer in the first direction; the first direction being an extension direction of the semiconductor bodies.

16. The semiconductor device of claim 13, wherein: A thickness of the first metal layer in the first direction is less than 20 nm.

17. The semiconductor device of claim 13, wherein, A thickness of the second metal layer in the first direction is greater than 50 nm.

18. The method of claim 12, wherein, Forming the to-be-etched stack includes: Sequentially forming a first semiconductor layer, a first conductive layer, a first contact layer, and a first metal layer on the transistor array.

19. The method of claim 12, wherein, The transistor array is provided with an alignment mark; forming the conductive mask layer includes: forming a first mask layer and a photoresist layer on the to-be-etched stack; forming a patterned photoresist layer with the alignment mark as a reference; forming a contact hole in the first mask layer by a self-aligned double patterning (SADP) process with the patterned photoresist layer as a mask; forming the conductive mask layer in the contact hole.

20. The method of claim 19, wherein, Forming the conductive mask layer in the contact hole includes: sequentially forming a second contact layer and a second metal layer in the contact hole, the second contact layer covering a bottom and sidewalls of the contact hole, and the second metal layer filling the contact hole; removing the first mask layer to form the conductive mask layer.

21. The method of claim 12, wherein, The first contact structure and the second contact structure form a conductive contact structure, and the method further includes: depositing an insulating material to form an insulating structure between the conductive contact structures; a surface of the insulating structure is flush with a surface of the conductive contact structure.

22. The method of claim 12, wherein, The method further includes: forming a storage capacitor coupled to the second contact structure, the storage capacitor being coupled to the semiconductor body through the first contact structure and the second contact structure.

23. A memory system, comprising: including: the semiconductor device of any one of claims 1-11; and, a memory controller connected to the semiconductor device and configured to control the semiconductor device.

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