A full layout-based test layout generation method

Abstract

The application provides a full layout-based test layout generation method, which comprises the following steps: reading a layout with a main pattern, predicting possible weak points in the layout by using an OPC model; extracting layout information corresponding to the weak points; importing the layout information corresponding to the weak points into a test layout generation tool, and modifying the layout information in multiple ways according to user-defined pattern rules to obtain multiple test layouts; detecting whether there is a layout in which the weak points disappear in the multiple test layouts by using the OPC model; if there is, transplanting the layout information of the layout into the main pattern; otherwise, screening a corresponding test layout from the multiple test layouts according to a set screening rule to perform photolithography process exposure, collecting actual layout parameters obtained after exposure, and modifying the OPC model according to the actual layout parameters obtained after exposure. The technical scheme of the application can generate a large number of test layouts and modify the OPC model.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor manufacturing, and in particular to a method for generating test layouts based on full layout. Background Technology

[0002] In the manufacturing process of integrated circuits (ICs), a target pattern is obtained on a wafer by transferring the pattern from a photomask to the surface of the silicon wafer. This is known as photolithography. Photolithography typically involves exposure, development, and etching steps. During exposure, light emitted from a light source passes through the transparent areas of the photomask and illuminates the silicon wafer coated with photoresist. The areas of the photoresist not blocked by the mask undergo a chemical reaction upon exposure to light. In the development step, the different solubility of the developer in the photoresist and the unphotoresisted areas create a photolithographic pattern, transferring the pattern from the photomask to the photoresist. In the etching step, the silicon wafer is etched based on the photolithographic pattern formed by the photoresist layer, further transferring the pattern from the photomask to the silicon wafer.

[0003] As Moore's Law advances and design dimensions continue to shrink, the minimum size of the design pattern approaches the limits of photolithography imaging systems. The diffraction effect of light becomes increasingly pronounced, resulting in severe distortion of the image obtained from exposure compared to the pattern on the mask. Consequently, the actual pattern formed on the silicon wafer through photolithography differs from the design pattern. This phenomenon is known as the Optical Proximity Effect (OPE). To correct the OPE, Optical Proximity Correction (OPC) was developed. This correction adjusts the pattern on the mask to offset the OPE, achieving a photolithography result that better matches the desired outcome.

[0004] During the layout correction process, OPC predicts potential weaknesses using models. Currently, mainstream OPC tools (such as calibre) provide information on these weaknesses during layout correction, which facilitates user analysis. However, there are still inconveniences in analyzing new layouts that appear later. The main reason is that mainstream OPC tools can only export result databases with relatively concentrated weaknesses. For layouts with dispersed weaknesses, such result databases cause great inconvenience for user analysis. Summary of the Invention

[0005] The purpose of this invention is to provide a test layout generation method based on the full layout, thereby solving the technical problem of inconvenient optical proximity correction of the layout in the prior art.

[0006] In this embodiment of the invention, a method for generating a test layout based on a full layout is provided, comprising:

[0007] Read the layout with the main graphic and use the OPC model to predict potential weaknesses in the layout;

[0008] Extract the layout information corresponding to the weakness;

[0009] The layout information corresponding to the weaknesses is imported into the test layout generation tool, and modified in various ways according to the user-defined graphic arrangement rules to obtain multiple test layouts.

[0010] The OPC model is used to detect whether there are any layouts in the multiple test layouts where weaknesses disappear.

[0011] If it exists, then the layout information of that layout is transferred to the main graphic;

[0012] Otherwise, according to the set filtering rules, the corresponding test pattern is selected from the multiple test patterns for photolithography exposure, the actual pattern parameters obtained after exposure are collected, and the OPC model is corrected according to the actual pattern parameters obtained after exposure.

[0013] In this embodiment of the invention, the layout information corresponding to the weakness includes the main graphic information, coordinates, line width, line length, and periodicity information of the weakness.

[0014] In this embodiment of the invention, the user-defined graphic arrangement rules include: auxiliary graphic generation rules, period, line width, and line length range.

[0015] In this embodiment of the invention, modifying the layout information corresponding to the weakness includes:

[0016] Add auxiliary graphics, and modify line width and line length.

[0017] In this embodiment of the invention, the OPC model is corrected based on the actual layout parameters obtained after exposure, including:

[0018] Input the obtained actual layout parameters into the EDA software;

[0019] Adjust the parameters of the OPC model to make the calculation results of the OPC model match the actual layout parameters as closely as possible.

[0020] Compared with existing technologies, the test layout generation method based on the full layout of this invention allows users to select a main graphic with characteristics from the full layout, import it into the test layout generation tool, and modify it by defining the graphic type and graphic arrangement rules. This simple and fast method generates a large number of test layouts. The test layouts are then exposed through photolithography to obtain parameters that maximize the process window of the main graphic and auxiliary graphic parameters. These parameters are used to guide model-based optical proximity effect correction and to correct the OPC model, thereby obtaining a highly accurate layout and improving the efficiency of chip manufacturing. Attached Figure Description

[0021] Figure 1 This is a flowchart of a test layout generation method based on a full layout according to an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0023] The implementation of the present invention will be described in detail below with reference to specific embodiments.

[0024] like Figure 1 As shown in the figure, this embodiment of the invention provides a method for generating a test layout based on a full layout, which includes steps S1-S6. These are described below.

[0025] Step S1: Read the layout with the main graphic and use the OPC model to predict the possible weaknesses in the layout.

[0026] In this embodiment of the invention, the user first selects a layout with a main graphic and uses an EDA tool to read the provided layout, including the graphic type, line width, period, coordinates, length, and auxiliary graphic information of the main graphic.

[0027] It's important to note that most mainstream EDA tools currently include an OPC model for optical proximity correction and weakness detection in layouts. The OPC model can be used to predict potential weaknesses in the layout. Weaknesses refer to parts that do not meet process window requirements (the printed pattern differs from the original design). Generally, weaknesses are not allowed in the layout. Therefore, any potential weaknesses predicted by the OPC model must be addressed.

[0028] Step S2: Extract the layout information corresponding to the weakness.

[0029] In this embodiment of the invention, the layout information corresponding to the weakness includes the main graphic information, coordinates, line width, line length, and periodicity information of the weak point. EDA tools can be used to extract the layout information corresponding to the weakness and output it as a file.

[0030] Step S3: Import the layout information corresponding to the weakness into the test layout generation tool, and modify it in various ways according to the user-defined graphic arrangement rules to obtain multiple test layouts.

[0031] It should be noted that when generating test layouts, the test layout tool requires specifying data such as graphic type, modifying auxiliary graphic generation rules, line width and length ranges, and period. User-defined graphic arrangement rules include: auxiliary graphic generation rules, period, and line width and length ranges. The graphic type and period should be consistent with the main graphic. Modifying the layout information corresponding to the weaknesses includes adding auxiliary graphics and modifying line width and length. Under the user-defined graphic arrangement rules, different auxiliary graphics can be added, and different line widths and lengths can be set, thus obtaining multiple different test layouts.

[0032] Step S4: Use the OPC model to detect whether there is a layout in the multiple test layouts where the weakness disappears. If there is, proceed to step S5; otherwise, proceed to step S6.

[0033] After obtaining multiple test layouts in step S3, the OPC model can be used to test these test layouts to detect whether the weaknesses have been corrected, that is, whether the weaknesses have disappeared.

[0034] Step S5: Transfer the layout information of the test layout to the main layout.

[0035] It should be noted that if a weakness disappears in a certain test layout, it means that the weakness has been overcome. In this case, the above-mentioned correction scheme can be used to transfer the layout information of the test layout to the main layout and correct the main layout.

[0036] Step S6: Select the corresponding test pattern from the multiple test patterns according to the set screening rules, perform photolithography exposure, collect the actual pattern parameters obtained after exposure, and correct the OPC model according to the actual pattern parameters obtained after exposure.

[0037] It should be noted that if none of the test layouts obtained in step S3 have their weaknesses overcome, it indicates that the weakness may be due to hardware information such as the equipment's process parameters, and the OPC model needs to be corrected based on the actual generated layout data. Therefore, users can set certain conditions to filter the test layouts in step S3, expose the filtered test layouts using photolithography, collect the actual layout parameters obtained after exposure, and correct the OPC model based on the actual layout parameters obtained after exposure.

[0038] Specifically, in this embodiment of the invention, the OPC model is corrected based on the actual layout parameters obtained after exposure, including:

[0039] Input the obtained actual layout parameters into the EDA software;

[0040] Adjust the parameters of the OPC model to make the calculation results of the OPC model match the actual layout parameters as closely as possible.

[0041] It should be noted that the OPC model is a semi-empirical model. The more experimental data there is, the more accurate the model will be. The more experimental data collected on the areas where weaknesses exist, the more helpful it will be in analyzing the causes of weaknesses and finding solutions.

[0042] In summary, by employing the full-pattern-based test layout generation method of this invention, users can select a main graphic with distinctive features from the full-pattern layout, import it into the test layout generation tool, and modify it by defining the graphic type and graphic arrangement rules. This allows for the simple and rapid generation of a large number of test layouts. The test layouts are then exposed using photolithography to obtain parameters that maximize the process window of the main graphic, as well as auxiliary graphic parameters. These parameters are used to guide model-based optical proximity effect correction and to modify the OPC model, thereby obtaining a highly accurate layout and improving the efficiency of chip manufacturing.

[0043] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for generating a test layout based on a full layout, characterized in that, include: Read the layout with the main graphic and use the OPC model to predict potential weaknesses in the layout; Extract the layout information corresponding to the weakness; The layout information corresponding to the weaknesses is imported into the test layout generation tool, and modified in various ways according to the user-defined graphic arrangement rules to obtain multiple test layouts. The OPC model is used to detect whether there are any layouts in the multiple test layouts where weaknesses disappear. If it exists, then the layout information of that layout is transferred to the main graphic; Otherwise, according to the set filtering rules, the corresponding test pattern is selected from the multiple test patterns for photolithography exposure, the actual pattern parameters obtained after exposure are collected, and the OPC model is corrected according to the actual pattern parameters obtained after exposure.

2. The test layout generation method based on the full layout as described in claim 1, characterized in that, The layout information corresponding to the weakness includes the main graphic information, coordinates, line width, line length, and periodicity information of the weakness.

3. The test layout generation method based on the full layout as described in claim 1, characterized in that, User-defined graphic arrangement rules include: auxiliary graphic generation rules, period, line width, and line length range.

4. The test layout generation method based on the full layout as described in claim 1, characterized in that, Modifying the layout information corresponding to the aforementioned weakness includes: Add auxiliary graphics, and modify line width and line length.

5. The test layout generation method based on the full layout as described in claim 1, characterized in that, The OPC model is corrected based on the actual layout parameters obtained after exposure, including: Input the obtained actual layout parameters into the EDA software; Adjust the parameters of the OPC model to make the calculation results of the OPC model match the actual layout parameters as closely as possible.

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