Memory-interface translator chip

Abstract

A memory device including a memory interface chip and an operating method thereof are provided. In some embodiments, the memory device includes a controller integrated circuit, a first memory die, and a first converter integrated circuit having a first external interface and a second external interface, the first external interface being a serial interface, the first external interface being connected to the controller integrated circuit, and the second external interface being a memory interface connecting the first converter integrated circuit to the first memory die.

Description

TECHNICAL FIELD

[0001] One or more aspects of embodiments according to the present disclosure relate to persistent storage, and more specifically, to an interface chip for a persistent storage device. BACKGROUND

[0002] A persistent storage device can include a controller and a storage medium (e.g., multiple memory dies in a package). Parallel connections between the controller and the memory dies can be susceptible to skew, can consume a large amount of chip area on the controller, and can complicate the routing of a printed circuit board to which the controller and the storage medium can be affixed.

[0003] Aspects of the present disclosure are related to this general technical environment. SUMMARY

[0004] According to embodiments of the present disclosure, a storage device is provided, including: a controller integrated circuit; a first memory die; and a first converter integrated circuit, the first converter integrated circuit having a first external interface and a second external interface, the first external interface being a serial interface, the first external interface being connected to the controller integrated circuit, and the second external interface being a memory interface connecting the first converter integrated circuit to the first memory die.

[0005] In some embodiments, the first memory die is a NAND flash die.

[0006] In some embodiments, the second external interface complies with a Toggle standard or an Open NAND Flash Interface (ONFI) standard.

[0007] In some embodiments, the storage device includes a package, the package including: the first memory die; the first converter integrated circuit; and a substrate, the first memory die and the first converter integrated circuit being affixed to the substrate.

[0008] In some embodiments, the storage device further includes a wire bond connected to the first converter integrated circuit and the first memory die.

[0009] In some embodiments, the first external interface is a Serial Peripheral Interface (SPI) or a Peripheral Component Interconnect Express (PCIe) interface or a Universal Chiplet Interconnect Express (UCIE).

[0010] In some embodiments, the first converter integrated circuit is configured to receive a packet including a packet header and a packet payload at the first external interface.

[0011] In some embodiments, the packet payload includes a first die payload, the first die payload including a command or data.

[0012] In some embodiments, the packet payload further includes a second die payload interleaved with the first die payload.

[0013] In some embodiments, the packet payload further includes a third die payload interleaved with the first die payload and the second die payload.

[0014] In some embodiments, the packet header includes an indicator that signals that the packet payload includes interleaved die payloads.

[0015] In some embodiments, the storage device further includes a second memory die, wherein the first memory die has a first die identifier and the second memory die has a second die identifier different from the first die identifier.

[0016] In some embodiments, the packet header includes a first die identifier and a second die identifier that signal an interleaving order in the packet payload.

[0017] In some embodiments, the storage device further includes a second converter integrated circuit and a switch, the first external interface is connected to the controller integrated circuit through the switch, and the second converter integrated circuit is connected to the controller integrated circuit through the switch.

[0018] In some embodiments, the storage device further includes a second converter integrated circuit, the second converter integrated circuit has a first external interface and a second external interface, the first external interface of the second converter integrated circuit is a serial interface, the second external interface of the second converter integrated circuit is a memory interface for connecting the second converter integrated circuit to a second memory die, and the second converter integrated circuit is connected to the controller integrated circuit through the first converter integrated circuit.

[0019] According to embodiments of the present disclosure, a method is provided, comprising: receiving, by a first converter integrated circuit of a storage device, a packet from a controller integrated circuit of the storage device through a first external interface of the first converter integrated circuit, the packet including a packet header and a packet payload; and sending, by the first converter integrated circuit, the packet payload through a second external interface of the first converter integrated circuit, the first external interface being a serial interface and the second external interface being a memory interface for connecting the first converter integrated circuit to a first memory die of the storage device.

[0020] In some embodiments, the first memory die is a NAND flash die.

[0021] In some embodiments, the first external interface is a serial peripheral interface (SPI) or a peripheral component interconnect express (PCIe) interface.

[0022] In some embodiments, the packet payload includes: a first die payload of the first memory die; and a second die payload of a second memory die of the storage device, the second die payload interleaved with the first die payload.

[0023] According to embodiments of the disclosure, a storage device is provided, comprising: a controller integrated circuit; a first memory die; and means for conversion, the means for conversion having a first external interface and a second external interface, the first external interface being a serial interface, the first external interface connected to the controller integrated circuit, and the second external interface being a memory interface connecting the means for conversion to the first memory die. BRIEF DESCRIPTION OF DRAWINGS

[0024] These and other features and advantages of the present disclosure will be appreciated and understood by reference to the detailed description, claims, and accompanying drawings, in which:

[0025] Figure 1A is a block diagram of a persistent storage device according to embodiments of the disclosure;

[0026] Figure 1B is a block diagram of a persistent storage device according to embodiments of the disclosure;

[0027] Figure 1C is a schematic side view of a memory package according to embodiments of the disclosure;

[0028] Figure 1D is a schematic plan view of a memory package according to embodiments of the disclosure;

[0029] Figure 2A is a block diagram of a persistent storage device according to embodiments of the disclosure;

[0030] Figure 2B is a block diagram of a persistent storage device and media card according to embodiments of the disclosure;

[0031] Figure 2C is a block diagram of a persistent storage device according to embodiments of the disclosure;

[0032] Figure 3 is a flowchart according to embodiments of the disclosure; and

[0033] Figure 4 is a flowchart according to embodiments of the disclosure. DETAILED DESCRIPTION

[0034] The detailed description set forth below, in connection with the appended drawings, is intended as a description of exemplary embodiments of memory interface chips provided in accordance with the present disclosure and is not intended to represent the only form in which the present disclosure can be constructed or utilized. The description sets forth the features of the present disclosure in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent features can be utilized in

[0035] In some embodiments, in a persistent storage device, a translator integrated circuit is connected between a controller of the persistent storage device and memory dies (e.g., flash memory dies) of the persistent storage device. The translator integrated circuit can have a serial connection (including, e.g., one or more serial lanes) to the controller and a parallel interface to each of the memory dies.

[0036] Compared to embodiments in which the controller is directly connected to the plurality of memory dies through a plurality of parallel interfaces, using a translator integrated circuit connected to the controller through a serial interface and to the memory dies through parallel interfaces has several advantages. For example, timing skew that can limit the data rate in a parallel connection can not be important in a serial connection. In addition, the number of pads required at the controller can be significantly reduced.

[0037] Reference Figure 1A In some embodiments, the persistent storage device 100 includes a controller (or “controller integrated circuit”) 102 and a plurality of memory packages 105, each of which can include a translator integrated circuit 110 (or “chiplet,” discussed in further detail below) and a plurality of memory dies 115. The persistent storage device 100 can be connected to a host through a host interface including a host interface connector 120. The controller 102 can include one or more serial interface circuits 125 (which can be serializer-deserializer (SERDES) circuits), through which the controller 102 can be connected to the translator integrated circuits 110 via serial connections 130. Each of the memory dies 115 can be a flash memory die, such as a non-AND (NAND) flash memory die. Each of the controller 102 and the translator integrated circuits 110 can be or include processing circuitry (discussed in further detail below). In some embodiments, the translator integrated circuits 110 are external to the memory packages 105 (e.g., inside the persistent storage device 100, along a path from the controller 102 to the memory packages 105), as shown. Figure 1B

[0038] ​The persistent storage device 100 can have a form factor suitable for any of a number of form factors for persistent storage devices, including but not limited to 2.5”, 1.8”, MO-297, MO-300, M.2, U.2, U.3, and Enterprise and Data Center SSD Form Factor (EDSFF), and it can have an electrical interface through which the persistent storage device 100 can be connected to a host, the electrical interface being any of a number of interfaces suitable for permanent storage devices, including Peripheral Component Interconnect (PCI), PCI Express (PCIe), Ethernet, Small Computer System Interface (SCSI), Serial AT Attachment (SATA), and Serial Attached SCSI (SAS).

[0039] With reference to Figure 1C and Figure 1D Each memory package 105 can include (as described above) a translator integrated circuit 110 and a number of memory dies 115. The translator integrated circuit 110 can be connected to each of the memory dies 115 through a respective parallel interface 135, which can include one or more wire bonds, each forming a connection between a wire bond pad on the translator integrated circuit 110 and a wire bond pad on the memory die 115. The translator integrated circuit 110 and the memory dies 115 can be secured to a substrate 127, which can be, for example, a ceramic substrate or an organic substrate (e.g., a printed circuit board). The substrate can have one or more layers of electrically conductive (e.g., metallic) traces and one or more vias separated by insulating layers. A ball grid array on a lower surface of the substrate 127 can be used to connect to a printed circuit board of a storage device. As shown, the memory dies 115 can be stacked in an interleaved manner, allowing a large number of memory dies to be placed on a small area of the substrate 127, while leaving a portion of a top surface of each of the memory dies 115 exposed so that each of the memory dies 115 can be connected (e.g., via wire bonds). The parallel interface 135 can be, for example, an interface that complies with the Open NAND Flash Interface (ONFI) standard or that complies with the Toggle standard. The translator integrated circuit 110 can be connected to the controller through a serial interface 140, and it can have a forward serial connection 145 for forming a daisy chain connection (discussed in further detail below). Figure 1C

[0040] In some embodiments, the serial interface 140 between the controller 102 and each translator integrated circuit 110 is a Serial Peripheral Interface (SPI) or a PCIe interface (e.g., a reduced, e.g., mobile, PCIe interface). In some embodiments, the serial interface 140 is a Universal Chiplet Interconnect Express (UCIE) interface or a short-reach serial interface (e.g., an Ultra-Short-Reach (USR) interface or an Ultra-Short-Reach (XSR) interface). ​

[0041] In operation, the controller 102 can send bit packets to the translator integrated circuit 110, each packet including a packet header and a packet payload. The header can include (e.g., begin with) a start delimiter, which can be or include a string of bits that is unlikely to occur in the payload (e.g., a long (e.g., 32 bits or longer) pseudo-random binary word). The payload can include one or more die payloads, which include commands and data to be sent to one or more of the memory dies 115. Each of the memory dies 115 can have a respective identifier (e.g., a 4-bit identifier) that can be programmed into the memory die 115 and can be different from the die identifiers of the other memory dies 115 in the memory package 105. Multiplexing (or “interleaving”) of the die payloads can be used in the payload to reduce latency. For example, if data is being transferred from the controller 102 to three (e.g., dies 0, 1, and 2) of the memory dies 115 during a time interval, the payload can include interleaved respective data words for the three memory dies 115. For example, the payload can repeatedly include the sequence {[data die #0], [data die #1], [data die #2]} (where [data die #0] is a data word for die 0, [data die #1] is a data word for die 1, and [data die #2] is a data word for die 2). Each data word can be a single bit or a set of bits (e.g., 4 bits, 8 bits, 16 bits, or 32 bits). Similarly, data transferred from the memory dies 115 to the controller 102 can be interleaved through the translator integrated circuit 110. Buffering of the data received from the memory dies 115 can be performed by the translator integrated circuit 110 to ensure that the data is available when needed to be sent to the controller 102 in any packet. When the die payloads are interleaved, the packet header can include (i) an indicator (e.g., a bit used as a flag) signaling that the packet payload includes interleaved die payloads; and (ii) a set of die identifiers for the dies whose payloads are interleaved, the set of die identifiers signaling the interleaving order in the packet payload.

[0042] Reference Figure 2AIn some embodiments, the switch 205 can be used to route packets from the controller 102 to the translator integrated circuits 110 in the plurality of memory packages 105, such that each of the translator integrated circuits 110 is connected to the controller 102 through the switch. In this configuration, each packet sent by the controller 102 can include in the header an identifier of the translator integrated circuit 110 to which the packet is addressed (or "translator identifier"); the switch 205 can parse the header and route the packet accordingly. Each packet sent by the translator integrated circuits 110 can also include the translator identifier of the sending translator integrated circuit 110, enabling the controller to identify its origin. This embodiment can be used with or without data interleaving of different memory dies 115. The use of a switch can make it possible to accommodate a larger number of memory packages 105 in the persistent storage device 100. As shown, the bandwidth of the connection between the controller 102 and the switch 205 can be increased by connecting the switch 205 to the controller 102 with multiple serial lanes (e.g., SPI lanes or PCIe lanes). In some embodiments, the switch 205 is connected to the controller 102 through a single serial lane. In some embodiments, one or more of the translator integrated circuits 110 can be external to the corresponding memory package 105 (e.g., they can be at the output ports of the switch 205).

[0043] In some embodiments, data can be multiplexed across the translator integrated circuits 110 in a manner similar to the multiplexing across memory dies 115 described above. For example, the controller 102 can repeatedly send groups of data words in the format {[data chiplet #0], [data chiplet #1], [data chiplet #2]}, where [data chiplet #0] is a data word for a first translator integrated circuit 110 ("chiplet #0"), [data chiplet #1] is a data word for a second translator integrated circuit 110 ("chiplet #1"), and [data chiplet #2] is a data word for a third translator integrated circuit 110 ("chiplet #2"). The multiplexing can be performed simultaneously across the translator integrated circuits 110 and across the memory dies 115. For example, the first translator integrated circuit 110 can demultiplex the share of the data stream that it receives from the switch 205 and send the respective portions to each of the plurality of memory dies 115 to which the first translator integrated circuit 110 is connected. In some embodiments, as shown, a media card 210 including a switch 205 and a plurality of memory packages 105 can be connected to the switch 205 of the persistent storage device 100 to further expand the number of memory packages 105 that can be accommodated. The media card can be within the housing of the persistent storage device 100, or it can be separate (e.g., within a separate housing). Figure 2B

[0044] ​In some embodiments, multiple memory packages 105 can be connected to the serial interface 140 of another memory package 105 by connecting the forwarding serial connection 145 of each of one or more memory packages 105 to the serial interface 140 of the other memory package 105. Figure 2C As shown, they are connected by a daisy chain. Figure 2C In this embodiment, when the first converter integrated circuit 110 receives a packet at its serial interface 140, the first converter integrated circuit 110 forwards the packet through its forwarding serial connection 145 (and other converter integrated circuits 110 in the chain operate in the same manner); in this manner, each converter integrated circuit 110 in the chain receives each packet. The first converter integrated circuit 110 also parses the packet header to extract the converter identifier. If the converter identifier in the packet header matches the converter identifier of the first converter integrated circuit 110, the first converter integrated circuit 110 processes the packet (e.g., sends the payload to the memory die 115 identified in the memory die identifier field of the packet header). If the converter identifier in the packet header does not match the converter identifier of the first converter integrated circuit 110, the first converter integrated circuit 110 ignores the remainder of the packet. Each other converter integrated circuit 110 operates in the same manner when it receives a packet. In this manner, a packet can be processed by the converter integrated circuit 110 in the chain that has a matching converter identifier.

[0045] In some embodiments, controller 102 may perform a discovery process to determine the converter identifier of each converter integrated circuit 110 connected to it. This may be based on... Figure 3 The process is executed according to the flowchart. At 305, controller 102 initializes the identifier value, for example, to zero. At 310, controller 102 sends an inquiry command (e.g., a command to inquire whether a receiver exists) to the first converter integrated circuit 110 in the chain. If at 315, controller 102 receives a valid response (from the first converter integrated circuit 110 in the chain or from another converter integrated circuit 110 in the chain, which receives the response after it has been forwarded by the first converter integrated circuit 110 in the chain), then controller 102 registers the converter integrated circuit 110 (chip) from which it received the response (e.g., it includes the current identifier value in a table of valid converter identifier values). Controller 102 then determines at 325 whether it has reached the maximum possible value of the identifier value. If it has, then at 330, the discovery process terminates; if it has not, controller 102 increments the identifier value at 335 and returns to step 310. If at 315, controller 102 does not receive a valid response, then control transfers to the determination step at 325.

[0046] Figure 4is a flow diagram of a method in some embodiments. The method includes: receiving, by a first translator integrated circuit of a storage device, from a controller integrated circuit of the storage device, a packet over a first external interface of the first translator integrated circuit, the packet including a packet header and a packet payload; and sending, by the first translator integrated circuit, the packet payload over a second external interface of the first translator integrated circuit, at 410. The first external interface can be a serial interface, and the second external interface can be a memory interface connecting the first translator integrated circuit to a first memory die of the storage device.

[0047] As used herein, a "portion" of something means "at least some" of the thing, and as such, can mean less than all of the thing or all of the thing. As such, a "portion" of a thing includes, as a special case, the entire thing, i.e., the entire thing is an example of a portion of the thing. As used herein, when a second quantity is "within Y of a first quantity X," it means that the second quantity is at least X-Y, and the second quantity is at most X+Y. As used herein, when a second quantity is "within Y% of a first quantity," it means that the second quantity is at least (1-Y / 100) times the first quantity, and the second quantity is at most (1+Y / 100) times the first quantity. As used herein, the term "or" is to be interpreted as "and / or," such that, for example, "A or B" means "A" or "B" or "A and B."

[0048] The background provided in the Background section of this disclosure is included solely for setting context and does not suggest that any component or combination of components described in this section of the background is art-recognized as being useful for performing one or more of the operations included in any of the flow diagrams included herein. Moreover, (i) the operations are example operations and can involve various additional steps not explicitly covered, and (ii) the time ordering of the operations can vary.

[0049] As used herein, the term "processing circuitry" means any combination of hardware, firmware and software, used to process data or digital signals. The processing circuitry hardware can include, for example, an application specific integrated circuit (ASIC), a general or special purpose central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), and a programmable logic device such as a field programmable gate array (FPGA). As used herein, each function performed by the processing circuitry is performed either by hardware that is configured (i.e., hardwired) to perform that function, or by more general hardware (such as a CPU) that is configured to execute instructions stored in a non-transitory storage medium. The processing circuitry can be fabricated on a single printed circuit board (PCB), or distributed among several interconnected PCBs. The processing circuitry can contain other processing circuitry; for example, the processing circuitry can include two processing circuitries interconnected over a PCB: an FPGA and a CPU.

[0050] As used herein, when a method (e.g., adjusting) or a first quantity (e.g., a first variable) is referred to as being "based on" a second quantity (e.g., a second variable), this means that the second quantity is an input to the method or influences the first quantity, e.g., the second quantity can be an input (e.g., the only input, or one of several inputs) to a function that computes the first quantity, or the first quantity can equal the second quantity, or the first quantity can be identical to the second quantity (e.g., stored in one or more locations in memory that are identical to the second quantity).

[0051] It should be understood that, although the terms "first", "second", "third", and the like can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed herein could be termed a second element, component, region, layer or section without departing from the spirit and scope of the inventive concept.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the terms "substantially", "about" and similar terms are used as approximating language and are intended to designate that the value of a measurement or calculation is not exact, but is close to the intended value within a reasonable range

[0053] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding the list of two or more members, modify the entire list of members and do not modify the list of members by excluding any one of the members. Also, the use of “can,” “could,” “might,” “may,” “expects,” “is expected,” and the like, are not used as a means to quantify or limit the number of embodiments of the present disclosure. In addition, the term “exemplary” is intended to mean an example or an illustration.

[0054] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “in direct contact with” another element or layer, there are no intervening elements or layers present.

[0055] Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” or “1.0 to 10.0” is intended to include all sub-ranges, e.g., 2.4 to 7.6, 3.5 to 5.5, etc. Similarly, a range of “35% of 10” is intended to include all sub-ranges, e.g., 7.4 to 10.6, 3.5 to 5.5, etc. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.

[0056] While exemplary embodiments of a memory interface chip have been described and illustrated herein, numerous modifications and changes will occur to those skilled in the art. Therefore, it is to be understood that the memory interface chip constructed according to the principles of the present disclosure can be embodied in a different manner than that specifically described herein. The present application is therefore to be taken as illustrative and not restrictive, and the scope of the present application is to be determined not with reference to the above description but with reference to the claims below and equivalents thereof.

Claims

1. A storage device, comprising: Controller integrated circuits; First memory die and second memory die; First converter integrated circuit; and Second converter integrated circuit, The first converter integrated circuit has a first external interface and a second external interface, and the second converter integrated circuit has a first external interface and a second external interface, wherein the first converter integrated circuit is configured to receive a packet including an indicator and a packet payload at the first external interface of the first converter integrated circuit, and wherein the indicator signals that the packet payload includes an interleaved die payload. The first external interface of the first converter integrated circuit and the first external interface of the second converter integrated circuit are each serial interfaces. The first external interface of the first converter integrated circuit is connected to the controller integrated circuit. The second external interface of the first converter integrated circuit is a memory interface that connects the first converter integrated circuit to the first memory die via wire bonding. The second external interface of the second converter integrated circuit is a memory interface that connects the second converter integrated circuit to the second memory die via wire bonding, and The second converter integrated circuit is connected to the controller integrated circuit through the first converter integrated circuit.

2. The storage device according to claim 1, wherein, The first memory die is a NAND flash memory die.

3. The storage device according to claim 2, wherein, The second external interface of the first converter integrated circuit and the second external interface of the second converter integrated circuit conform to the Toggle standard or the Open NAND Flash Interface ONFI standard.

4. The storage device according to claim 1, further comprising a package, the package comprising: The first memory die; The first converter integrated circuit; and Substrate, The first memory die and the first converter integrated circuit are fixed to the substrate.

5. The storage device according to claim 1, wherein, The first external interface of the first converter integrated circuit and the first external interface of the second converter integrated circuit are each a serial peripheral interface (SPI), a peripheral component fast interconnect (PCIe), or a universal core fast interconnect (UCIE).

6. The storage device according to claim 1, wherein, The group includes a group header.

7. The storage device according to claim 6, wherein, The grouped payload includes a first die payload, which includes commands or data.

8. The storage device according to claim 7, wherein, The grouped payload further includes a second die payload that is interwoven with the first die payload.

9. The storage device according to claim 8, wherein, The grouped payload further includes a third die payload that is interwoven with the first die payload and the second die payload.

10. The storage device according to claim 9, wherein, The packet header includes the indicator that signals the packet payload to include interleaved die payloads.

11. The storage device according to claim 9, wherein, The first memory die has a first die identifier, and the second memory die has a second die identifier that is different from the first die identifier.

12. The storage device according to claim 11, wherein, The packet header includes a first die identifier and a second die identifier, which signal the interleaving order in the packet payload.

13. A method performed by a storage device, comprising: A packet is received by a first converter integrated circuit of the storage device from a controller integrated circuit of the storage device via a first external interface of the first converter integrated circuit. The packet includes a packet header and a packet payload, wherein the packet header includes an indicator that signals the packet payload to include an interleaved die payload; and The packet payload is transmitted by the first converter integrated circuit through the second external interface of the first converter integrated circuit. The first external interface of the first converter integrated circuit is a serial interface. The second external interface of the first converter integrated circuit is a memory interface that connects the first converter integrated circuit to the first memory die and the second memory die of the storage device via wire bonding. The second converter integrated circuit of the storage device is connected to the controller integrated circuit through the first converter integrated circuit.

14. The method according to claim 13, wherein, The first memory die is a NAND flash memory die.

15. The method according to claim 13, wherein, The first external interface of the first converter integrated circuit is a serial peripheral interface (SPI) or a peripheral component fast interconnect (PCIe) interface.

16. The method according to claim 13, wherein, The grouped payload includes: The first die payload of the first memory die; and The second die payload of the second memory die of the storage device The effective load of the second die is intertwined with the effective load of the first die.

17. A storage device, comprising: Controller integrated circuits; First memory die and second memory die; First converter; and Second converter, The first converter has a first external interface and a second external interface, and the second converter also has a first external interface and a second external interface. The first converter is configured to receive a packet including an indicator and a packet payload at its first external interface, and the indicator signals that the packet payload includes an interleaved die payload. The first external interface of the first converter and the first external interface of the second converter are each serial interfaces. The first external interface of the first converter is connected to the controller integrated circuit. The second external interface of the first converter is a memory interface that connects the first converter to the first memory die via wire bonding. The second external interface of the second converter is a memory interface that connects the second converter to the second memory die via wire bonding, and The second converter is connected to the controller integrated circuit via the first converter.

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