Gate driving circuit and display panel
By designing pull-up and pull-down control modules in the gate drive circuit and using clock signals to control the node potential, the problem of complex gate drive circuit structure is solved, and the structure is simplified and stability is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2023-10-24
- Publication Date
- 2026-05-12
AI Technical Summary
Existing gate drive circuits are complex in structure and contain a large number of thin-film transistors, resulting in a large number of drive signal input terminals that are difficult to simplify.
By designing a structure including a pull-up control module, a pull-down control module, pull-up nodes, and pull-down nodes, the node potential is controlled by controlling the potential of the first and second clock signals, thereby reducing the number of drive signal input terminals.
The structure of the gate drive circuit is simplified, the number of thin-film transistors and drive signal input terminals are reduced, and the stability of the gate drive circuit is improved.
Smart Images
Figure CN117456874B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, specifically to a gate driving circuit and a display panel. Background Technology
[0002] Gate-driver-on-Array (GOA) technology utilizes the fabrication process of thin-film transistor arrays (TFT arrays) to fabricate gate driver circuitry on a TFT array substrate, enabling a row-by-row scanning driving method. The gate driver circuitry comprises multiple cascaded gate driver units.
[0003] In order to improve the stability of the gate drive circuit while ensuring the basic function of the gate drive circuit, the existing gate drive unit generally contains dozens of thin film transistors, and these dozens of thin film transistors are electrically connected to multiple different drive signal input terminals, making the structure of the gate drive circuit very complex. Summary of the Invention
[0004] The purpose of this application is to provide a gate driving circuit and a display panel that can reduce the number of driving signal input terminals that the gate driving unit needs to access, thereby simplifying the structure of the gate driving circuit and the display panel.
[0005] On one hand, embodiments of this application provide a gate driving circuit, including multiple cascaded gate driving units. Each gate driving unit includes: a pull-up control module, a pull-up node, a first output module, a second output module, a pull-down control module, a first pull-down module, a pull-down node, a second pull-down module, and a pull-down sustaining module. The pull-up control module is electrically connected to a first clock signal input terminal and the pull-up node, and is used to pull up the potential of the pull-up node under the control of a first clock signal input terminal. The first output module is electrically connected to a second clock signal input terminal, the pull-up node, and a current-stage scan signal output terminal, and is used to output a current-stage scan signal under the control of the potential of the pull-up node. The second output module is electrically connected to a third clock signal input terminal, the pull-up node, and a current-stage cascade signal output terminal, and is used to output a current-stage cascade signal under the control of the potential of the pull-up node. The pull-down control module is electrically connected to a first clock signal input terminal, the pull-up node, and a current-stage cascade signal output terminal. The first clock signal input terminal and the pull-down node are electrically connected. The pull-down control module is used to pull the potential of the pull-down node high under the control of the first clock signal. The first pull-down module is electrically connected to the first clock signal input terminal, the pull-up node, and the pull-down node. The first pull-down module is used to pull the potential of the pull-down node low to the potential of the first clock signal under the control of the potential of the pull-up node. The second pull-down module is electrically connected to the local scan signal output terminal, the local cascade signal output terminal, and the pull-down node. The second pull-down module is used to pull down the potential of the local scan signal and the potential of the local cascade signal under the control of the potential of the pull-down node. The pull-down sustaining module is electrically connected to the second clock signal input terminal, the pull-up node, and the pull-down node. The pull-down sustaining module is used to keep the potential of the pull-up node low under the control of the second clock signal input terminal and the potential of the pull-down node.
[0006] Optionally, in some embodiments of this application, the phase of the first clock signal is opposite to the phase of the second clock signal, and the phase of the second clock signal is the same as the phase of the third clock signal input to the third clock signal input terminal.
[0007] Optionally, in some embodiments of this application, the pull-up control module includes a first transistor, the gate of the first transistor is electrically connected to a first clock signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal of the previous stage, and the second electrode of the first transistor is electrically connected to the pull-up node.
[0008] Optionally, in some embodiments of this application, the first output module includes a second transistor and a first capacitor. The gate of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the second clock signal input terminal, and the second electrode of the second transistor is electrically connected to the local stage scan signal output terminal. The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the local stage scan signal output terminal. The second output module includes a third transistor. The gate of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the third clock signal input terminal, and the second electrode of the third transistor is electrically connected to the local stage cascade signal output terminal.
[0009] Optionally, in some embodiments of this application, the pull-down control module includes a fourth transistor, the gate of the fourth transistor being electrically connected to a first clock signal input terminal, the first electrode of the fourth transistor being electrically connected to a reference high-level signal input terminal, and the second electrode of the fourth transistor being electrically connected to the pull-down node.
[0010] Optionally, in some embodiments of this application, the first pull-down module includes a fifth transistor, the gate of which is electrically connected to the pull-up node, the first electrode of which is electrically connected to the first clock signal input terminal, and the second electrode of which is electrically connected to the pull-down node; the second pull-down module includes a sixth transistor, a seventh transistor, and a second capacitor, the gate of which is electrically connected to the pull-down node, the first electrode of which is electrically connected to the reference low-level signal input terminal, and the second electrode of which is electrically connected to the current stage scan signal output terminal; the gate of which is electrically connected to the pull-down node, the first electrode of which is electrically connected to the reference low-level signal input terminal, and the second electrode of which is electrically connected to the current stage cascade signal output terminal; the first plate of which is electrically connected to the pull-down node, and the second plate of which is electrically connected to the reference low-level signal input terminal.
[0011] Optionally, in some embodiments of this application, the pull-down sustaining module includes an eighth transistor and a ninth transistor. The gate of the eighth transistor is electrically connected to the pull-down node, the first electrode of the eighth transistor is electrically connected to a reference low-level signal input terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the ninth transistor. The gate of the ninth transistor is electrically connected to a second clock signal input terminal, and the second electrode of the ninth transistor is electrically connected to the pull-up node.
[0012] Optionally, in some embodiments of this application, the gate driving unit further includes a detection module, which is electrically connected to the pull-up node. The detection module is used to pull up the potential of the pull-up node in at least one stage of the gate driving unit after all the cascaded gate driving units have output the scan signal of the current stage. The scan signal output terminal outputs the scan compensation signal of the current stage under the control of the potential of the pull-up node.
[0013] Optionally, in some embodiments of this application, the detection module includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor. The gate of the tenth transistor is electrically connected to a selection signal input terminal, the first electrode of the tenth transistor is electrically connected to a previous stage transmission signal input terminal, and the second electrode of the tenth transistor is electrically connected to the gate of the eleventh transistor. The first electrode of the eleventh transistor is electrically connected to a reference high-level signal input terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor. Therefore, the gate of the twelfth transistor is electrically connected to a reset signal input terminal, and the second electrode of the twelfth transistor is electrically connected to the pull-up node. The first plate of the third capacitor is electrically connected to the gate of the eleventh transistor, and the second plate of the third capacitor is electrically connected to the first electrode of the eleventh transistor.
[0014] On the other hand, this application provides a display panel including pixel units and a gate driving circuit as described above, wherein the gate driving circuit is electrically connected to the pixel units.
[0015] The gate driving circuit and display panel provided in this application embodiment, through the above-described configuration, enable the control of the pull-up control module and the pull-down control module by controlling the potential of the first clock signal, thereby controlling the potential of the pull-up node, and controlling the potential of the pull-down node through the potential of the pull-up node. Simultaneously, the control of the pull-down sustaining module by controlling the potential of the second clock signal and the potential of the pull-down node, thereby controlling the potential of the pull-up node. In other words, the potentials of the pull-up node and the pull-down node can be controlled simply by controlling the potentials of the first clock signal and the second clock signal, greatly reducing the number of drive signal input terminals required for the gate driving unit, thus simplifying the structure of the gate driving circuit. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the gate driving circuit provided in an embodiment of this application;
[0017] Figure 2 This is a circuit diagram of the gate driving unit provided in the first embodiment of this application;
[0018] Figure 3 This is a circuit diagram of the gate driving unit provided in the second embodiment of this application;
[0019] Figure 4 yes Figure 3 The provided signal timing diagram for the gate drive unit. Detailed Implementation
[0020] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.
[0021] The various embodiments provided in this application are similar, and the features in different embodiments are combined with each other.
[0022] An embodiment of this application provides a display panel, including pixel units and a gate driving circuit, wherein the gate driving circuit is electrically connected to the pixel units.
[0023] Specifically, the display panel includes multiple pixel units arranged in an array and multiple scan lines. Each scan line is electrically connected to a row of pixel units. The gate driving circuit includes multiple cascaded gate driving units. Each gate driving unit is electrically connected to a scan line and is used to provide a scan signal to the corresponding scan line to control the thin-film transistors in the pixel units of the corresponding row to turn on.
[0024] The gate driving circuit in the display panel provided in the embodiments of this application can greatly reduce the number of driving signal input terminals that the gate driving unit needs to connect to, thereby simplifying the structure of the gate driving circuit and the display panel.
[0025] The transistors used in all embodiments of this application can be thin-film transistors or other devices with similar characteristics. To distinguish the two terminals of a transistor other than the gate, one of the source and drain is referred to as the first electrode, and the other of the source and drain is referred to as the second electrode. According to the configuration shown in the accompanying drawings, the middle input terminal of the transistor is the gate, the signal input terminal is the first electrode, and the signal output terminal is the second electrode. Furthermore, the transistors used in the embodiments of this application are P-type transistors or N-type transistors. A P-type transistor conducts when the gate is at a low potential and is cut off when the gate is at a high potential; an N-type transistor conducts when the gate is at a high potential and is cut off when the gate is at a low potential.
[0026] like Figure 1 As shown, the gate driving circuit provided in the embodiments of this application includes multiple cascaded gate driving units. Figure 1Take the cascaded gate drive unit GOA(N-1), the Nth gate drive unit GOA(N), and the N+1th gate drive unit GOA(N+1) as an example.
[0027] The (N-1)th stage gate driving unit GOA(N-1), the Nth stage gate driving unit GOA(N), and the (N+1)th stage gate driving unit GOA(N+1) are connected to scan lines G(N-1), G(N), and G(N+1), respectively. The Nth stage gate driving unit GOA(N) is connected to the stage-transfer scan signal Cout(N-1) output by the (N-1)th stage gate driving unit GOA(N-1), and correspondingly, the (N+1)th stage gate driving unit GOA(N+1) is connected to the stage-transfer signal Co output by the Nth stage gate driving unit GOA(N). ut(N), and so on; at the same time, the (N-1)th stage gate driving unit GOA(N-1) transmits the scan signal to the scan line G(N-1) connected to the (N-1)th stage gate driving unit GOA(N-1), the Nth stage gate driving unit GOA(N) transmits the scan signal to the scan line G(N) connected to the Nth stage gate driving unit GOA(N), the (N+1)th stage gate driving unit GOA(N+1) transmits the scan signal to the scan line G(N+1) connected to the (N+1)th stage gate driving unit GOA(N+1), and so on.
[0028] In this system, the first-stage gate driving unit GOA(1) transmits the scan signal to the first scan line G(1) connected to the first-stage gate driving unit GOA(1) in response to the start signal STV, and transmits the stage transmission signal Cout(1) to the second-stage gate driving unit GOA(2). It should be noted that the Nth-stage gate driving unit (N is a positive integer greater than 1) can transmit the scan signal to the Nth scan line G(N) and transmit the stage transmission signal Cout(N) to the (N+1)th-stage gate driving unit GOA(N+1).
[0029] The scan drive control signal input terminals include a first clock signal input terminal CK1, a second clock signal input terminal CK2, and a third clock signal input terminal CK3.
[0030] When the Nth-level gate driving unit is working, the scan signal output by the Nth-level gate driving unit GOA(N) is at a high potential, which is used to turn on the transistor switch of each pixel in a row of the display panel and charge the pixel electrode in each pixel through the data signal. The scan signal is used to control the operation of the (N+1)th-level gate driving unit. When the (N+1)th-level gate driving unit is working, the scan signal output by the (N+1)th-level gate driving unit GOA(N+1) is at a high potential, while the scan signal output by the Nth-level gate driving unit GOA(N) is at a low potential.
[0031] like Figure 2 As shown, the gate driving circuit provided in the embodiments of this application includes multiple cascaded gate driving units 100. Figure 2 The gate driving unit shown is a non-starting stage gate driving unit. The gate driving unit 100 includes: a pull-up control module 101, a pull-up node Q, a first output module 102, a second output module 103, a pull-down control module 104, a first pull-down module 105, a pull-down node P, a second pull-down module 106, and a pull-down maintenance module 107.
[0032] The pull-up control module 101 is electrically connected to the first clock signal input terminal CK1, the previous stage signal input terminal Cout(N-1), and the pull-up node Q. The pull-up control module 101 is used to pull up the potential of the pull-up node Q under the control of the first clock signal input at the first clock signal input terminal CK1.
[0033] The first output module 102 is electrically connected to the second clock signal input terminal CK2, the pull-up node Q, and the current level scan signal output terminal WR(N). The first output module 102 is used to output the current level scan signal under the control of the potential of the pull-up node Q.
[0034] The second output module 103 is electrically connected to the third clock signal input terminal CK3, the pull-up node Q, and the cascade signal output terminal Cout(N). The second output module 103 is used to output the cascade signal under the control of the potential of the pull-up node Q.
[0035] The pull-down control module 104 is electrically connected to the first clock signal input terminal CK1 and the pull-down node P. The pull-down control module 104 is used to pull the potential of the pull-down node P high under the control of the first clock signal.
[0036] The first pull-down module 105 is electrically connected to the first clock signal input terminal CK1, the pull-up node Q, and the pull-down node P. The first pull-down module 105 is used to pull down the potential of the pull-down node P to the potential of the first clock signal under the control of the potential of the pull-up node Q.
[0037] The second pull-down module 106 is electrically connected to the local scan signal output terminal WR(N), the local transmission signal output terminal Cout(N), and the pull-down node P. The second pull-down module 106 is used to pull down the potential of the local scan signal and the potential of the local transmission signal under the control of the potential of the pull-down node P.
[0038] The pull-down sustaining module 107 is electrically connected to the second clock signal input terminal CK2, the pull-up node Q, and the pull-down node P. The pull-down sustaining module 107 is used to keep the potential of the pull-up node Q at a low potential under the control of the second clock signal input at the second clock signal input terminal CK2 and the potential of the pull-down node P.
[0039] The gate driving circuit provided in the embodiments of this application can control the opening and closing of the pull-up control module 101 and the pull-down control module 104 by controlling the potential of the first clock signal, thereby controlling the potential of the pull-up node Q, and controlling the potential of the pull-down node P through the potential of the pull-up node Q. Simultaneously, the pull-down sustaining module 107 is controlled by controlling the potential of the second clock signal and the potential of the pull-down node P, thereby controlling the potential of the pull-up node Q. That is, the potentials of the pull-up node Q and the pull-down node P can be controlled by controlling the potentials of the first clock signal and the second clock signal, greatly reducing the number of drive signal input terminals required for the gate driving unit, thus simplifying the structure of the gate driving circuit.
[0040] like Figure 2 As shown, the pull-up control module 101 includes a first transistor T1. The gate of the first transistor T1 is electrically connected to the first clock signal input terminal CK1. The first electrode of the first transistor T1 is electrically connected to the previous stage signal input terminal Cout(N-1). The second electrode of the first transistor T1 is electrically connected to the pull-up node Q.
[0041] The first output module 102 includes a second transistor T2 and a first capacitor C1. The gate of the second transistor T2 is electrically connected to the pull-up node Q, the first electrode of the second transistor T2 is electrically connected to the second clock signal input terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the scan signal output terminal WR(N) of this stage. The first plate of the first capacitor C1 is electrically connected to the pull-up node Q, and the second plate of the first capacitor C1 is electrically connected to the scan signal output terminal WR(N) of this stage.
[0042] The second output module 103 includes a third transistor T3. The gate of the third transistor T3 is electrically connected to the pull-up node Q. The first electrode of the third transistor T3 is electrically connected to the third clock signal input terminal CK3. The second electrode of the third transistor T3 is electrically connected to the stage transmission signal output terminal Cout(N).
[0043] The pull-down control module 104 includes a fourth transistor T4. The gate of the fourth transistor T4 is electrically connected to the first clock signal input terminal CK1, the first electrode of the fourth transistor T4 is electrically connected to the reference high-level signal input terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the pull-down node P.
[0044] The first pull-down module 105 includes a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to the pull-up node Q, the first electrode of the fifth transistor T5 is electrically connected to the first clock signal input terminal CK1, and the second electrode of the fifth transistor T5 is electrically connected to the pull-down node P.
[0045] The second pull-down module 106 includes a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. The gate of the sixth transistor T6 is electrically connected to the pull-down node P, the first electrode of the sixth transistor T6 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the current stage scan signal output terminal WR(N). The gate of the seventh transistor T7 is electrically connected to the pull-down node P, the first electrode of the seventh transistor T7 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the seventh transistor T7 is electrically connected to the current stage cascade signal output terminal Cout(N). The first plate of the second capacitor C2 is electrically connected to the pull-down node P, and the second plate of the second capacitor C2 is electrically connected to the reference low-level signal input terminal VGL.
[0046] The pull-down sustaining module 107 includes an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 is electrically connected to the pull-down node P, the first electrode of the eighth transistor T8 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the eighth transistor T8 is electrically connected to the first electrode of the ninth transistor T9. The gate of the ninth transistor T9 is electrically connected to the second clock signal input terminal CK2, and the second electrode of the ninth transistor T9 is electrically connected to the pull-up node Q.
[0047] The gate driving circuit provided in the embodiments of this application can control the potential of the pull-up node Q and the potential of the pull-down node P by controlling the potential of the first clock signal and the potential of the second clock signal, which greatly reduces the number of thin film transistors required by the gate driving unit and the number of driving signal input terminals that need to be connected, thereby simplifying the structure of the gate driving circuit.
[0048] like Figure 3 As shown, the second type of gate driving unit provided in the embodiments of this application, the gate driving unit 200, differs from the gate driving unit 100 in that the gate driving unit 200 further includes a detection module 108.
[0049] The detection module 108 is electrically connected to the pull-up node Q, the previous stage signal input terminal Cout(N-1), and the reset signal input terminal Reset. The detection module 108 is used to pull up the potential of the pull-up node Q in at least one stage of the cascaded gate drive units after all stages have output their current scan signals. Therefore, the current scan signal output terminal WR(N) outputs the current scan compensation signal wr1 under the control of the potential of the pull-up node Q.
[0050] The pull-up control module 101 is electrically connected to the first clock signal input terminal CK1, the previous stage signal input terminal Cout(N-1), and the pull-up node Q. The pull-up control module 101 is used to pull up the potential of the pull-up node Q under the control of the first clock signal input at the first clock signal input terminal CK1.
[0051] The first output module 102 is electrically connected to the second clock signal input terminal CK2, the pull-up node Q, and the current level scan signal output terminal WR(N). The first output module 102 is used to output the current level scan signal under the control of the potential of the pull-up node Q.
[0052] The second output module 103 is electrically connected to the third clock signal input terminal CK3, the pull-up node Q, and the cascade signal output terminal Cout(N). The second output module 103 is used to output the cascade signal under the control of the potential of the pull-up node Q.
[0053] The pull-down control module 104 is electrically connected to the first clock signal input terminal CK1 and the pull-down node P. The pull-down control module 104 is used to pull the potential of the pull-down node P high under the control of the first clock signal.
[0054] The first pull-down module 105 is electrically connected to the first clock signal input terminal CK1, the pull-up node Q, and the pull-down node P. The first pull-down module 105 is used to pull down the potential of the pull-down node P to the potential of the first clock signal under the control of the potential of the pull-up node Q.
[0055] The second pull-down module 106 is electrically connected to the local scan signal output terminal WR(N), the local transmission signal output terminal Cout(N), and the pull-down node P. The second pull-down module 106 is used to pull down the potential of the local scan signal and the potential of the local transmission signal under the control of the potential of the pull-down node P.
[0056] The pull-down sustaining module 107 is electrically connected to the second clock signal input terminal CK2, the pull-up node Q, and the pull-down node P. The pull-down sustaining module 107 is used to keep the potential of the pull-up node Q at a low potential under the control of the second clock signal input at the second clock signal input terminal CK2 and the potential of the pull-down node P.
[0057] The gate driving circuit provided in the embodiments of this application can control the potential of the pull-up node Q and the pull-down node P by controlling the potential of the first clock signal and the potential of the second clock signal. This greatly reduces the number of thin-film transistors required for the gate driving unit and the number of driving signal input terminals that need to be connected, thereby simplifying the structure of the gate driving circuit. At the same time, by setting the detection module 108, external compensation can be performed on the pixel circuit of the pixel row corresponding to the gate driving unit, improving the stability of the pixel circuit.
[0058] like Figure 3As shown, the detection module 108 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a third capacitor C3. The gate of the tenth transistor T10 is electrically connected to the selection signal input terminal LSP. The first electrode of the tenth transistor T10 is electrically connected to the previous stage transmission signal input terminal Cout(N-1). The second electrode of the tenth transistor T10 is electrically connected to the gate of the eleventh transistor T11. The first electrode of the eleventh transistor T11 is electrically connected to the reference high-level signal input terminal VGH. The second electrode of the eleventh transistor T11 is electrically connected to the first electrode of the twelfth transistor T12. Therefore, the gate of the twelfth transistor T12 is electrically connected to the reset signal input terminal Reset. The second electrode of the twelfth transistor T12 is electrically connected to the pull-up node Q. The first plate of the third capacitor C3 is electrically connected to the gate of the eleventh transistor T11, and the second plate of the third capacitor C3 is electrically connected to the first electrode of the eleventh transistor T11.
[0059] The pull-up control module 101 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the first clock signal input terminal CK1, the first electrode of the first transistor T1 is electrically connected to the previous stage signal input terminal Cout(N-1), and the second electrode of the first transistor T1 is electrically connected to the pull-up node Q.
[0060] The first output module 102 includes a second transistor T2 and a first capacitor C1. The gate of the second transistor T2 is electrically connected to the pull-up node Q, the first electrode of the second transistor T2 is electrically connected to the second clock signal input terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the scan signal output terminal WR(N) of this stage. The first plate of the first capacitor C1 is electrically connected to the pull-up node Q, and the second plate of the first capacitor C1 is electrically connected to the scan signal output terminal WR(N) of this stage.
[0061] The second output module 103 includes a third transistor T3. The gate of the third transistor T3 is electrically connected to the pull-up node Q. The first electrode of the third transistor T3 is electrically connected to the third clock signal input terminal CK3. The second electrode of the third transistor T3 is electrically connected to the stage transmission signal output terminal Cout(N).
[0062] The pull-down control module 104 includes a fourth transistor T4. The gate of the fourth transistor T4 is electrically connected to the first clock signal input terminal CK1, the first electrode of the fourth transistor T4 is electrically connected to the reference high-level signal input terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the pull-down node P.
[0063] The first pull-down module 105 includes a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to the pull-up node Q, the first electrode of the fifth transistor T5 is electrically connected to the first clock signal input terminal CK1, and the second electrode of the fifth transistor T5 is electrically connected to the pull-down node P.
[0064] The second pull-down module 106 includes a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. The gate of the sixth transistor T6 is electrically connected to the pull-down node P, the first electrode of the sixth transistor T6 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the current stage scan signal output terminal WR(N). The gate of the seventh transistor T7 is electrically connected to the pull-down node P, the first electrode of the seventh transistor T7 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the seventh transistor T7 is electrically connected to the current stage cascade signal output terminal Cout(N). The first plate of the second capacitor C2 is electrically connected to the pull-down node P, and the second plate of the second capacitor C2 is electrically connected to the reference low-level signal input terminal VGL.
[0065] The pull-down sustaining module 107 includes an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 is electrically connected to the pull-down node P, the first electrode of the eighth transistor T8 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the eighth transistor T8 is electrically connected to the first electrode of the ninth transistor T9. The gate of the ninth transistor T9 is electrically connected to the second clock signal input terminal CK2, and the second electrode of the ninth transistor T9 is electrically connected to the pull-up node Q.
[0066] In the embodiments of this application, the gate drive circuit includes a first clock signal input terminal CK1, a second clock signal input terminal CK2, a third clock signal input terminal CK3, a previous stage transmission signal input terminal Cout(N-1), a reference high-level signal input terminal VGH, a reference low-level signal input terminal VGL, a selection signal input terminal LSP, and a reset signal input terminal Reset.
[0067] The circuit consists of the following components: First clock signal input CK1, which inputs the first clock signal ck1 to the gate drive unit; Second clock signal input CK2, which inputs the second clock signal ck2 to the gate drive unit; Third clock signal input CK3, which inputs the third clock signal ck3 to the gate drive unit; Previous stage transmission signal input Cout(N-1), which inputs the previous stage transmission signal cout(N-1) to the gate drive unit; Reference high level signal input VGH, which inputs the reference high level signal vgh to the gate drive unit; Reference low level signal input VGL, which inputs the reference low level signal vgl to the gate drive unit; Selection signal input LSP, which inputs the selection signal lsp to the gate drive unit; Reset signal input Reset, which inputs the reset signal reset to the gate drive unit; Current stage scan signal output WR(N), which outputs the current stage scan signal wr and the current stage scan compensation signal wr1 to the scan line; and Current stage transmission signal output Cout(N), which outputs the current stage transmission signal cout(N) to the next stage gate drive unit.
[0068] like Figure 3 and Figure 4 As shown, the driving timing of the gate driving unit includes a display period T01 and a blank period T02. During the display period T01, the gate driving unit outputs a scan signal to drive the display panel to display the image. During the blank period T02, the detection module 108 pulls up the potential of the pull-up node Q in at least one stage of the gate driving unit. Therefore, the scan signal output terminal WR(N) of this stage outputs a scan compensation signal wr1 under the control of the potential of the pull-up node Q, to perform threshold voltage compensation on the driving transistors in the pixel units within the display panel, i.e., to perform external compensation on the pixel units.
[0069] In the embodiments of this application, the phase of the first clock signal ck1 is opposite to the phase of the second clock signal ck2 during the display period T01, and the phase of the second clock signal ck2 is the same as the phase of the third clock signal ck3 input at the third clock signal input terminal CK3 during the display period T01.
[0070] Specifically, the display period T01 includes a first sub-display period t11, a second sub-display period t12, and a third sub-display period t13.
[0071] During the first sub-display period t11, the first clock signal ck1 is at a high level, the previous stage transmission signal cout(N-1) is at a high level, and the first transistor T1 and the fourth transistor T4 are turned on. The reference high-level signal vgh is transmitted to the pull-down node P through the fourth transistor T4, and the potential of the pull-down node P is pulled high. The previous stage transmission signal cout(N-1) is transmitted to the pull-up node Q through the first transistor T1, and the potential of the pull-up node Q is pulled high. The second transistor T2, the third transistor T3, and the fifth transistor T5 are turned on under the control of the potential of the pull-up node Q. In addition, the selection signal lsp is at a high level, and the potential of the previous stage transmission signal cout(N-1) is transmitted to the third capacitor C3 through the tenth transistor T10. The third capacitor C3 is used to store the potential of the previous stage transmission signal cout(N-1), and the eleventh transistor T11 is turned on.
[0072] During the second sub-display period t12, the first clock signal ck1 is transmitted to the pull-down node P through the fifth transistor T5, pulling the potential of the pull-down node P low. The second clock signal ck2 is at a high potential and is transmitted to the second plate of the first capacitor C1 through the second transistor T2, coupling the potential of the second plate to the first plate of the first capacitor C1. This causes the potential of the pull-up node Q to be raised a second time. The second clock signal ck2 is transmitted to the scan signal output terminal WR(N) of this stage through the second transistor T2 to output the scan signal of this stage. At the same time, the third clock signal ck3 is at a high potential and is transmitted to the cascade signal output terminal Cout(N) of this stage through the third transistor T3 to output the cascade signal of this stage. The cascade signal cout(N-1) of the previous stage and the selection signal lsp are at a low potential.
[0073] In the third sub-display stage, when the first clock signal ck1 is high, the fourth transistor T4 turns on. The reference high-level signal vgh is transmitted to the pull-down node P through the fourth transistor T4, and the potential of the pull-down node P remains high. The potential of the reference high-level signal vgh is stored in the second capacitor C2, which is used to maintain the potential of the pull-down node P. The high potential of the pull-down node P causes the sixth transistor T6 and the seventh transistor T7 to turn on. The reference low-level signal vgl is transmitted to the current stage scan signal output terminal WR(N) through the sixth transistor T6, and the potential of the current stage scan signal is pulled low, that is, the current stage gate drive unit stops outputting the current stage scan signal. At the same time, the reference low-level signal vgl is transmitted to the current stage cascade signal output terminal Cout(N) through the seventh transistor T7, and the potential of the current stage cascade signal is pulled low, that is, the current stage gate drive unit stops outputting the current stage cascade signal. A high potential at pull-down node P turns on the eighth transistor T8. A high potential at the second clock signal ck2 turns on the ninth transistor T9. The reference low-level signal vgl is transmitted to pull-up node Q through the eighth transistor T8 and the ninth transistor T9, pulling the potential of pull-up node Q low. At this time, the upstream transmission signal cout(N-1) remains low, keeping the potential of pull-up node Q low.
[0074] Specifically, the blank period T02 includes the first sub-blank period t21, the second sub-blank period t22, and the third sub-blank period t23.
[0075] In the embodiments of this application, the potentials of the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3 are the same in the first sub-blank period t21. The potentials of the first clock signal ck1 and the third clock signal ck3 are the same in the second sub-blank period t22, and the potentials of the second clock signal ck2 and the first clock signal ck1 are opposite in the second sub-blank period t22. The potentials of the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3 are the same in the third sub-blank period t23.
[0076] During the first sub-blank period t21, the upstream transmission signal cout(N-1), the first clock signal ck1, the second clock signal ck2, the third clock signal ck3, and the selection signal lsp are all at low potentials. The potential of the pull-down node P is pulled low by the continuous input of the reference low-level signal vgl, and the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.
[0077] When the reset signal is high, the twelfth transistor T12 turns on, and the eleventh transistor T11 remains on under the control of the potential of the third capacitor C3. The reference high-level signal vgh is transmitted to the pull-up node Q through the eleventh transistor T11 and the twelfth transistor T12. The potential of the pull-up node Q is pulled high, and the second transistor T2 turns on.
[0078] During the second sub-blank period t22, the reset signal is low, meaning charging of the pull-up node Q stops. The second clock signal ck2 is high and is transmitted to the scan signal output terminal WR(N) of this stage through the second transistor T2. The gate drive unit of this stage outputs the scan compensation signal wr1. Furthermore, the second clock signal ck2 is transmitted to the second plate of the first capacitor C1 through the second transistor T2, and the potential of the second plate is coupled to the first plate of the first capacitor C1, thereby causing the potential of the pull-up node Q to be raised a second time.
[0079] During the third sub-blank period t23, the preceding stage transmission signal cout(N-1), the first clock signal ck1, the second clock signal ck2, the third clock signal ck3, the selection signal lsp, and the reset signal are all at low potentials. The potential of the pull-up node Q decreases, and the output of the current stage scan compensation signal wr1 is cut off.
[0080] The above provides a detailed description of a gate driving circuit and a display panel provided in the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the core idea of this application, and the above description should not be construed as a limitation on the scope of protection of this application.
Claims
1. A gate driving circuit, characterized in that, The system includes a multi-stage cascaded gate driving unit, which includes a pull-up control module, a pull-up node, a first output module, a second output module, a pull-down control module, a first pull-down module, a pull-down node, a second pull-down module, and a pull-down sustaining module. The pull-up control module is electrically connected to the first clock signal input terminal and the pull-up node. The pull-up control module is used to pull up the potential of the pull-up node under the control of the first clock signal input to the first clock signal input terminal. The first output module is electrically connected to the second clock signal input terminal, the pull-up node, and the current scan signal output terminal. The first output module is used to output the current scan signal under the control of the potential of the pull-up node. The second output module is electrically connected to the third clock signal input terminal, the pull-up node, and the cascade signal output terminal of this stage. The second output module is used to output the cascade signal of this stage under the control of the potential of the pull-up node. The pull-down control module is electrically connected to the first clock signal input terminal and the pull-down node. The pull-down control module is used to pull the potential of the pull-down node high under the control of the first clock signal. The first pull-down module is electrically connected to the first clock signal input terminal, the pull-up node, and the pull-down node. The first pull-down module is used to pull the potential of the pull-down node down to the potential of the first clock signal under the control of the potential of the pull-up node. The second pull-down module is electrically connected to the local scan signal output terminal, the local transmission signal output terminal, and the pull-down node. The second pull-down module is used to pull down the potential of the local scan signal and the potential of the local transmission signal under the control of the potential of the pull-down node. The pull-down sustaining module is electrically connected to the second clock signal input terminal, the pull-up node, and the pull-down node. The pull-down sustaining module is used to keep the potential of the pull-up node at a low potential under the control of the second clock signal input to the second clock signal input terminal and the potential of the pull-down node.
2. The gate driving circuit according to claim 1, characterized in that, The phase of the first clock signal is opposite to the phase of the second clock signal, and the phase of the second clock signal is the same as the phase of the third clock signal input at the third clock signal input terminal.
3. The gate driving circuit according to claim 1 or 2, characterized in that, The pull-up control module includes a first transistor, the gate of the first transistor is electrically connected to a first clock signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal of the previous stage, and the second electrode of the first transistor is electrically connected to the pull-up node.
4. The gate driving circuit according to claim 1 or 2, characterized in that, The first output module includes a second transistor and a first capacitor. The gate of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the second clock signal input terminal, and the second electrode of the second transistor is electrically connected to the scan signal output terminal of the current stage. The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the output terminal of the scan signal of this stage. The second output module includes a third transistor, the gate of which is electrically connected to the pull-up node, the first electrode of which is electrically connected to the third clock signal input terminal, and the second electrode of which is electrically connected to the cascade signal output terminal of the same stage.
5. The gate driving circuit according to claim 1 or 2, characterized in that, The pull-down control module includes a fourth transistor, the gate of which is electrically connected to a first clock signal input terminal, the first electrode of which is electrically connected to a reference high-level signal input terminal, and the second electrode of which is electrically connected to the pull-down node.
6. The gate driving circuit according to claim 1 or 2, characterized in that, The first pull-down module includes a fifth transistor, the gate of which is electrically connected to the pull-up node, the first electrode of which is electrically connected to the first clock signal input terminal, and the second electrode of which is electrically connected to the pull-down node; The second pull-down module includes a sixth transistor, a seventh transistor, and a second capacitor. The gate of the sixth transistor is electrically connected to the pull-down node, the first electrode of the sixth transistor is electrically connected to the reference low-level signal input terminal, and the second electrode of the sixth transistor is electrically connected to the local scan signal output terminal. The gate of the seventh transistor is electrically connected to the pull-down node, the first electrode of the seventh transistor is electrically connected to the reference low-level signal input terminal, and the second electrode of the seventh transistor is electrically connected to the cascade signal output terminal of the same stage. The first plate of the second capacitor is electrically connected to the pull-down node, and the second plate of the second capacitor is electrically connected to the reference low-level signal input terminal.
7. The gate driving circuit according to claim 1 or 2, characterized in that, The pull-down sustaining module includes an eighth transistor and a ninth transistor. The gate of the eighth transistor is electrically connected to the pull-down node, the first electrode of the eighth transistor is electrically connected to a reference low-level signal input terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the ninth transistor. The gate of the ninth transistor is electrically connected to the second clock signal input terminal, and the second electrode of the ninth transistor is electrically connected to the pull-up node.
8. The gate driving circuit according to claim 1 or 2, characterized in that, The gate driving unit further includes a detection module, which is electrically connected to the pull-up node. The detection module is used to pull up the potential of the pull-up node in at least one stage of the gate driving unit after all the gate driving units in the multi-stage cascaded output the scan signal of their respective stage. The local scan signal output terminal outputs the local scan compensation signal under the control of the potential of the pull-up node.
9. The gate driving circuit according to claim 8, characterized in that, The detection module includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor. The gate of the tenth transistor is electrically connected to the selection signal input terminal, the first electrode of the tenth transistor is electrically connected to the signal input terminal of the previous stage, and the second electrode of the tenth transistor is electrically connected to the gate of the eleventh transistor. The first electrode of the eleventh transistor is electrically connected to the reference high-level signal input terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor. Therefore, the gate of the twelfth transistor is electrically connected to the reset signal input terminal, and the second electrode of the twelfth transistor is electrically connected to the pull-up node; The first plate of the third capacitor is electrically connected to the gate of the eleventh transistor, and the second plate of the third capacitor is electrically connected to the first electrode of the eleventh transistor.
10. A display panel, characterized in that, It includes a pixel unit and a gate driving circuit as described in any one of claims 1-9, wherein the gate driving circuit is electrically connected to the pixel unit.