Array substrate and display device

Abstract

The present application discloses an array substrate and a display device, comprising a substrate, a first metal layer, an intermediate insulating layer, a second metal layer, and a passivation layer. The first metal layer is located on the substrate and includes a metal trace, each of which includes at least two sub-traces spaced apart on the substrate. The intermediate insulating layer is located on the substrate and has at least two insulating portions spaced apart, with the sub-traces located between two adjacent insulating portions. The second metal layer is located on a surface of the intermediate insulating layer away from the substrate and includes a transition portion and two wall portions located on opposite sides of the transition portion. The transition portion is located on the intermediate insulating layer and contacts the sub-traces, while the wall portions contact the substrate. The passivation layer is located on a surface of the second metal layer away from the substrate. This prevents cracks from forming at the slope of the passivation layer, thereby improving product yield.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Currently, existing display devices require the second metal layer, which houses the Gate Driver on Array (GOA) circuitry, to be routed downward for bonding. Vertical traces within the display area consist solely of the LS layer (light sheild, the first metal layer, which can be made of copper). To ensure signal transmission, the LS layer, extending vertically from the AA region, must be connected to the second metal layer on the outer side of the substrate.

[0003] like Figure 1 As shown, the existing product includes a substrate 201, a first metal layer 202, a buffer layer 203, an intermediate insulating layer 204, a second metal layer 205 (M2 layer, which can be copper), and a passivation layer 206 (PV layer, which can be an inorganic silicon nitride layer). The first metal layer 202, buffer layer 203, intermediate insulating layer 204, second metal layer 205, and passivation layer 206 are sequentially arranged on the substrate 201 along the thickness direction of the substrate 201. The first metal layer 202 and the second metal layer 205 are electrically connected through holes provided in the buffer layer 203 and the intermediate insulating layer 204. Due to the influence of the morphology of the underlying first metal layer 202 and second metal layer 205, the passivation layer 206 has a large climbing step difference during production, resulting in cracks. Water vapor can easily enter through the cracks and corrode the metal, affecting product yield. Especially when conducting reliability testing on products, due to the high temperature and humidity in the test conditions, generally 60°C and 90% humidity are used. Under these conditions, the organic film inside the product will produce water vapor. If cracks occur in the protective inorganic layer at this time, the water vapor of the organic film will enter the cracks and corrode the metal, causing burns in the GOA area, resulting in bright lines and other problems in the product, seriously affecting the product yield. Summary of the Invention

[0004] The present application provides an array substrate and a display device to prevent cracks from occurring in an internal passivation layer at a slope.

[0005] In one aspect, an embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] a first metal layer, the first metal layer being located on the substrate, the first metal layer comprising a metal trace, and the metal trace comprising at least two sub-traces spaced apart and arranged on the substrate;

[0008] an intermediate insulating layer, the intermediate insulating layer being located on the substrate, the intermediate insulating layer having at least two insulating portions spaced apart from each other, wherein the sub-trace is located between two adjacent insulating portions;

[0009] a second metal layer, the second metal layer being located on a surface of the intermediate insulating layer away from the substrate, the second metal layer comprising a transition portion and two wall portions disposed on opposite sides of the transition portion, the transition portion being located on the intermediate insulating layer and in contact with the sub-trace, and the wall portions being in contact with the substrate; and

[0010] A passivation layer is located on a surface of the second metal layer away from the substrate.

[0011] Optionally, the transition portion of the second metal layer includes at least two concave portions spaced apart from each other, and positions of the concave portions correspond to positions of the sub-routing.

[0012] Optionally, the wall portion includes a horizontal portion provided on the substrate and a side wall portion inclined upward from the horizontal portion and toward the insulating portion to the transition portion.

[0013] Optionally, a length of the insulating portion in the thickness direction of the substrate is greater than a length of the sub-trace in the thickness direction of the substrate.

[0014] Optionally, a distance between a surface of the intermediate insulating layer away from the substrate and the substrate is between 0.3 micrometers and 0.42 micrometers.

[0015] Optionally, the distance between two adjacent sub-routes is greater than 5 microns.

[0016] Optionally, the length of the sub-trace in the longitudinal direction of the substrate is greater than 5 microns.

[0017] Optionally, a distance between an outer edge of the bottom of the intermediate insulating layer and an outer edge of the bottom of the adjacent sub-routing is greater than 3 microns.

[0018] Optionally, the array substrate has a display area and an outer area connected to the display area;

[0019] The first metal layer is disposed on the display area, and metal traces of the first metal layer extend from the display area into the outer area and are connected to the transition portion of the second metal layer.

[0020] On the other hand, the present application also provides a display device, which includes the above-mentioned array substrate.

[0021] The array substrate provided by the present application includes a substrate, a first metal layer, an intermediate insulating layer, a second metal layer, and a passivation layer; the first metal layer is located on the substrate, the first metal layer including a metal trace, the metal trace including at least two sub-traces spaced apart on the substrate; the intermediate insulating layer is located on the substrate, the intermediate insulating layer having at least two insulating portions spaced apart, wherein the sub-traces are located between two adjacent insulating portions; the second metal layer is located on a surface of the intermediate insulating layer away from the substrate, the second metal layer including a transition portion and two wall portions located on opposite sides of the transition portion, the transition portion being located on the intermediate insulating layer and in contact with the sub-traces, and the wall portions being in contact with the substrate; and the passivation layer is located on a surface of the second metal layer away from the substrate. Thus, the array substrate provided by the present application increases the distance between the outer edge of the intermediate insulating layer and the edge of the sub-traces, preventing the projection overlap of the metal layer wall portion and the metal trace sub-traces, thereby improving the slope difference during passivation layer preparation and solving the problem of crack formation at the slope of the passivation layer.

[0022] The display device provided in the present application adopts the above-mentioned array substrate, which can avoid the formation of cracks at the slope of the passivation layer, thereby avoiding the occurrence of cracks at the slope of the passivation layer and causing problems such as bright lines on the product, thereby improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a cross-sectional view of an existing array substrate;

[0024] Figure 2 is a cross-sectional view of an array substrate provided in an embodiment of the present application;

[0025] Figure 3 It is a partial schematic diagram of the array substrate provided in an embodiment of the present application.

[0026] Description of main component symbols

[0027] Existing technology:

[0028] 201 - substrate; 202 - first metal layer; 203 - buffer layer; 204 - intermediate insulating layer; 205 - second metal layer; 206 - passivation layer;

[0029] This application:

[0030] 100-array substrate; 101-outer area; 10-substrate; 20-first metal layer; 21-metal trace; 21a-sub-trace; 30-intermediate insulating layer; 31-insulating portion; 40-second metal layer; 41-transition portion; 41a-concave portion; 42-wall portion; 42a-horizontal portion; 42b-sidewall portion; 50-passivation layer. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0032] like Figure 2 and Figure 3 As shown, an embodiment of the present application provides an array substrate 100 , including a substrate 10 , a first metal layer 20 , an intermediate insulating layer 30 , a second metal layer 40 and a passivation layer 50 .

[0033] Specifically, the first metal layer 20 is located on the substrate 10, the first metal layer 20 includes a metal trace 21, and the metal trace 21 includes at least two sub-traces 21a spaced apart on the substrate 10; the intermediate insulating layer 30 is located on the substrate 10, and the intermediate insulating layer 30 has at least two insulating portions 31 spaced apart, wherein the sub-traces 21a are located between two adjacent insulating portions 31; the second metal layer 40 is located on a surface of the intermediate insulating layer 30 away from the substrate 10, the second metal layer 40 includes a transition portion 41 and two wall portions 42 arranged on opposite sides of the transition portion 41, the transition portion 41 is located on the intermediate insulating layer 30, and the transition portion 41 is in contact with the sub-traces 21a, and the wall portion 42 is in contact with the substrate 10; the passivation layer 50 is located on a surface of the second metal layer 40 away from the substrate 10.

[0034] The array substrate 100 provided in the embodiment of the present application is provided with a metal trace 21 including at least two sub-traces 21a spaced apart on the substrate 10, and an intermediate insulating layer 30 having at least two insulating portions 31 spaced apart, and the sub-traces 21a are located between two adjacent insulating portions 31. In this way, the metal trace 21 at the transition position can be made into a sub-traces 21a with a smaller width, and the second metal layer 40 to which it is transitioned covers the sub-traces 21a at the transition position, and an intermediate insulating layer 30 is provided between the two. In this way, when preparing the second metal layer 40, the wall portion 42 of the second metal layer 40 at the transition position only needs to be formed by climbing along the outer edge of the intermediate insulating layer 30, and when preparing the passivation layer 50, it also only needs to climb along the second metal layer 40. The array substrate 100 increases the distance between the edge of the intermediate insulating layer 30 and the edge of the sub-trace 21a, avoiding the projection overlap of the wall portion 42 of the second metal layer 40 and the sub-trace 21a of the metal trace 21, thereby improving the climbing step difference during the preparation of the passivation layer 50 and solving the problem of cracks forming at the climbing portion of the passivation layer 50.

[0035] See also Figure 2 and Figure 3The array substrate 100 provided in this embodiment includes a display area (not shown) and an outer area 101. The outer area 101 is connected to the display area and is located on one side of the display area. It can also be on both sides or any one or more sides of the periphery of the display area.

[0036] See also Figure 2 and Figure 3 The array substrate 100 provided in this embodiment includes a substrate 10 and a first metal layer 20, an intermediate insulating layer 30, a second metal layer 40, and a passivation layer 50 formed thereon. The substrate 10 can be made of materials such as quartz or glass, or can also be made of a flexible material. The material of the substrate 10 can be transparent, translucent, or opaque.

[0037] See also Figure 2 and Figure 3 The first metal layer 20 provided in this embodiment is a film layer made of an opaque material. It can be copper (Cu), or a single-layer or multi-layer structure of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or their alloys, but is not limited to these structures. The first metal layer 20 acts as a light shield in the display area, which can improve the contrast of the display screen, prevent color mixing between adjacent color layers, reduce external light reflection, and prevent external light from irradiating the amorphous silicon layer of the TFT (Thin Film Transistor) device and increasing leakage current. In this embodiment, the first metal layer 20 is, but is not limited to, a film layer made of copper. The first metal layer 20 includes a plurality of strip-shaped metal traces 21 arranged on the display area of ​​the substrate 10. The plurality of metal traces 21 can be arranged to cover the display area, and each metal trace 21 extends from the display area to the outer area 101.

[0038] It is worth mentioning that the number of transition parts 41 in the second metal layer 40 corresponds to the number of metal traces 21 in the first metal layer 20. Each metal trace 21 is electrically connected to the corresponding transition part 41 of the second metal layer 40, and wall parts 42 are provided on both sides of the opposite sides of the transition part 41.

[0039] In another embodiment, the metal trace 21 may also be a structure covering the entire surface of the display area of ​​the substrate 10 .

[0040] See also Figure 2 and Figure 3 The sub-routing 21a provided in this embodiment may only be the portion of the metal routing 21 located in the outer area 101. The metal routing 21 includes at least two sub-routings 21a spaced apart from each other. In this embodiment, the number of sub-routings 21a in each metal routing 21 is two, but not limited to two, and a predetermined spacing is left between the two sub-routings 21a.

[0041] More preferably, the two sub-routes 21a provided in this embodiment are parallel to each other, and the two sub-routes 21a are arranged at intervals in the length direction of the substrate 10. The length direction of the substrate 10 can be perpendicular to the extension direction of each sub-routes 21a or at a preset angle.

[0042] In another embodiment, the number of the sub-routes 21 a of the metal trace 21 may be three or more. The number of the sub-routes 21 a may be selected according to the width of the metal trace 21 in the outer region 101 (ie, the length in the longitudinal direction of the substrate 10 ).

[0043] See also Figure 2 and Figure 3 In the first metal layer 20 provided in this embodiment, the spacing between the two sub-traces 21a needs to be greater than 5 microns. In this way, during the manufacturing process of the array substrate 100, the edges of the sub-traces 21a will not be damaged due to the small spacing between the two.

[0044] See also Figure 2 and Figure 3 In the first metal layer 20 provided in this embodiment, the length of the sub-trace 21a in the length direction of the substrate is greater than 5 microns. In this way, it can be avoided that the contact area between the sub-trace 21a of the metal trace 21 and the second metal layer 40 is too small, resulting in an increase in contact impedance, thereby affecting product performance.

[0045] See also Figure 2 and Figure 3 The intermediate insulating layer 30 provided in this embodiment is located on the side of the first metal layer 20 away from the substrate 10. The intermediate insulating layer 30 (ILD) is formed on the entire surface of the display area including the first metal layer 20. The intermediate insulating layer 30 can be formed of an inorganic insulating material, such as a single-layer structure or a multi-layer structure of SiO2 (silicon dioxide), SiNx (silicon nitride), or SiON (silicon oxynitride), but is not limited to these structures. In this embodiment, the intermediate insulating layer 30 located in the outer area 101 of the array substrate 100 has an insulating portion 31, and the sub-trace 21a is located between two adjacent insulating portions 31.

[0046] It's worth noting that the intermediate insulating layer 30 directly contacts the outer surface of the sub-trace 21a. During fabrication, a buffer layer (not shown) is retained in the display area. The buffer layer in the outer region 101 can be removed using an existing mold. This allows the intermediate insulating layer 30 to be directly formed on the substrate 10 and the sub-trace 21a. This allows the average thickness of the intermediate insulating layer 30 (i.e., the distance between the surface of the intermediate insulating layer 30 facing away from the substrate 10 and the substrate 10) to be between 0.3 microns and 0.42 microns. In other words, the transition structure provided on the array substrate 100 is located in the outer region 101 of the array substrate 100. The transition structure is comprised of the substrate 10, the first metal layer 20, the intermediate insulating layer 30, the second metal layer 40, and the passivation layer 50. Furthermore, a planarization layer can be provided on the transition structure, located on the side of the passivation layer 50 facing away from the substrate 10. This allows the overall thickness of the intermediate insulating layer 30 to be reduced after fabrication, thereby reducing the slope height during fabrication of the second metal layer 40 and the passivation layer 50.

[0047] See also Figure 2 and Figure 3 The intermediate insulating layer 30 provided in this embodiment has a spacing greater than 3 microns between the outer edge of its bottom and the outer edge of the bottom of the adjacent sub-trace 21a. In this way, it can be ensured that the projection of the outer edge of the intermediate insulating layer 30 on the substrate 10 along the thickness direction of the substrate 10 and the projection of the outer edge of the adjacent sub-trace 21a on the substrate 10 along the thickness direction of the substrate 10 are staggered.

[0048] See also Figure 2 and Figure 3 The second metal layer 40 provided in this embodiment is located on the side of the intermediate insulating layer 30 away from the substrate 10. The second metal layer 40 is a film layer made of a metal material. It can be made of the same material as the first metal layer 20 or a different material. The second metal layer 40 can be copper (Cu), or it can be a single-layer structure or a multi-layer structure of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or their alloys, but is not limited to these structures.

[0049] See also Figure 2 and Figure 3The second metal layer 40 provided in this embodiment includes a driving circuit of the array substrate 100. The second metal layer 40 is electrically connected to the sub-track 21a of the metal track 21 of the first metal layer 20 in the outer area 101 of the array substrate 100. In this embodiment, the second metal layer 40 includes a transition portion 41 and two wall portions 42 respectively arranged on opposite sides of the transition portion 41. The intermediate insulating layer 30 has an insulating portion 31 for the transition portion 41 to contact the sub-track 21a respectively. Through the insulating portion 31 on the intermediate insulating layer 30, the transition portion 41 of the second metal layer 40 contacts the sub-track 21a of the metal track 21 and can realize the transmission of electrical signals.

[0050] See also Figure 2 and Figure 3 In this embodiment, the sub-trace 21a is located between two adjacent insulating portions 31. In this way, the wall portion 42 of the second metal layer 40 does not overlap with the projection of the sub-trace 21a on the substrate 10. When preparing the second metal layer 40 and the passivation layer 50, they will not be affected by the slope of the edge of the connected sub-trace 21a, thereby reducing the climbing height of the second metal layer 40 and the passivation layer 50, thereby optimizing product performance.

[0051] See also Figure 2 and Figure 3 In the second metal layer 40 of this embodiment, the transition portion 41 includes at least two spaced-apart recessed portions 41a, the positions of which correspond to the positions of the sub-routings 21a. In the second metal layer 40 of this embodiment, the number of recessed portions 41a of the transition portion 41 is, but is not limited to, two, corresponding one-to-one to the two sub-routings 21a. In the length direction of the substrate 10, the length dimension of the recessed portions 41a of the transition portion 41 can be slightly shorter than the length dimension of the sub-routings 21a in this direction. It is easy to understand that the size of the insulating portion 31 on the intermediate insulating layer 30 corresponds to the size of the recessed portions 41a of the transition portion 41 of the second metal layer 40. If the size of the insulating portion 31 on the intermediate insulating layer 30 is larger than the length dimension of the sub-routings 21a in the side-by-side direction, it is easy to cause damage to the sidewalls of the sub-routings 21a.

[0052] See also Figure 2 and Figure 3 In this embodiment, the passivation layer 50 is located on the side of the second metal layer 40 away from the substrate 10. The passivation layer 50 can be formed of an inorganic insulating material, and more specifically, can be formed as a single-layer structure or a multi-layer structure of SiO2 (silicon dioxide), SiNx (silicon nitride), or SiON (silicon oxynitride), but is not limited to these structures.

[0053] In this embodiment, the array substrate 100 further includes a planarization layer (not shown) located on a side of the passivation layer 50 away from the substrate 10. The planarization layer is formed on the passivation layer 50. The planarization layer is arranged to planarize the surface of the array substrate 100. The planarization layer can be formed of an organic insulating material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0054] See also Figure 2 and Figure 3 In this embodiment, each wall portion 42 of the second metal layer 40 includes a horizontal portion 42a disposed on the substrate 10 and a sidewall portion 42b that slopes upward and inward from the horizontal portion 42a to the transition portion 41. Thus, the wall portion 42 of the second metal layer 40 includes the horizontal portion 42a directly formed on the substrate 10 and the sidewall portion 42b that slopes directly formed on the sloped surface of the intermediate insulating layer 30. The passivation layer 50 covers the surface of the horizontal portion 42a, the surface of the sidewall portion 42b, and the surface of the transition portion 41 of the wall portion 42 of the second metal layer 40. This can reduce the impact on the deposition of the passivation layer 50 during the process of preparing the passivation layer 50 on the second metal layer 40, improve the climbing step difference during the preparation of the passivation layer 50, and solve the problem of cracks forming at the climbing portion of the passivation layer 50, thereby avoiding the occurrence of bright line defects during reliability testing of the product.

[0055] The display device provided in this embodiment includes the above-mentioned array substrate 100. The display device adopts the above-mentioned array substrate 100, which can avoid the problem of cracks forming at the slope of the passivation layer 50.

[0056] The above is a detailed introduction to an array substrate and a display device provided by the embodiments of the present application. The description of the above embodiments is only used to help understand the core idea of ​​the present application, and the above description should not be understood as limiting the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; a first metal layer, the first metal layer being located on the substrate, the first metal layer comprising a metal trace, and the metal trace comprising at least two sub-traces spaced apart and arranged on the substrate; an intermediate insulating layer, the intermediate insulating layer being located on the substrate, the intermediate insulating layer having at least two insulating portions spaced apart from each other, wherein the sub-trace is located between two adjacent insulating portions; a second metal layer, the second metal layer being located on a surface of the intermediate insulating layer away from the substrate, the second metal layer comprising a transition portion and two wall portions disposed on opposite sides of the transition portion, the transition portion being located on the intermediate insulating layer and in contact with the sub-trace, and the wall portions being in contact with the substrate; and A passivation layer is located on a surface of the second metal layer away from the substrate.

2. The array substrate according to claim 1, wherein: The transition portion of the second metal layer includes at least two concave portions spaced apart from each other, and positions of the concave portions correspond to positions of the sub-routing.

3. The array substrate according to claim 1, wherein: The wall portion includes a horizontal portion provided on the substrate and a side wall portion inclined upward from the horizontal portion and toward the insulating portion to the transition portion.

4. The array substrate according to claim 1, wherein: The length of the insulating portion in the thickness direction of the substrate is greater than the length of the sub-trace in the thickness direction of the substrate.

5. The array substrate according to claim 1, wherein: A distance between a surface of the intermediate insulating layer away from the substrate and the substrate is between 0.3 micrometers and 0.42 micrometers.

6. The array substrate according to claim 1, wherein: The distance between two adjacent sub-routes is greater than 5 microns.

7. The array substrate according to claim 1, wherein: The length of the sub-trace in the longitudinal direction of the substrate is greater than 5 microns.

8. The array substrate according to claim 1, wherein: The distance between the outer edge of the bottom of the middle insulating layer and the outer edge of the bottom of the adjacent sub-trace is greater than 3 micrometers.

9. The array substrate according to claim 1, wherein: The array substrate comprises a display area and an outer area connected to the display area; The first metal layer is disposed on the display area, and a metal trace of the first metal layer extends from the display area into the outer area and is connected to a transfer portion of the second metal layer.

10. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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