Array substrate and display panel

Abstract

An embodiment of the present invention discloses an array substrate and a display panel; the array substrate includes a substrate, pixel units, scan lines extending along a first direction, and a first type of signal line extending along a second direction, each pixel unit includes a main pixel area and a sub-pixel area, the pixel unit also includes a thin film transistor, the scan line is located between the main pixel area and the sub-pixel area, the first type of signal line and the thin film transistor are located between the first main pixel sub-area and the second main pixel sub-area of ​​the main pixel area, and the present invention reduces the light-transmitting area occupied by the signal lines in the array substrate, improves the aperture ratio of the array substrate, improves the transmittance of the display panel using the array substrate, and reduces the manufacturing cost and power consumption of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] Currently, if Figure 1 As shown, the array substrate 100' controls a row of pixel units via a row of horizontally extending scan lines 105'. A row of vertically extending data lines 113' provides data signals to the pixel units, enabling independent control of the pixel units. A vertically extending shared electrode line (Sharebar) 112' vertically passes through the primary pixel region 103' and secondary pixel region 104' of each pixel unit. Because the areas corresponding to signal lines such as the scan lines, data lines, and shared electrode lines are opaque, the light-transmitting area of ​​the pixel units in the array substrate is reduced, lowering the aperture ratio of the array substrate. This creates a technical problem of difficulty in improving the transmittance of a display panel using the array substrate.

[0003] Furthermore, unlike the aforementioned single-gate array substrate, where pixels of different colors are alternately arranged horizontally when a row of horizontally extending scan lines and a row of vertically extending data lines control the pixels, a tri-gate array substrate alternates the pixels of different colors vertically, achieving lower costs and lower power consumption at the same resolution. However, the number of scan lines in a tri-gate array substrate is three times that of a single-gate array substrate at the same resolution, and the scan lines are arranged between the pixels, which also reduces the aperture ratio of the tri-gate array substrate. This creates a technical problem that it is difficult to improve the transmittance of a display panel using a tri-gate array substrate.

[0004] Therefore, an array substrate and a display panel are urgently needed to solve the above technical problems. Summary of the Invention

[0005] The present invention provides an array substrate and a display panel, which can alleviate the technical problem that the transmittance of a display panel using the array substrate is difficult to improve due to the low light transmission area of ​​pixel units in the current array substrate.

[0006] The present invention provides an array substrate, comprising:

[0007] substrate;

[0008] A plurality of pixel units, wherein the plurality of pixel units are distributed on one side of the substrate, each of the pixel units includes a primary pixel region and a secondary pixel region, and each of the pixel units further includes a pixel electrode located in the primary pixel region and the secondary pixel region;

[0009] a scan line extending along a first direction, wherein the scan line is located between the primary pixel region and the secondary pixel region;

[0010] a first type of signal line extending along a second direction, wherein the first direction intersects the second direction;

[0011] The primary pixel region includes a first primary pixel sub-region and a second primary pixel sub-region arranged along the first direction, the secondary pixel region includes a first secondary pixel sub-region and a second secondary pixel sub-region arranged along the first direction, the first primary pixel sub-region and the first secondary pixel sub-region are arranged along the second direction, and the second primary pixel sub-region and the second secondary pixel sub-region are arranged along the second direction;

[0012] The first type of signal line is located between the first main pixel sub-region and the second main pixel sub-region;

[0013] Each of the pixel units also includes multiple thin film transistors, which are electrically connected to the scan lines and the first type of signal lines. The thin film transistors are located between the first main pixel sub-area and the second main pixel sub-area. The pixel electrode in the first main pixel sub-area and the pixel electrode in the second main pixel sub-area are connected to the same thin film transistor, and the pixel electrode in the first pixel sub-area and the pixel electrode in the second pixel sub-area are connected to the same thin film transistor.

[0014] In some embodiments, the array substrate further includes a data line extending along the second direction;

[0015] The pixel electrode includes a first trunk electrode extending along the second direction, and an orthographic projection of the first trunk electrode on the substrate is at least partially located within an orthographic projection of the data line on the substrate.

[0016] In some embodiments, the first trunk electrode includes a first subsegment located in the first main pixel sub-region, a second subsegment located in the second main pixel sub-region, a third subsegment located in the first primary pixel sub-region, and a fourth subsegment located in the second secondary pixel sub-region;

[0017] The data lines include a first type of data lines and a second type of data lines, the orthographic projection of the first sub-segment on the substrate is at least partially located within the orthographic projection of the first type of data lines on the substrate, and the orthographic projection of the third sub-segment on the substrate is at least partially located within the orthographic projection of the first type of data lines on the substrate, the orthographic projection of the second sub-segment on the substrate is at least partially located within the orthographic projection of the second type of data lines on the substrate, and the orthographic projection of the fourth sub-segment on the substrate is at least partially located within the orthographic projection of the second type of data lines on the substrate.

[0018] In some embodiments, the pixel unit includes a first pixel unit and a second pixel unit, the first pixel unit and the second pixel unit are alternately arranged along the second direction, the first pixel unit is electrically connected to the first type of data line, the second pixel unit is electrically connected to the second type of data line, and the array substrate further includes a first common electrode line;

[0019] The voltage difference between the first type of data line and the first common electrode line is opposite in polarity to the voltage difference between the second type of data line and the first common electrode line.

[0020] In some embodiments, the first type of signal lines are shared electrode lines.

[0021] In some embodiments, the array substrate further includes a shared electrode line, and the shared electrode line is disposed around the pixel unit.

[0022] In some embodiments, the array substrate further includes a first common electrode line, the first common electrode line extending along the first direction, the first common electrode line and the scan line being in the same layer and spaced apart;

[0023] The first common electrode line includes a first sub-portion and a second sub-portion arranged along the second direction, and the first sub-portion and the second sub-portion are respectively located on two opposite sides of the pixel unit.

[0024] In some embodiments, the shared electrode line is disposed around the pixel unit, and the shared electrode line includes a third sub-portion and a fourth sub-portion arranged along the second direction, and the third sub-portion and the fourth sub-portion extend along the first direction respectively;

[0025] In which, the third sub-section and the fourth sub-section are respectively located on opposite sides of the pixel unit, the orthographic projection of the third sub-section on the substrate is at least partially located within the orthographic projection of the first sub-section on the substrate, and the orthographic projection of the fourth sub-section on the substrate is at least partially located within the orthographic projection of the second sub-section on the substrate.

[0026] In some embodiments, the first type of signal lines are data lines.

[0027] In some embodiments, in each of the pixel units, the thin film transistor is located on a side of the first type signal line close to the first main pixel sub-region, or the thin film transistor is located on a side of the first type signal line close to the second main pixel sub-region;

[0028] Wherein, the thin film transistor includes a first thin film transistor, a second thin film transistor and a third thin film transistor;

[0029] The gate of the first thin film transistor is electrically connected to the scan line, the source of the first thin film transistor is electrically connected to the data line, and the drain of the first thin film transistor is electrically connected to the pixel electrode in the main pixel area;

[0030] The gate of the second thin film transistor is electrically connected to the scan line, the source of the second thin film transistor is electrically connected to the data line, and the drain of the second thin film transistor is electrically connected to the pixel electrode in the sub-pixel area;

[0031] The gate of the third thin film transistor is electrically connected to the scan line, the source of the third thin film transistor is electrically connected to the drain of the second thin film transistor, and the drain of the third thin film transistor is electrically connected to the shared electrode line.

[0032] In some embodiments, the scan line, the gate of the first thin film transistor, the gate of the second thin film transistor, and the gate of the third thin film transistor are integrally provided.

[0033] The present invention further provides a display panel, comprising the array substrate as described above.

[0034] The present invention arranges the scanning line between the main pixel area and the sub-pixel area, and arranges the first type of signal line and the thin film transistor between the first main pixel sub-area and the second main pixel sub-area, thereby reducing the light-transmitting area occupied by the signal line in the array substrate, improving the aperture ratio of the array substrate, and improving the transmittance of the display panel using the array substrate, and reducing the manufacturing cost and power consumption of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 This is a structural diagram of an existing array substrate;

[0037] Figure 2 This is a structural diagram of a structure of an array substrate provided by an embodiment of the present invention;

[0038] Figure 3 is a structural diagram of a first structure of a pixel unit of an array substrate provided by an embodiment of the present invention;

[0039] Figure 4 yes Figure 3 A schematic structural diagram of a structure of a first metal layer in a provided array substrate;

[0040] Figure 5 yes Figure 3 A schematic structural diagram of a structure of a second metal layer in a provided array substrate;

[0041] Figure 6 yes Figure 3 A schematic structural diagram of a structure of a pixel electrode layer in a provided array substrate;

[0042] Figure 7 is a structural diagram of a second structure of a pixel unit of an array substrate provided by an embodiment of the present invention;

[0043] Figure 8 1 is a schematic structural diagram of a third structure of a pixel unit of an array substrate provided by an embodiment of the present invention;

[0044] Figure 9 1 is a schematic structural diagram of a fourth structure of a pixel unit of an array substrate provided by an embodiment of the present invention;

[0045] Figure 10 yes Figure 9 A schematic structural diagram of a structure of a second metal layer in a provided array substrate;

[0046] Figure 11 is a structural diagram of a fifth structure of a pixel unit of an array substrate provided by an embodiment of the present invention;

[0047] Figure 12 It is a structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0049] At present, since the areas corresponding to signal lines such as scan lines, data lines, and shared electrode lines are not light-transmitting, the light-transmitting area of ​​the pixel units in the array substrate is small and the aperture ratio of the array substrate is low, there is a technical problem that it is difficult to improve the transmittance of the display panel using the array substrate.

[0050] See also Figures 2 to 11 , an embodiment of the present invention provides an array substrate 100, comprising:

[0051] substrate 101;

[0052] A plurality of pixel units 102 , each of the pixel units 102 being distributed on one side of the substrate 101 , each of the pixel units 102 including a primary pixel region 103 and a secondary pixel region 104 , and each of the pixel units 102 further including a pixel electrode 114 located within the primary pixel region 103 and the secondary pixel region 104 ;

[0053] a scan line 105 extending along a first direction X, wherein the scan line 105 is located between the primary pixel region 103 and the secondary pixel region 104;

[0054] A first-type signal line 106 extending along a second direction Y, wherein the first direction X intersects the second direction Y;

[0055] The primary pixel region 103 includes a first primary pixel sub-region 107 and a second primary pixel sub-region 108 arranged along the first direction X, and the secondary pixel region 104 includes a first primary pixel sub-region 109 and a second secondary pixel sub-region 110 arranged along the first direction X. The first primary pixel sub-region 107 and the first primary pixel sub-region 109 are arranged along the second direction Y, and the second primary pixel sub-region 108 and the second secondary pixel sub-region 110 are arranged along the second direction Y.

[0056] The first type of signal line 106 is located between the first main pixel sub-region 107 and the second main pixel sub-region 108;

[0057] Each pixel unit 102 further includes a thin film transistor 111 . The thin film transistor 111 is electrically connected to the scan line 105 and the first type signal line 106 . The thin film transistor 111 is located between the first primary pixel sub-region 107 and the second primary pixel sub-region 108 .

[0058] The array substrate 100 provided in an embodiment of the present invention can be a three-gate array substrate, in which the scan line 105 is arranged between the main pixel area 103 and the sub-pixel area 104, thereby reducing the occupation of the light-transmitting area by the scan line 105. Compared with the existing three-gate array substrate, the aperture ratio is effectively improved; at the same time, compared with the existing single-gate array substrate, the aperture ratio is effectively improved while reducing costs and power consumption.

[0059] In the embodiment of the present invention, the scanning line 105 is arranged between the main pixel area 103 and the sub-pixel area 104, and the first type of signal line 106 and the thin film transistor 111 are arranged between the first main pixel sub-area 107 and the second main pixel sub-area 108. This reduces the light-transmitting area occupied by the signal line in the array substrate 100, increases the light-transmitting area of ​​the pixel unit 102, improves the aperture ratio of the array substrate 100, improves the transmittance of the display panel using the array substrate 100, and reduces the manufacturing cost and power consumption of the display panel.

[0060] The technical solution of the present invention will now be described in conjunction with specific embodiments.

[0061] See also Figure 3 、 Figures 7 to 11 In this embodiment, when the scan line 105 is located between the main pixel area 103 and the sub-pixel area 104, the scan line 105 is located between the first main pixel sub-area 107 and the first sub-pixel sub-area 109, and the scan line 105 is located between the second main pixel sub-area 108 and the second sub-pixel sub-area 110.

[0062] When the first-type signal line 106 is located between the first primary pixel sub-region 107 and the second primary pixel sub-region 108 , the first-type signal line 106 is also located between the first secondary pixel sub-region 109 and the second secondary pixel sub-region 110 .

[0063] When the thin film transistor 111 is located between the first primary pixel sub-region 107 and the second primary pixel sub-region 108, the thin film transistor 111 is also located between the first primary pixel sub-region 109 and the second secondary pixel sub-region 110. Within each of the pixel units 102, the thin film transistor 111 can be located on a side of the first-type signal line 106 close to the first primary pixel sub-region 107. Alternatively, within each of the pixel units 102, the thin film transistor 111 can be located on a side of the first-type signal line 106 close to the second primary pixel sub-region 108.

[0064] See also Figure 3 ,and Figures 7 to 11In some embodiments, the thin film transistor 111 includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3. The gate of the first thin film transistor T1 is electrically connected to the scan line 105, the source of the first thin film transistor T1 is electrically connected to the data line 113, and the drain of the first thin film transistor T1 is electrically connected to the pixel electrode 114 in the primary pixel area 103. The gate of the second thin film transistor T2 is electrically connected to the scan line 105, the source of the second thin film transistor T2 is electrically connected to the data line 113, and the drain of the second thin film transistor T2 is electrically connected to the pixel electrode 114 in the secondary pixel area 104. The gate of the third thin film transistor T3 is electrically connected to the scan line 105, the source of the third thin film transistor T3 is electrically connected to the drain of the second thin film transistor T2, and the drain of the third thin film transistor T3 is electrically connected to the shared electrode line 112. The first thin-film transistor T1 controls the pixel electrode 114 in the main pixel area 103, and the second thin-film transistor T2 and the third thin-film transistor T3 jointly control the pixel electrode 114 in the sub-pixel area 104, so that the potential of the pixel electrode 114 in the main pixel area 103 and the pixel electrode 114 in the sub-pixel area 104 are different, thereby independently controlling the bias voltage of the pixel electrode 114 in the sub-pixel area 104, which is beneficial to reducing the color shift of the display panel using the array substrate 100 and improving the display quality of the display panel.

[0065] In some embodiments, the first direction X may be a row direction, and the second direction Y may be a column direction. Each row of the pixel units 102 is electrically connected to the same scan line 105 .

[0066] See also Figure 3 、 Figures 7 to 9 In some embodiments, the first type of signal line 106 is a shared electrode line 112. By setting the shared electrode line 112 between the first main pixel sub-region 107 and the second main pixel sub-region 108, compared with extending the shared electrode line 112 into the main pixel region 103 and the sub-pixel region 104, the shared electrode line 112 reduces the occupation of the light-transmitting area of ​​the pixel unit 102, thereby improving the aperture ratio of the array substrate 100 and thereby improving the transmittance of the display panel using the array substrate 100.

[0067] In some embodiments, the array substrate 100 further includes a data line 113 extending along the second direction Y. The thin film transistor 111 is electrically connected to the data line 113. In this case, the first type signal line 106 may be the shared electrode line 112.

[0068] Each pixel unit 102 further includes a pixel electrode 114 located in the primary pixel region 103 and the secondary pixel region 104 . The pixel electrode 114 includes a primary pixel electrode located in the primary pixel region 103 and a secondary pixel electrode located in the secondary pixel region 104 .

[0069] In some embodiments, the pixel electrode 114 includes a first trunk electrode 115 extending along the second direction Y, and the orthographic projection of the first trunk electrode 115 on the substrate 101 is at least partially located within the orthographic projection of the data line 113 on the substrate 101. This reduces the light-transmitting area of ​​the array substrate 100 occupied by the data line 113, thereby improving the aperture ratio of the array substrate 100.

[0070] In some embodiments, the orthographic projection of the first trunk electrode 115 on the substrate 101 is located within the orthographic projection of the data line 113 on the substrate 101. Alternatively, the orthographic projection of the portion of the data line 113 located within the pixel unit 102 on the substrate 101 is located within the orthographic projection of the first trunk electrode 115 on the substrate 101.

[0071] In some embodiments, the primary pixel electrode includes a first primary pixel electrode located in the first primary pixel sub-region 107 and a second primary pixel electrode located in the second primary pixel sub-region 108. The secondary pixel electrodes include a first primary pixel electrode located in the first secondary pixel sub-region 109 and a second secondary pixel electrode located in the second secondary pixel sub-region 110.

[0072] The first main electrode 115 includes a first subsegment 115a located in the first primary pixel sub-region 107, a second subsegment 115b located in the second primary pixel sub-region 108, a third subsegment 115c located in the first secondary pixel sub-region 109, and a fourth subsegment 115d located in the second secondary pixel sub-region 110. That is, the first primary pixel electrode includes the first subsegment 115a, the second primary pixel electrode includes the second subsegment 115b, the first primary pixel electrode includes the third subsegment 115c, and the second secondary pixel electrode includes the fourth subsegment 115d.

[0073] In some embodiments, the orthographic projection of the first sub-segment 115a on the substrate 101 is at least partially located within the orthographic projection of the data line 113 on the substrate 101, and the orthographic projection of the third sub-segment 115c on the substrate 101 is at least partially located within the orthographic projection of the data line 113 on the substrate 101. Alternatively,

[0074] The orthographic projection of the second sub-segment 115b on the substrate 101 is at least partially located within the orthographic projection of the data line 113 on the substrate 101, and the orthographic projection of the fourth sub-segment 115d on the substrate 101 is at least partially located within the orthographic projection of the data line 113 on the substrate 101. Alternatively,

[0075] See also Figures 3 and 4 ,and Figures 7 to 9 The data lines 113 include first-type data lines 113a and second-type data lines 113b. The orthographic projection of the first sub-segment 115a on the substrate 101 is at least partially located within the orthographic projection of the first-type data lines 113a on the substrate 101, and the orthographic projection of the third sub-segment 115c on the substrate 101 is at least partially located within the orthographic projection of the first-type data lines 113a on the substrate 101. The orthographic projection of the second sub-segment 115b on the substrate 101 is at least partially located within the orthographic projection of the second-type data lines 113b on the substrate 101, and the orthographic projection of the fourth sub-segment 115d on the substrate 101 is at least partially located within the orthographic projection of the second-type data lines 113b on the substrate 101. Taking the large-size 75UD display panel as an example, when using the following Figure 1 The array substrate 100 shown in FIG. 1 is a conventional array substrate 100 ′ (eg, Figure 1 As shown), the aperture ratio is increased by more than 20%.

[0076] In some embodiments, the pixel unit 102 includes a first pixel unit 102a and a second pixel unit 102b. The first pixel unit 102a and the second pixel unit 102b are alternately arranged along the second direction Y. The first pixel unit 102a is electrically connected to the first-type data line 113a, and the second pixel unit 102b is electrically connected to the second-type data line 113b. The polarity of the first-type data line 113a and the second-type data line 113b are opposite. That is, the array substrate 100 further includes a first common electrode line 118. The voltage difference between the first-type data line 113a and the first common electrode line 118 is opposite in polarity to the voltage difference between the second-type data line 113b and the first common electrode line 118. The polarities of the signals input to the first-type data lines 113a and the second-type data lines 113b are opposite. By inputting signals of opposite polarity to the first-type data lines 113a and the second-type data lines 113b, respectively, the first-type data lines 113a control the polarity of the first pixel unit 102a, and the second-type data lines 113b control the polarity of the second pixel unit 102b. This facilitates enabling a display panel using the array substrate 100 to achieve single-point flipping in the column direction, reducing graininess in the display panel's image, and improving the display quality of the display panel. Furthermore, the first pixel units 102a and the second pixel units 102b are alternately arranged along the second direction Y, and the first pixel units 102a and the second pixel units 102b are alternately arranged along the first direction X. This facilitates enabling a display panel using the array substrate 100 to achieve single-point flipping in the column and row directions, reducing graininess in the display panel's image, and improving the display quality of the display panel.

[0077] At the same time, the first pixel unit 102a and the second pixel unit 102b are alternately arranged along the second direction Y. When the first pixel unit 102a is electrically connected to the first type of data line 113a and the second pixel unit 102b is electrically connected to the second type of data line 113b, the first type of data line 113a is electrically connected to the pixel electrode 114 in the first pixel unit 102a to control the polarity of the first pixel unit 102a, and the polarity of the pixel electrode 114 in the first pixel unit 102a is opposite to the polarity of the second type of data line 113b; similarly, the second type of data line 113b is electrically connected to the pixel electrode 114 in the second pixel unit 102b to control the polarity of the second pixel unit 102b, and the polarity of the pixel electrode 114 in the second pixel unit 102b is opposite to the polarity of the first type of data line 113a. By having the polarity of the pixel electrode 114 in the first pixel unit 102a be opposite to the polarity of the signal input by the second type data line 113b, and the polarity of the pixel electrode 114 in the second pixel unit 102b be opposite to the polarity of the signal input by the first type data line 113a, the coupling capacitance between the data line 113 and the pixel electrode 114 is reduced, thereby reducing the risk of crosstalk and improving the product quality of the array substrate 100. Since the polarity between the first type data line 113a and the second type data line 113b is opposite, the coupling effects are balanced, and the need for Figure 1 The arrangement of the DBS (Data line BM Less) common electrode 130 ′ shown in FIG further improves the aperture ratio of the array substrate 100 .

[0078] See also Figure 7In some embodiments, when the first-type data line 113a is electrically connected to the first pixel unit 102a and the second-type data line 113b is electrically connected to the second pixel unit 102b, the array substrate 100 further includes a first-type routing line 116 and a second-type routing line 117, the first-type routing line 116 is connected between the first pixel unit 102a and the first-type data line 113a, and the second-type routing line 117 is connected between the second pixel unit 102b and the second-type data line 113b. Specifically, one end of the first-type routing line 116 is connected to the source of the first thin-film transistor T1 and the source of the second thin-film transistor T2 in the first pixel unit 102a, and the other end of the first-type routing line 116 is connected to the first-type data line 113a. One end of the second-type routing line 117 is connected to the source of the first thin-film transistor T1 and the source of the second thin-film transistor T2 in the second pixel unit 102b, and the other end of the second-type routing line 117 is connected to the second-type data line 113b. The first-type routing line 116 extends along the first direction X and is located between the primary pixel area 103 and the secondary pixel area 104. The second-type routing line 117 extends along the first direction X and is located between the primary pixel area 103 and the secondary pixel area 104, so as to avoid occupying additional light-transmitting area of ​​the pixel unit 102 and improve the aperture ratio of the array substrate 100. The orthographic projection of the first type of routing 116 on the substrate 101 is at least partially located within the orthographic projection of the scanning line 105 on the substrate 101, and the orthographic projection of the second type of routing 117 on the substrate 101 is at least partially located within the orthographic projection of the scanning line 105 on the substrate 101, so as to further avoid additional occupation of the light-transmitting area of ​​the pixel unit 102 and improve the aperture ratio of the array substrate 100.

[0079] See also Figure 11In some embodiments, the first type of signal line 106 is a data line 113, that is, the data line 113 is located between the first main pixel sub-area 107 and the second main pixel sub-area 108, and the data line 113 is located between the first sub-pixel sub-area 109 and the second sub-pixel sub-area 110, which reduces the coupling capacitance between the data line 113 and the pixel electrode 114 and improves the signal transmission performance of the data line 113. When the data line 113 is located between the first main pixel sub-area 107 and the second main pixel sub-area 108, the pixel units 102 in the same column arranged along the second direction Y are electrically connected to the same data line 113, that is, a first-type signal line 106 is arranged between the first main pixel sub-area 107 and the second main pixel sub-area 108 of each pixel unit 102, so as to further reduce the coupling capacitance between the data line 113 and the pixel electrode 114 while reducing the additional light-transmitting area of ​​the array substrate 100 occupied by the data line 113, thereby improving the aperture ratio of the array substrate 100.

[0080] In some embodiments, see Figure 11 The array substrate 100 further includes a shared electrode line 112, which is disposed around the pixel unit 102. The shared electrode line 112 transmits a constant voltage signal, thereby achieving different potentials between the primary pixel electrode and the secondary pixel electrode. When the shared electrode line 112 is disposed around the pixel unit 102, a stable capacitance is generated between the shared electrode line 112 and the pixel electrode 114, which helps to increase the storage capacitance of the pixel unit 102 and improve the display stability of the display panel using the array substrate 100. In this case, the first-type signal line 106 can be a data line 113.

[0081] The shared electrode line 112 includes a first electrode line subsegment 112a, a second electrode line subsegment 112b, and a third electrode line subsegment 112c located within each pixel unit 102. The first electrode line subsegment 112a and the second electrode line subsegment 112b extend along the first direction X. The third electrode line subsegment 112c is connected between the first electrode line subsegment 112a and the second electrode line subsegment 112b. The third electrode line subsegment 112c extends along the second direction Y and is located on a side of the first electrode line subsegment 112a away from the thin film transistor 111. The first, second, and third electrode line subsegments 112a, 112b, and 112c are arranged around the periphery of the first primary pixel sub-region 107 and the first secondary pixel sub-region 109. The end of the second electrode line subsegment 112b proximal to the third thin film transistor T3 is connected to the drain of the third thin film transistor T3.

[0082] The shared electrode line 112 may further include a fourth electrode line sub-segment 112d, a fifth electrode line sub-segment 112e, a sixth electrode line sub-segment 112f, and a seventh electrode line sub-segment 112g located within each pixel unit 102. The fourth electrode line sub-segment 112d and the fifth electrode line sub-segment 112e extend along the first direction X, and the sixth electrode line sub-segment 112f and the seventh electrode line sub-segment 112g extend along the second direction Y. The sixth electrode line sub-segment 112f is connected between the fourth electrode line sub-segment 112d and the fifth electrode line sub-segment 112e, and the seventh electrode line sub-segment 112g is connected between the fourth electrode line sub-segment 112d and the fifth electrode line sub-segment 112e. The fourth electrode line sub-segment 112d and the first electrode line sub-segment 112a are respectively located on opposite sides of the first-type signal line 106, and the fifth electrode line sub-segment 112e and the second electrode line sub-segment 112b are respectively located on opposite sides of the first-type signal line 106. Within each pixel unit, the sixth electrode line sub-segment 112f and the seventh electrode line sub-segment 112g are respectively located on opposite sides of the first trunk electrode 115 within the second primary pixel sub-region 108. The sixth electrode line sub-segment 112f is located on the side of the third electrode line sub-segment 112c away from the thin-film transistor 111, and the seventh electrode line sub-segment 112g is located on the side of the third electrode line sub-segment 112c closer to the thin-film transistor 111. The fourth electrode line sub-segment 112d, the fifth electrode line sub-segment 112e, the sixth electrode line sub-segment 112f, and the seventh electrode line sub-segment 112g are arranged around the periphery of the second primary pixel sub-region 108 and the second secondary pixel sub-region 110.

[0083] Along the first direction X, in the pixel units 102 in the same row, the fourth electrode line subsegment 112d, the fifth electrode line subsegment 112e, the sixth electrode line subsegment 112f, and the seventh electrode line subsegment 112g in each of the pixel units 102 are connected and connected to the third electrode line subsegment 112c of the adjacent pixel unit 102 adjacent to the sixth electrode line subsegment 112f through the sixth electrode line subsegment 112f. For example, along the first direction X, in the pixel units 102 in the same row, the third electrode line subsegment 112c in the Mth pixel unit is connected to the sixth electrode line subsegment 112f in the M+1th pixel unit, where M is an integer greater than or equal to 1.

[0084] In some embodiments, along the first direction X, in the same row of the pixel units 102, the sixth electrode line sub-segment 112f in each of the pixel units 102 is shared with the third electrode line sub-segment 112c of the adjacent pixel unit adjacent to the sixth electrode line sub-segment 112f, so as to simplify the process and improve the aperture ratio of the array substrate.

[0085] See also Figure 8 and Figure 9 In some embodiments, the array substrate 100 further includes a first common electrode line 118. The first common electrode line 118 extends along the first direction X. The first common electrode line 118 is disposed on the same layer as the scan line 105 and is spaced apart therefrom. The first common electrode line 118 includes a first sub-portion 118a and a second sub-portion 118b arranged along the second direction Y. The first sub-portion 118a and the second sub-portion 118b are located on opposite sides of the pixel unit 102. The first common electrode line 118 transmits a constant voltage signal, generating a stable capacitance between the first common electrode line 118 and the pixel electrode 114, thereby increasing the storage capacitance of the pixel unit 102 and improving the display stability of a display panel using the array substrate 100.

[0086] The first sub-portion 118a is located at the periphery of the first main pixel sub-region 107 and the second main pixel sub-region 108, and the second sub-portion 118b is located at the periphery of the first primary pixel sub-region 109 and the second secondary pixel sub-region 110, so as to avoid excessive occupation of the light-transmitting area of ​​the pixel unit 102, which is beneficial to improving the aperture ratio of the array substrate 100.

[0087] In some embodiments, when the shared electrode line 112 is disposed around the pixel unit 102, the shared electrode line 112 includes a third sub-portion 119 and a fourth sub-portion 120 arranged along the second direction Y, and the third sub-portion 119 and the fourth sub-portion 120 each extend along the first direction X. The third sub-portion 119 and the fourth sub-portion 120 are respectively located on opposite sides of the pixel unit 102, and the orthographic projection of the third sub-portion 119 on the substrate 101 is at least partially located within the orthographic projection of the first sub-portion 118a on the substrate 101, and the orthographic projection of the fourth sub-portion 120 on the substrate 101 is at least partially located within the orthographic projection of the second sub-portion 118b on the substrate 101. This facilitates increasing the storage capacitance of the pixel unit 102 while minimizing the additional light-transmitting area of ​​the array substrate 100 occupied, thereby improving the display stability of a display panel using the array substrate 100. The first electrode line sub-segment 112 a and the fourth electrode line sub-segment 112 d of the shared electrode line 112 constitute the third sub-portion 119 , and the second electrode line sub-segment 112 b and the fifth electrode line sub-segment 112 e of the shared electrode line 112 constitute the fourth sub-portion 120 .

[0088] See also Figure 9 and Figure 10 In some embodiments, the first common electrode line 118 and the scan line 105 can be disposed in the same layer. The first sub-portion 118a of the first common electrode line 118 includes a first extending sub-portion extending in the second direction Y to between the first primary pixel sub-region 107 and the second primary pixel sub-region 108. The second sub-portion 118b of the first common electrode line 118 includes a second extending sub-portion extending in the second direction Y to between the first secondary pixel sub-region 109 and the second secondary pixel sub-region 110.

[0089] The pixel unit 102 further includes a first pixel electrode connection portion located between the first primary pixel sub-region 107 and the second primary pixel sub-region 108. The first pixel electrode connection portion connects the pixel electrode 114 in the first primary pixel sub-region 107 with the pixel electrode 114 in the second primary pixel sub-region 108. The pixel unit 102 further includes a second pixel electrode connection portion located between the first secondary pixel sub-region 109 and the second secondary pixel sub-region 110. The second pixel electrode connection portion connects the pixel electrode 114 in the first secondary pixel sub-region 109 with the pixel electrode 114 in the second secondary pixel sub-region 110. The first pixel electrode connection portion and the second pixel electrode connection portion are located in the pixel electrode layer 123.

[0090] The orthographic projection of the first extending sub-portion on the substrate 101 at least partially overlaps with the orthographic projection of the first pixel electrode connecting portion on the substrate 101, which helps to increase the storage capacitance of the pixel unit 102 and improve the display stability of the display panel using the array substrate 100. Similarly, the orthographic projection of the second extending sub-portion on the substrate 101 at least partially overlaps with the orthographic projection of the second pixel electrode connecting portion on the substrate 101.

[0091] See also Figure 10 The first common electrode line 118 and the scanning line 105 are separately arranged and do not cross each other to avoid a short circuit between the first common electrode line 118 and the scanning line 105, which affects the product quality of the display panel using the array substrate 100.

[0092] See also Figures 4 to 6 In some embodiments, the shared electrode line 112 is disposed on the same layer as the data line 113, the source of the first thin-film transistor T1, the drain of the first thin-film transistor T1, the source of the second thin-film transistor T2, the drain of the second thin-film transistor T2, the source of the third thin-film transistor T3, and the drain of the third thin-film transistor T3, on the first metal layer 121. The scan line 105, the first common electrode line 118, the gate of the first thin-film transistor T1, the gate of the second thin-film transistor T2, and the gate of the third thin-film transistor T3 are disposed on the same layer as the second metal layer 122. The pixel electrode 114 is located on the pixel electrode layer 123, and the first metal layer 121 is located between the second metal layer 122 and the pixel electrode layer 123. The array substrate 100 further includes a first via hole located between the first primary pixel sub-region 107 and the second primary pixel sub-region 108. The pixel electrode 114 in the first primary pixel sub-region 107 and the pixel electrode 114 in the second primary pixel sub-region 108 are electrically connected to the drain of the first thin-film transistor T1 through the first via hole. The array substrate 100 further includes a second via hole located between the first secondary pixel sub-region 109 and the second secondary pixel sub-region 110. The pixel electrode 114 in the first secondary pixel sub-region 109 and the pixel electrode 114 in the second secondary pixel sub-region 110 are electrically connected to the drain of the second thin-film transistor T2 through the second via hole.

[0093] In some embodiments, the scan line 105 , the gate of the first thin film transistor T1 , the gate of the second thin film transistor T2 , and the gate of the third thin film transistor T3 are integrated to simplify the manufacturing process of the array substrate 100 and reduce manufacturing costs.

[0094] In some embodiments, the material of the first metal layer 121 and the second metal layer 122 may include metal. For example, the first metal layer 121 and / or the second metal layer 122 may be an alloy, a metal material, or a stack of a metal material and other conductive materials.

[0095] In some embodiments, the pixel electrode 114 is selected from a transparent conductive material, for example, an indium tin oxide material.

[0096] In some embodiments, each of the pixel units 102 has an eight-domain structure, and the eight domains include four domains located in the main pixel area 103 and four domains located in the sub-pixel area 104. The four domains located in the main pixel area 103 include two domains located in the first main pixel sub-area 107 and two domains located in the second main pixel sub-area 108; the four domains located in the sub-pixel area 104 include two domains located in the first sub-pixel sub-area 109 and two domains located in the second sub-pixel sub-area 110.

[0097] In each pixel unit 102, the first main pixel electrode in the first main pixel sub-region 107 includes a first main branch electrode and a second main branch electrode connected to both ends of the first subsegment 115a of the first trunk electrode 115. The first main branch electrode is connected to an end of the first subsegment 115a closer to the first sub-pixel sub-region 109, and the second main branch electrode is connected to an end of the first subsegment 115a farther from the first sub-pixel sub-region 109. The first main branch electrode and the second main branch electrode extend along the first direction X. In each pixel unit 102, the first main pixel electrode in the first main pixel sub-region 107 further includes a third main branch electrode connected between the first main branch electrode and the second main branch electrode. The third main branch electrode is located on a side of the first subsegment 115a farther from the thin film transistor 111. In each pixel unit 102, the first main pixel electrode in the first main pixel sub-region 107 further includes a first branch electrode. The first branch electrode is connected between the first sub-segment 115a and the first main branch electrode, the first main branch electrode and the second main branch electrode, and the third main branch electrode and the second main branch electrode. The first branch electrode forms a first angle with the scan line 105. In each pixel unit 102, the first main pixel electrode in the first main pixel sub-region 107 further includes a second branch electrode. The second branch electrode is connected between the first sub-segment 115a and the first main branch electrode, the first main branch electrode and the second main branch electrode, and the third main branch electrode and the second main branch electrode. The second branch electrode forms a second angle with the first direction X. The first branch electrode and the second branch electrode are symmetrically arranged with respect to the first sub-segment 115a. When the first angle is 45 degrees, the second angle can be 135 degrees.

[0098] In each pixel unit 102, the second main pixel electrode in the second main pixel sub-region 108 includes a fourth main branch electrode and a fifth main branch electrode connected to both ends of the second subsegment 115b of the first trunk electrode 115. The fourth main branch electrode is connected to an end of the second subsegment 115b closer to the second secondary pixel sub-region 110, and the fifth main branch electrode is connected to an end of the second subsegment 115b farther from the second secondary pixel sub-region 110. The fourth main branch electrode and the fifth main branch electrode extend along the first direction X. In each pixel unit 102, the second main pixel electrode in the second main pixel sub-region 108 also includes a sixth main branch electrode connected between the fourth main branch electrode and the fifth main branch electrode. The sixth main branch electrode is located on a side of the second subsegment 115b farther from the thin film transistor 111. In each pixel unit 102, the second main pixel electrode in the second main pixel sub-region 108 further includes a third branch electrode. The third branch electrode is connected between the second sub-segment 115b and the fifth main branch electrode, the fourth main branch electrode and the fifth main branch electrode, and the sixth main branch electrode and the fourth main branch electrode. The third branch electrode forms a third angle with the scan line 105. In each pixel unit 102, the second main pixel electrode in the second main pixel sub-region 108 further includes a fourth branch electrode. The fourth branch electrode is connected between the second sub-segment 115b and the fifth main branch electrode, the fourth main branch electrode and the fifth main branch electrode, and the sixth main branch electrode and the fourth main branch electrode. The third branch electrode forms a fourth angle with the scan line 105. The third branch electrode and the fourth branch electrode are symmetrically arranged about the second sub-segment 115b. When the third angle is 45 degrees, the fourth angle can be 135 degrees.

[0099] In each pixel unit 102, the first sub-pixel electrode in the first sub-pixel sub-region 109 includes a seventh main branch electrode and an eighth main branch electrode connected to both ends of the third sub-segment 115c of the first trunk electrode 115. The seventh main branch electrode is connected to an end of the third sub-segment 115c that is closer to the first main pixel sub-region 107, and the eighth main branch electrode is connected to an end of the third sub-segment 115c that is farther from the first main pixel sub-region 107. The seventh main branch electrode and the eighth main branch electrode extend along the first direction X. In each pixel unit 102, the first sub-pixel electrode in the first sub-pixel sub-region 109 also includes a ninth main branch electrode connected between the seventh and eighth main branch electrodes. The ninth main branch electrode is located on a side of the third sub-segment 115c that is farther from the thin film transistor 111. In each pixel unit 102, the first sub-pixel electrode in the first sub-pixel sub-region 109 further includes a fifth branch electrode. The fifth branch electrode is connected between the third sub-segment 115c and the seventh main-branch electrode, the seventh main-branch electrode and the eighth main-branch electrode, and the eighth main-branch electrode and the ninth main-branch electrode. The fifth branch electrode forms a fifth angle with the scan line 105. In each pixel unit 102, the first sub-pixel electrode in the first sub-pixel sub-region 109 further includes a sixth branch electrode. The sixth branch electrode is connected between the third sub-segment 115c and the seventh main-branch electrode, the seventh main-branch electrode and the eighth main-branch electrode, and the eighth main-branch electrode and the ninth main-branch electrode. The sixth branch electrode forms a sixth angle with the scan line 105. The fifth branch electrode and the sixth branch electrode are symmetrically arranged about the third sub-segment 115c. When the fifth angle is 45 degrees, the sixth angle can be 135 degrees.

[0100] In each pixel unit 102, the second sub-pixel electrode in the second sub-pixel sub-region 110 includes a tenth main branch electrode and an eleventh main branch electrode connected to both ends of the fourth sub-segment 115d of the first trunk electrode 115. The tenth main branch electrode is connected to an end of the fourth sub-segment 115d closer to the second sub-pixel sub-region 110, and the eleventh main branch electrode is connected to an end of the fourth sub-segment 115d farther from the second sub-pixel sub-region 110. The tenth main branch electrode and the eleventh main branch electrode extend along the first direction X. In each pixel unit 102, the second sub-pixel electrode in the second sub-pixel sub-region 110 also includes a twelfth main branch electrode connected between the tenth main branch electrode and the eleventh main branch electrode. The twelfth main branch electrode is located on a side of the fourth sub-segment 115d farther from the thin film transistor 111. In each pixel unit 102, the second sub-pixel electrode in the second sub-pixel sub-region 110 further includes a seventh branch electrode. The seventh branch electrode is connected between the fourth sub-segment 115d and the eleventh main branch electrode, the tenth main branch electrode and the eleventh main branch electrode, and the tenth main branch electrode and the twelfth main branch electrode. The seventh branch electrode forms a seventh angle with the scan line 105. In each pixel unit 102, the second sub-pixel electrode in the second sub-pixel sub-region 110 further includes an eighth branch electrode. The eighth branch electrode is connected between the fourth sub-segment 115d and the eleventh main branch electrode, the tenth main branch electrode and the eleventh main branch electrode, and the tenth main branch electrode and the twelfth main branch electrode. The eighth branch electrode forms an eighth angle with the scan line 105. The seventh branch electrode and the eighth branch electrode are symmetrically arranged with respect to the fourth sub-segment 115d. When the seventh angle is 45 degrees, the eighth angle can be 135 degrees.

[0101] In some embodiments, the first branch electrode and the fifth branch electrode are located on the same side of the first trunk electrode 115 in the first main pixel sub-region 107 and the first sub-pixel sub-region 109, the second branch electrode and the sixth branch electrode are located on the same side of the first trunk electrode 115 in the first main pixel sub-region 107 and the first sub-pixel sub-region 109. The third branch electrode and the seventh branch electrode are located on the same side of the first trunk electrode 115 in the second main pixel sub-region 108 and the second sub-pixel sub-region 110, and the fourth branch electrode and the eighth branch electrode are located on the same side of the first trunk electrode 115 in the second main pixel sub-region 108 and the second sub-pixel sub-region 110.

[0102] In some embodiments, the scan line 105 is located between the primary pixel area 103 and the secondary pixel area 104, and the orthographic projection of the scan line 105 on the substrate 101 is located outside the orthographic projection of the pixel electrode 114 on the substrate 101, so as to reduce the coupling capacitance between the scan line 105 and the pixel electrode 114. Alternatively, the orthographic projection of the scan line 105 on the substrate 101 and the orthographic projection of the pixel electrode 114 on the substrate 101 at least partially overlap, so as to reduce the light-transmitting area of ​​the array substrate 100 occupied by the scan line 105 and improve the aperture ratio of the array substrate 100.

[0103] In some embodiments, the pixel cells 102 include pixel cells of a first color, pixel cells of a second color, and pixel cells of a third color. The pixel cells of the first color, the pixel cells of the second color, and the pixel cells of the third color are arranged repeatedly along the second direction Y, and the first color, the second color, and the third color are different colors. Along the first direction X, the pixel cells 102 in each row are pixel cells corresponding to the same color and arranged in sequence. For example, if the Nth row contains pixel cells of the first color, where N is an integer greater than or equal to 1, then the N+1th row contains pixel cells of the second color, and the N+2th row contains pixel cells of the third color.

[0104] In some embodiments, the substrate 101 is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, so that the substrate 101 has good impact resistance and can effectively protect the array substrate 100 .

[0105] The array substrate 100 disclosed in the embodiment of the present invention reduces the light-transmitting area occupied by the signal lines in the array substrate 100, increases the light-transmitting area of ​​the pixel unit 102, improves the aperture ratio of the array substrate 100, and improves the transmittance of the display panel using the array substrate 100 by arranging the scan line 105 between the main pixel area 103 and the sub-pixel area 104, and arranging the first type of signal line 106 and the thin film transistor 111 between the first main pixel sub-area 107 and the second main pixel sub-area 108.

[0106] See also Figure 12 An embodiment of the present invention further provides a display panel 10, comprising any array substrate 100 as described above.

[0107] The specific structure of the array substrate 100 can be found in any of the above-mentioned embodiments and drawings of the array substrate, and will not be described in detail here.

[0108] In this embodiment, the display panel 10 may be a liquid crystal display panel. The display panel 10 further includes a liquid crystal layer 200 located on one side of the array substrate 100, and a color filter substrate 300 located on a side of the liquid crystal layer 200 away from the array substrate 100. The liquid crystal layer 200 is located on a side of the array substrate 100 where the pixel unit 102 is away from the substrate 101 of the array substrate 100.

[0109] In some embodiments, the display panel 10 further includes a color filter layer, which may be located on a side of the array substrate 100 close to the liquid crystal layer 200 . Alternatively, the color filter layer may be located on a side of the color filter substrate 300 close to the liquid crystal layer 200 .

[0110] The color filter layer includes a first color resist, a second color resist, and a third color resist. The first color resist is configured to correspond to the first color pixel unit in the array substrate 100, the second color resist is configured to correspond to the second color pixel unit in the array substrate 100, and the third color resist is configured to correspond to the third color pixel unit in the array substrate 100, to achieve image display on the display panel. The first color resist, the second color resist, and the third color resist are each selected from red, green, and blue, and the first, second, and third colors are different from each other.

[0111] An embodiment of the present invention discloses an array substrate and a display panel; the array substrate includes a substrate, pixel units, scan lines extending along a first direction, and a first type of signal line extending along a second direction, each pixel unit includes a main pixel area and a sub-pixel area, and each pixel unit also includes a thin film transistor, the scan line is located between the main pixel area and the sub-pixel area, and the first type of signal line and the thin film transistor are located between the first main pixel sub-area and the second main pixel sub-area of ​​the main pixel area. The present invention reduces the light-transmitting area occupied by the signal lines in the array substrate, improves the aperture ratio of the array substrate, improves the transmittance of the display panel using the array substrate, and reduces the manufacturing cost and power consumption of the display panel.

[0112] The above is a detailed introduction to an array substrate and a display panel provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, based on the idea of ​​the present invention, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of pixel units, wherein the plurality of pixel units are distributed on one side of the substrate, each of the pixel units includes a primary pixel region and a secondary pixel region, and each of the pixel units further includes a pixel electrode located in the primary pixel region and the secondary pixel region; a scan line extending along a first direction, wherein the scan line is located between the primary pixel region and the secondary pixel region; a first type of signal line extending along a second direction, wherein the first direction intersects the second direction; The primary pixel region includes a first primary pixel sub-region and a second primary pixel sub-region arranged along the first direction, the secondary pixel region includes a first secondary pixel sub-region and a second secondary pixel sub-region arranged along the first direction, the first primary pixel sub-region and the first secondary pixel sub-region are arranged along the second direction, and the second primary pixel sub-region and the second secondary pixel sub-region are arranged along the second direction; The first type of signal line is located between the first main pixel sub-region and the second main pixel sub-region; Each of the pixel units also includes multiple thin film transistors, which are electrically connected to the scan lines and the first type of signal lines. The thin film transistors are located between the first main pixel sub-area and the second main pixel sub-area. The pixel electrode in the first main pixel sub-area and the pixel electrode in the second main pixel sub-area are connected to the same thin film transistor, and the pixel electrode in the first pixel sub-area and the pixel electrode in the second pixel sub-area are connected to the same thin film transistor.

2. The array substrate according to claim 1, wherein: The array substrate further includes a data line extending along the second direction; The pixel electrode includes a first trunk electrode extending along the second direction, and an orthographic projection of the first trunk electrode on the substrate is at least partially located within an orthographic projection of the data line on the substrate.

3. The array substrate according to claim 2, wherein: The first trunk electrode includes a first subsegment located in the first main pixel sub-region, a second subsegment located in the second main pixel sub-region, a third subsegment located in the first primary pixel sub-region, and a fourth subsegment located in the second secondary pixel sub-region; The data lines include a first type of data lines and a second type of data lines, the orthographic projection of the first sub-segment on the substrate is at least partially located within the orthographic projection of the first type of data lines on the substrate, and the orthographic projection of the third sub-segment on the substrate is at least partially located within the orthographic projection of the first type of data lines on the substrate, the orthographic projection of the second sub-segment on the substrate is at least partially located within the orthographic projection of the second type of data lines on the substrate, and the orthographic projection of the fourth sub-segment on the substrate is at least partially located within the orthographic projection of the second type of data lines on the substrate.

4. The array substrate according to claim 3, wherein: The pixel units include first pixel units and second pixel units, the first pixel units and the second pixel units are alternately arranged along the second direction, the first pixel units are electrically connected to the first type of data lines, and the second pixel units are electrically connected to the second type of data lines. The array substrate further includes a first common electrode line; The voltage difference between the first type of data line and the first common electrode line is opposite in polarity to the voltage difference between the second type of data line and the first common electrode line.

5. The array substrate according to claim 2, wherein: The first type of signal lines are shared electrode lines.

6. The array substrate according to claim 1, wherein: The array substrate further includes a shared electrode line, and the shared electrode line is arranged around the pixel unit.

7. The array substrate according to claim 2 or 6, characterized in that: The array substrate further includes a first common electrode line, the first common electrode line extending along the first direction, the first common electrode line and the scanning line being in the same layer and spaced apart; The first common electrode line includes a first sub-portion and a second sub-portion arranged along the second direction, and the first sub-portion and the second sub-portion are respectively located on two opposite sides of the pixel unit.

8. The array substrate according to claim 7, wherein: The shared electrode line is disposed around the pixel unit, and the shared electrode line includes a third sub-portion and a fourth sub-portion arranged along the second direction, and the third sub-portion and the fourth sub-portion extend along the first direction respectively; In which, the third sub-section and the fourth sub-section are respectively located on opposite sides of the pixel unit, the orthographic projection of the third sub-section on the substrate is at least partially located within the orthographic projection of the first sub-section on the substrate, and the orthographic projection of the fourth sub-section on the substrate is at least partially located within the orthographic projection of the second sub-section on the substrate.

9. The array substrate according to claim 6, wherein: The first type of signal lines are data lines.

10. The array substrate according to claim 9, wherein: In each of the pixel units, the thin film transistor is located on a side of the first type signal line close to the first main pixel sub-region, or the thin film transistor is located on a side of the first type signal line close to the second main pixel sub-region; Wherein, the thin film transistor includes a first thin film transistor, a second thin film transistor and a third thin film transistor; The gate of the first thin film transistor is electrically connected to the scan line, the source of the first thin film transistor is electrically connected to the data line, and the drain of the first thin film transistor is electrically connected to the pixel electrode in the main pixel area; The gate of the second thin film transistor is electrically connected to the scan line, the source of the second thin film transistor is electrically connected to the data line, and the drain of the second thin film transistor is electrically connected to the pixel electrode in the sub-pixel area; The gate of the third thin film transistor is electrically connected to the scan line, the source of the third thin film transistor is electrically connected to the drain of the second thin film transistor, and the drain of the third thin film transistor is electrically connected to the shared electrode line.

11. The array substrate according to claim 10, wherein: The scan line, the gate of the first thin film transistor, the gate of the second thin film transistor, and the gate of the third thin film transistor are integrally arranged.

12. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 11.

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