Power supply circuits, negative voltage supply methods and electronic equipment

Abstract

This disclosure relates to the field of analog circuits, and particularly to a power supply circuit, a negative voltage supply method, and an electronic device. The power supply circuit includes: a first capacitor, with a first terminal for receiving a first control clock and a second terminal connected to the drain of a first PMOS transistor, the source of which is connected to the input of the power supply circuit; a second capacitor, with a first terminal for receiving a second control clock and a second terminal connected to the drain of a second PMOS transistor, the source of which is connected to the input of the power supply circuit; a second terminal of the first capacitor is also connected to the gate of the second PMOS transistor, and a second terminal of the second capacitor is also connected to the gate of the first PMOS transistor; a first discharge path is configured to be driven by an effective first control signal to provide a negative voltage to the output of the power supply circuit; a second discharge path is configured to be driven by an effective second control signal to provide a negative voltage to the output of the power supply circuit, at least for improving the voltage gain and power conversion efficiency of the negative voltage supply circuit.

Description

Technical Field

[0001] This disclosure relates to the field of analog circuits, and in particular to a power supply circuit, a negative voltage supply method, and an electronic device. Background Technology

[0002] Neurological disorders, also known as neurological imbalances, have received increasing attention and recognition worldwide in recent years. These disorders include Alzheimer's disease, Parkinson's disease, epilepsy, multiple sclerosis, and many others. Due to global population aging, changes in lifestyle and environmental factors, the prevalence of neurological disorders is rising. Therefore, more people are directly or indirectly affected by these diseases.

[0003] While curing many neurological disorders remains challenging, significant breakthroughs have been achieved at the treatment and intervention levels, including the development of new drugs, surgical techniques, and non-invasive therapies. Advances in electronic technology have provided many potential treatment options for neurodegenerative diseases, such as treating epilepsy through implanted electrical stimulation.

[0004] The primary consideration for implantable electrical stimulation devices is size. Because these devices are invasive, smaller sizes result in less physiological harm to the patient. To reduce device size, wireless power transmission is typically used to charge the device, which then generates the direct current required by the stimulation system via AC-DC conversion.

[0005] The therapeutic effect of electrical stimulation is closely related to its parameters, which can vary depending on the specific application. These parameters may include frequency, intensity, duration, stimulation type (e.g., monophasic or biphasic, constant current or constant voltage), pulse duty cycle, and interphase interval time. Under constant voltage electrical stimulation, the order of anodic and cathodic stimulation usually does not significantly affect the stimulation results; however, under constant current electrical stimulation, the order may influence the results. When establishing a constant voltage stimulation circuit, it is important to note that during CMOS fabrication, resistance division is easily affected by process variations, such as temperature changes. When using biphasic current stimulation, the alternating direction of the current in each phase of the waveform can reverse the direction of ion movement in the tissue. Furthermore, the biphasic waveform must ensure that the net charge transferred over time is balanced, thus distributing the charge more evenly, preventing charge accumulation at the electrode interface, and reducing the risk of tissue damage and electrolysis. Conversely, with monophasic current stimulation, the monophasic waveform has net charge transfer, and electrolysis can occur under monophasic current, involving the accumulation of charged ions at the electrode site, which may cause skin burns and tissue damage. On the other hand, patients often find biphasic electrical stimulation more comfortable and tolerable than monophasic electrical stimulation. The alternating phases can reduce discomfort or pain associated with electrical stimulation. Biphasic waveforms offer greater flexibility in adjusting stimulation parameters to achieve specific therapeutic goals, and healthcare providers can fine-tune the treatment effect by adjusting the pulse duration, frequency, and amplitude of different treatment phases.

[0006] To achieve biphasic current stimulation, systems using wireless power transmission typically employ two power supplies with different voltages: one supplying a positive voltage and the other a negative voltage. However, the efficiency of current negative voltage power supplies is not ideal. Summary of the Invention

[0007] This disclosure provides a power supply circuit, a negative voltage supply method, and an electronic device, which are at least used to improve the voltage gain and power conversion efficiency of the negative voltage supply circuit.

[0008] One embodiment of this disclosure provides a power supply circuit, including: a first capacitor, with a first terminal for receiving a first control clock and a second terminal connected to the drain of a first PMOS transistor, the source of the first PMOS transistor being connected to the input of the power supply circuit; a second capacitor, with a first terminal for receiving a second control clock and a second terminal connected to the drain of a second PMOS transistor, the source of the second PMOS transistor being connected to the input of the power supply circuit; the second terminal of the first capacitor is also connected to the gate of the second PMOS transistor, and the second terminal of the second capacitor is also connected to the gate of the first PMOS transistor; wherein at most one of the first control clock and the second control clock is at a high level; a first discharge path, with its input terminal connected to the second terminal of the first capacitor and its output terminal connected to the output of the power supply circuit, and a control terminal for receiving a first control signal, configured to drive based on a valid first control signal, such that the second terminal of the first capacitor provides a negative voltage to the output of the power supply circuit; and a second discharge path, with its input terminal connected to the second terminal of the second capacitor and its output terminal connected to the output of the power supply circuit, and a control terminal for receiving a second control signal, configured to drive based on a valid second control signal, such that the second terminal of the second capacitor provides a negative voltage to the output of the power supply circuit.

[0009] The power supply circuit provided in this embodiment, through the alternating effectiveness of the first control clock and the second control clock, allows the first capacitor and the second capacitor to discharge alternately, thereby improving the voltage gain and power conversion efficiency of the power supply circuit in providing negative voltage. Furthermore, since both the first and second capacitors need to accumulate negative charge during charging, they both pull down the potential at the input terminal of the power supply circuit. With respect to the input potential of the power supply circuit, the first and second capacitors continuously pull down the potential through positive feedback, causing the input potential of the power supply circuit to continuously decrease. This results in a faster accumulation rate of negative charge on the lower plate of the first capacitor and the upper plate of the second capacitor after the subsequent charging circuit is turned on.

[0010] In some embodiments, the first discharge path includes a first NMOS transistor; the second discharge path includes a second NMOS transistor; wherein the drain of the first NMOS transistor is connected to the second terminal of the first capacitor, the source is connected to the output terminal of the power supply circuit, and the gate is used to receive a first control signal; the drain of the second NMOS transistor is connected to the second terminal of the second capacitor, the source is connected to the output terminal of the power supply circuit, and the gate is used to receive a second control signal.

[0011] In some embodiments, the gate terminal of the first NMOS transistor is connected to the second terminal of the second capacitor, and the gate terminal of the second NMOS transistor is connected to the second terminal of the first capacitor.

[0012] In some embodiments, the power supply circuit further includes a body bias circuit configured to provide a bias voltage to the body terminal of the first NMOS transistor, wherein the bias voltage provided to the first NMOS transistor is the lower of the second terminal voltage of the first capacitor and the output terminal voltage of the power supply circuit.

[0013] In some embodiments, the body bias circuit includes: a first switching NMOS transistor, one end of which has its source connected to the second end of the first capacitor C1, and the other end of which has its drain connected to the body end and connected to the body end of the first NMOS transistor, and the control terminal connected to the output end of the power supply circuit; and a second switching NMOS transistor, one end of which has its source connected to the output end of the power supply circuit, and the other end of which has its drain connected to the body end and connected to the body end of the first NMOS transistor, and the control terminal connected to the second end of the first capacitor C1.

[0014] In some embodiments, the body terminal of the first PMOS transistor is connected to the source terminal, and the body terminal of the second PMOS transistor is connected to the source terminal.

[0015] In some embodiments, the first control clock and the second control clock are non-overlapping clocks.

[0016] Another embodiment of this disclosure provides a negative voltage supply method applied to the power supply circuit provided in the above embodiments, comprising: providing a high-level first control clock and a low-level second control clock to charge a first capacitor based on the first control clock; providing a second control signal to provide a negative voltage to the output terminal of the power supply circuit from the second terminal of the second capacitor; providing a high-level second control clock and a low-level first control clock to charge the second capacitor based on the second control clock; and providing a first control signal to provide a negative voltage to the output terminal of the power supply circuit from the second terminal of the first capacitor, at least for improving the voltage gain and power conversion efficiency of the negative voltage supply circuit.

[0017] In some embodiments, the first control signal is provided based on the second capacitor, so that during the charging process of the second capacitor, the second terminal of the first capacitor provides a negative voltage to the output terminal of the power supply circuit; the second control signal is provided based on the first capacitor, so that during the charging process of the first capacitor, the second terminal of the second capacitor provides a negative voltage to the output terminal of the power supply circuit.

[0018] Another embodiment of this disclosure provides an electronic device that provides a negative voltage power supply based on the power supply circuit provided in the above embodiments, at least for improving the voltage gain and power conversion efficiency of the negative voltage supply circuit. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram illustrating the working principle of a charge pump circuit provided in an embodiment of the present disclosure;

[0021] Figure 2 This is a schematic diagram of a charge pump circuit applied to a CMOS integrated circuit according to an embodiment of the present disclosure;

[0022] Figure 3 This is a schematic diagram of the structure of a multi-capacitor charge pump circuit applied to a CMOS integrated circuit according to an embodiment of the present disclosure;

[0023] Figure 4 This is a schematic diagram of the power supply circuit provided in an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram of a power supply circuit including a specific first discharge path and a second discharge path is provided for an embodiment of this disclosure;

[0025] Figure 6 A schematic diagram of another power supply circuit including a specific first discharge path and a second discharge path, provided as an embodiment of this disclosure;

[0026] Figure 7 A schematic diagram of a power supply circuit with a body bias circuit provided in an embodiment of this disclosure;

[0027] Figure 8 This is a schematic diagram of the structure of a body bias circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0028] As can be seen from the background technology, the current efficiency of negative voltage power supplies is not ideal.

[0029] In response, this embodiment provides a power supply circuit that is at least used to improve the voltage gain G and power conversion efficiency PCE of the negative voltage supply circuit.

[0030] Figure 1 This is a schematic diagram illustrating the working principle of the charge pump circuit provided in this embodiment. Figure 2This is a schematic diagram of the charge pump circuit applied to CMOS integrated circuits provided in this embodiment. Figure 3 This is a schematic diagram of the structure of a multi-capacitor charge pump circuit applied to CMOS integrated circuits provided in this embodiment. Figure 4 This is a schematic diagram of the power supply circuit provided in this embodiment. Figure 5 This embodiment provides a schematic diagram of a power supply circuit including a specific first discharge path and a second discharge path. Figure 6 This embodiment provides another schematic diagram of a power supply circuit including a specific first discharge path and a second discharge path. Figure 7 This is a schematic diagram of the power supply circuit with a body bias circuit provided in this embodiment. Figure 8 The diagram below shows the structure of the body bias circuit provided in this embodiment. The power supply circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0031] In analog circuits, commonly used negative voltage generation circuits generally include buck-boost circuits and charge pump circuits. Buck-boost circuits include inductors, which occupy a very large area / volume in CMOS integrated circuits. Area / volume is a major consideration in implantable electrical stimulation systems; therefore, buck-boost circuits are unsuitable for implantable electrical stimulation systems. Charge pump circuits, on the other hand, pump charges upwards to generate voltages higher than the conventional power supply. Charge pump circuits have been used for programming floating-point devices and non-volatile memories such as EEPROM and flash memory. Charge pump circuits can achieve the provision of negative voltage by controlling MOS switches to adjust the direction of charge flow.

[0032] For the principle of generating negative voltage in a charge pump circuit, refer to... Figure 1 (a) The charge pump circuit includes a pump capacitor C and four switches S1 to S4; the charge pump circuit references [the following information] during charging. Figure 1 (b) When switches S1 and S2 are closed, a circuit is formed from top to bottom, and the power supply VDD charges the pump capacitor C. At this time, positive charge accumulates on the upper plate of the pump capacitor C, with a charge value of C*VDD, and negative charge accumulates on the lower plate of the pump capacitor C; the charge pump circuit discharges with reference to... Figure 1 (c) Switches S1 and S2 are open, and switches S3 and S4 are closed, forming a circuit from left to right. At this time, the upper plate of the pump capacitor C is grounded. Due to the conservation of charge in the capacitor, the charge of the capacitor remains C*VDD. The voltage difference between the upper and lower plates of the capacitor remains VDD, so the voltage value of the lower plate of the capacitor becomes -VDD. Since the output terminal Vout of the charge pump circuit is on the side of switch S4, the charge pump circuit provides a voltage value of -VDD on the lower plate when the pump capacitor C discharges, that is, it provides a negative voltage during discharge.

[0033] Based on the foregoing, charge pump circuits can also be used in CMOS integrated circuits. For charge pump circuits applied in CMOS integrated circuits, MOS switches are typically used to configure the specific circuitry. In some embodiments, refer to... Figure 2 The charge pump circuit includes two main NMOS switches (M1 and M2), two auxiliary NMOS switches (M3 and M4), a main clock CLK1, two auxiliary clocks (CLK1b and CLK2b), a pump capacitor C1, and two auxiliary capacitors (C1b and C2b).

[0034] for Figure 2 The charge pump circuit shown has two operating phases: Phase 1: When CLK1 is high and CLK1b is high, and CLK2b is low, M1 is turned on. At this time, the upper plate of pump capacitor C1 is connected to Vin, and the lower plate receives CLK1. CLK1 charges C1, causing positive charge to accumulate on the lower plate (high potential) and negative charge to accumulate on the upper plate (low potential). Phase 2: When CLK1 is low and CLK1b is low, and CLK2b is high, M1 is turned off and M2 is turned on. At this time, the lower plate of pump capacitor C1 is connected to a low potential. Due to the conservation of charge in the capacitor, the voltage across the capacitor remains constant, thus the upper plate of the capacitor becomes negative. Because M2 is turned on, the negative voltage of the upper plate of pump capacitor C1 is output to the output terminal Vout of the charge pump circuit, meaning the charge pump circuit provides a negative voltage to the externally connected load.

[0035] Specifically, if a valid CLK1 is provided in stage 1, CLK1 charges the pump capacitor C1, causing positive charge to accumulate on the lower plate and negative charge on the upper plate. In stage 2, CLK1 switches from a high potential to a low potential, the voltage on the upper plate of C1 becomes negative, the release path is opened, and the negative charge accumulated on the upper plate is released to Vout, causing the charge pump circuit to output a negative voltage. If a positive voltage Vin is provided in stage 1 and CLK1 is at a low potential, Vin charges the pump capacitor C1, causing negative charge to accumulate on the lower plate and positive charge on the upper plate. The voltage difference between the upper and lower plates of the capacitor is Vin, and the potential of the upper plate is Vin. In stage 2, the potential of CLK1 switches from a low potential to a high potential Vin, the charge of the capacitor remains balanced, the potential of the upper plate is pulled up to 2Vin, the release path of the upper plate is opened, and the charge pump circuit outputs twice the input voltage. In this case, the charge pump circuit acts as a voltage multiplier.

[0036] During the discharge process of pump capacitor C1 in stage 2, when CLK1 switches from high to low, the voltage difference between the upper and lower plates of pump capacitor C1 remains constant due to charge balance, making the upper plate of C1 negative. At this time, CLK1b becomes low, and the voltage level of the lower plate of C1b is still higher than negative, causing M1 to turn on again. This means that C1 is charging while discharging, affecting the discharge efficiency of C1. For the auxiliary transistor M3, its gate is connected to Vin, and its source is connected to the upper plate of C1. Since the upper plate of C1 has a low voltage (negative voltage less than Vin), M3 turns on. After M3 turns on, it clamps the lower plate of C1b to a negative voltage and pulls down the gate of M1 to a negative voltage, turning off M1. That is, by setting the auxiliary transistor M3, the charging path of pump capacitor C1 is closed while it is discharging, improving the discharge efficiency of pump capacitor C1. In addition, the fact that M3 is turned off during stage 1 does not affect the charging process of pump capacitor C1.

[0037] During Phase 1, i.e., the charging process of pump capacitor C1, when CLK1 switches from low to high, a negative voltage accumulates on the upper plate of pump capacitor C1, causing it to go low. At this time, CLK2b goes low, but the lower plate of C2b remains above the negative level, causing M2 to turn on again. This means that C1 is discharging while charging, affecting its charging efficiency. For the auxiliary transistor M4, its gate is connected to the upper plate of C1, and its source is connected to Vout. Since the upper plate of C1 has a low voltage greater than the negative voltage of Vout, M4 turns on. After M4 turns on, it clamps the lower plate of C2b to a negative voltage and pulls the gate of M2 down to a negative voltage, turning M2 off. In other words, by setting the auxiliary transistor M4, the discharge path of pump capacitor C1 is closed while it is charging, improving its charging efficiency. Furthermore, the fact that M4 is off during Phase 2 does not affect the discharge process of pump capacitor C1.

[0038] In some embodiments, reference Figure 3 , Figure 3 The circuit shown is compared to Figure 2 In the circuit shown, more pump capacitors, such as C3, can be added between M1 and M2. In this case, C3 is connected in parallel with C1, which is equivalent to increasing the capacitance value of the pump capacitor in the charge pump circuit, making the positive / negative voltage output by the charge pump circuit larger.

[0039] In some embodiments, continue to refer to Figure 3If the charge pump circuit needs to output a negative voltage, based on the aforementioned content, the principle of the charge pump circuit outputting a negative voltage is as follows: CLK1 is at a high potential, and CLK1b is at a high potential. M1 is open, and the upper plate of C1 is connected to the Vin terminal, clamping the upper plate potential of C1 to Vin. The lower plate of C1 is at the high potential of CLK1. Changing the potential of CLK1 from high to low, CLK1b also becomes a low potential, and M1 is closed. Due to the conservation of charge in the capacitor, the voltage difference between the two plates of the capacitor remains unchanged. The upper plate of C1 is pulled down to a negative voltage. When CLK2b is at a high potential, the negative voltage of the upper plate of C1 is output to the load. If cascading is considered, a capacitor, such as capacitor C2, can be placed at the Vin terminal. Capacitor C2 is charged by clock CLK2 (its function is equivalent to CLK1 controlling the charging of C1). By controlling CLK2 to be at a high potential when pump capacitor C1 is discharging, capacitor C2 is charged, causing positive charge to accumulate on the lower plate of capacitor C2. Correspondingly, negative charge will also accumulate on the upper plate of capacitor C2. Thus, when pump capacitor C1 is charging, since a large amount of negative charge has already accumulated at the Vin terminal, pump capacitor C1 can accumulate more negative charge, achieving the effect of negative voltage multiplication.

[0040] For charge pump circuits, the performance of a charge pump circuit is measured by two parameters: one is the voltage gain G, which is defined as the absolute value of the ratio of the output voltage Vout to the clock voltage VA, i.e.:

[0041] G = |Vout / VA| (1)

[0042] The output voltage Vout is related to the capacitor in the charge pump circuit and the loss voltage Vloss, specifically:

[0043] Vout= – Cp / (Cp+Cb+Cpr) + Vloss (2)

[0044] Where Cp is the size of the pump capacitor in the charge pump circuit, Cb is the size of the boost capacitor, i.e., the auxiliary capacitor (C1b or C2b), and Cpr is the parasitic capacitance between the input and the boost point or between the boost point and the output point; while the loss voltage Vloss depends on the frequency of the clock, the pump capacitor, and the output current, specifically:

[0045] Vloss=Iloss / (f * Cp) (3)

[0046] Where Iloss is the magnitude of the output current, Cp is the size of the pump capacitor, and f is the clock frequency; as can be seen from equation (3), the higher the frequency f or the larger the pump capacitor Cp, the lower the voltage loss Vloss.

[0047] The second is the power conversion efficiency (PCE), which is defined as follows:

[0048]

[0049] Where N*T is the integration period calculated by Pin, T is the period of the clock signal, and N is the number of calculation cycles.

[0050] for Figure 2 or Figure 3 The charge pump circuit shown has a relatively low clock frequency f due to the alternating charging and discharging. Equation (3) shows that a lower clock frequency f results in a higher voltage loss Vloss. Equation (2) shows that a higher voltage loss Vloss results in a lower value of |Vout|. Equation (1) shows that a lower value of |Vout| results in a lower voltage gain G, and Equation (4) shows that a lower value of |Vout| results in a lower power conversion efficiency PCE. Figure 2 or Figure 3 Although the charge pump circuit shown can provide negative voltage, the overall voltage gain G and power conversion efficiency PCE of the circuit are very low, and the load driving capability of the circuit can only reach the uA level.

[0051] In this regard, this embodiment also provides a power supply circuit, see reference. Figure 4 The power supply circuit includes: a first capacitor C1, a second capacitor C2, a first PMOS transistor P1, a second PMOS transistor P2, a first discharge path 101, and a second discharge path 102.

[0052] In this circuit, the first terminal of the first capacitor C1 is used to receive the first control clock CLK1, and the second terminal is connected to the drain terminal of the first PMOS transistor P1. The source terminal of the first PMOS transistor P1 is connected to the input terminal Vin of the power supply circuit. The first terminal of the second capacitor C2 is used to receive the second control clock CLK2, and the second terminal is connected to the drain terminal of the second PMOS transistor P2. The source terminal of the second PMOS transistor P2 is connected to the input terminal Vin of the power supply circuit. In addition, the second terminal of the first capacitor C1 is also connected to the gate terminal of the second PMOS transistor P2, and the second terminal of the second capacitor C2 is also connected to the gate terminal of the first PMOS transistor.

[0053] Among them, at most one of the first control clock CLK1 and the second control clock CLK2 is at a high level. That is, when the first control clock CLK1 is at a high level, the second control clock CLK2 cannot be at a high level, and when the second control clock CLK2 is at a high level, the first control clock CLK1 cannot be at a low level.

[0054] For the first discharge path 101 and the second discharge path 102, the input terminal of the first discharge path 101 is connected to the second terminal of the first capacitor C1, the output terminal is connected to the output terminal Vout of the power supply circuit, and the control terminal is used to receive the first control signal K1. The first discharge path 101 is configured to be driven based on the valid first control signal K1, so that the second terminal of the first capacitor C1 provides a negative voltage to the output terminal Vout of the power supply circuit. The input terminal of the second discharge path 102 is connected to the second terminal of the second capacitor C2, the output terminal is connected to the output terminal Vout of the power supply circuit, and the control terminal is used to receive the second control signal K2. The second discharge path 102 is configured to be driven based on the valid second control signal K2, so that the second terminal of the second capacitor C2 provides a negative voltage to the output terminal Vout of the power supply circuit.

[0055] for Figure 4 The working principle of the power supply circuit shown is as follows:

[0056] When the first control clock CLK1 is high, positive charge accumulates on the upper plate of the first capacitor C1, and negative charge accumulates on the lower plate of the first capacitor C1. The level at Vb1 gradually rises to a high level to turn off the second PMOS transistor P2. Since at most one of the first control clock CLK1 and the second control clock CLK2 is high, the second control clock CLK2 cannot be high at this time. That is, the level at Vb2 remains low to turn on the first PMOS transistor P1. After the first PMOS transistor P1 is turned on, the lower plate of the first capacitor C1 is connected to the input terminal Vin of the power supply circuit. Since this embodiment requires the power supply circuit to provide a negative voltage, as described above, when the first control clock CLK1 switches from high to low, the first PMOS transistor P1 is turned off, and the upper plate of the first capacitor C1 is at a low level. Due to the charge balance of the capacitor, the voltage difference between the upper and lower plates of the first capacitor C1 remains unchanged, and the potential of the lower plate of the first capacitor C1 is pulled to a negative voltage. If the first discharge path 101 is opened based on the first control signal K1, the lower plate of the first capacitor C1 provides a negative voltage to the output terminal Vout of the power supply circuit, that is, provides a negative voltage to the external load. At the same time, the second PMOS transistor P2 is turned on, and the input terminal Vin of the power supply circuit is connected to the upper plate of the second capacitor C2. The second control clock CLK2 charges the second capacitor C2, and the lower plate of the second capacitor C2 accumulates positive charge, while the upper plate accumulates negative charge.

[0057] When the second control clock CLK2 is high, positive charge accumulates on the lower plate of the second capacitor C2, and negative charge accumulates on the upper plate. The voltage level at Vb2 gradually rises to a high level, turning off the first PMOS transistor P1. Since at most one of the first control clock CLK1 and the second control clock CLK2 is high, the first control clock CLK1 cannot be high at this time. That is, the voltage level at Vb1 remains low to turn on the second PMOS transistor P2. After the second PMOS transistor P2 is turned on, the upper plate of the second capacitor C2 is connected to the input terminal Vin of the power supply circuit. Since this embodiment requires the power supply circuit to provide a negative voltage, based on the above, when the second control clock CLK2 switches from high to low, due to the charge balance effect of the capacitor, the voltage difference between the lower and upper plates of the second capacitor C2 remains unchanged, and the upper plate of the second capacitor C2 is pulled down to a negative voltage. If the second discharge path 102 is turned on based on the second control signal K2, the upper plate of the second capacitor C2 provides a negative voltage to the output terminal Vout of the power supply circuit, that is, provides a negative voltage to the external load. At the same time, the first PMOS transistor P1 is turned on, the input terminal Vin of the power supply circuit is connected to the lower plate of the first capacitor C1, and the first control clock CLK1 charges the first capacitor C1. The lower plate of the first capacitor C1 accumulates negative charge, and the upper plate accumulates positive charge.

[0058] In summary, the power supply circuit provided in this embodiment allows the first capacitor C1 and the second capacitor C2 to discharge alternately by the alternating effectiveness of the first control clock CLK1 and the second control clock CLK2. Under the condition that the power supply circuit discharges for the same time, a larger clock frequency f can be set. Based on the formulas (1) to (4) mentioned above, it can be seen that increasing the clock frequency f can improve the voltage gain G and power conversion efficiency PCE of the power supply circuit providing negative voltage.

[0059] In addition, since both the first capacitor C1 and the second capacitor C2 need to accumulate negative charge during charging, when the control clock switches from a high potential to a low potential, the plate potentials (Vb1, Vb2) of the first capacitor C1 and the second capacitor C2 connected to the corresponding discharge path will be pulled down to a negative potential. For the potential of the input terminal Vin of the power supply circuit, the first capacitor C1 and the second capacitor C2 continuously pull down the potential (Vb1, Vb2) through positive feedback, so that after the subsequent charging circuit is turned on, the accumulation speed of negative charge on the lower plate of the first capacitor C1 and the upper plate of the second capacitor C2 will be accelerated.

[0060] In some embodiments, reference Figure 5The first discharge path 101 includes a first NMOS transistor, and the second discharge path 102 includes a second NMOS transistor. The drain of the first NMOS transistor is connected to the second terminal of the first capacitor C1, the source is connected to the output terminal Vout of the power supply circuit, and the gate is used to receive the first control signal K1. The drain of the second NMOS transistor is connected to the second terminal of the second capacitor C2, the source is connected to the output terminal Vout of the power supply circuit, and the gate is used to receive the second control signal K2.

[0061] for Figure 5 The circuit shown uses the first NMOS transistor N1 and the second NMOS transistor N2 to respectively turn on and off the first discharge path 101 and the second discharge path 102, so that... Figure 4 The provided power supply circuit is compatible with CMOS integrated circuits.

[0062] In some embodiments, reference Figure 6 The gate terminal of the first NMOS transistor N1 is connected to the second terminal of the second capacitor C2, and the gate terminal of the second NMOS transistor N2 is connected to the second terminal of the first capacitor C1.

[0063] Based on the preceding discussion, when the first capacitor C1 is charging, the second capacitor C2 is discharging, requiring the second discharge path 102 to be activated. Conversely, when the first capacitor C1 is discharging, the second capacitor C2 is charging, requiring the first discharge path 101 to be activated. When the first discharge path 101 is implemented through the first NMOS transistor N1, it can be directly activated based on the high level Vb2. When the second capacitor C2 is charging, the first discharge path 101 is activated to discharge the first capacitor C1. Similarly, when the second discharge path 102 is implemented through the second NMOS transistor N2, it can be directly activated based on the high level Vb1. When the first capacitor C1 is charging, the second discharge path 102 is activated to discharge the second capacitor C2.

[0064] Furthermore, since both capacitors C1 and C2 need to release a large amount of negative charge during discharge, this negative charge flows to the load terminal (output terminal) of the power supply circuit, making the output voltage Vout of the power supply circuit negative. Regarding the potential of the output terminal Vout of the power supply circuit, the alternating discharge of capacitors C1 and C2 allows the potential of Vout to be stably clamped at a lower value, thus enabling the power supply circuit to provide a stable negative voltage.

[0065] refer to Figure 7In some embodiments, the power supply circuit further includes a body bias circuit 103, which is configured to provide a bias voltage to the body terminal of the first NMOS transistor N1. The bias voltage provided to the first NMOS transistor N1 is the lower of the voltage Vb1 at the second terminal of the first capacitor C1 and the output voltage Vout of the power supply circuit. By connecting the body terminal of the first NMOS transistor N1 to the lowest potential point of the power supply circuit, the accuracy of turning the first NMOS transistor N1 on and off is improved.

[0066] It should be noted that, in Figure 7 In the example, the body bias circuit 103 is also configured to provide a bias voltage to the body terminal of the second NMOS transistor N2, that is, by connecting the body terminal of the second NMOS transistor N2 to the lowest potential point of the power supply circuit, so as to ensure the accuracy of turning on and off the second NMOS transistor N2. The body bias circuit 103 can be configured to simultaneously provide corresponding bias voltages to the first NMOS transistor N1 and the second NMOS transistor N2 through a single body bias circuit 103, or to be configured with two separate body bias circuits 103 providing corresponding bias voltages to the first NMOS transistor N1 and the second NMOS transistor N2 respectively.

[0067] Specifically, the structure of the body bias circuit 103 used to provide bias voltage for the first NMOS transistor N1 and the second NMOS transistor is the same. In this embodiment, the structure of the body bias circuit 103 that provides bias voltage for the first NMOS transistor N1 will be described as an example. Those skilled in the art can replace the corresponding signal flow to know how the body bias circuit 103 provides bias voltage for the second NMOS transistor N2. This embodiment will not repeat the description.

[0068] Specifically, in some embodiments, reference is made to Figure 8 The body bias circuit 103 includes a first switching NMOS transistor KN1 and a second switching NMOS transistor KN2. The source terminal of the first switching NMOS transistor KN1 is connected to the second terminal of the first capacitor C1, the drain terminal is connected to the body terminal and connected to the body terminal b of the first NMOS transistor KN1, and the gate terminal is connected to the output terminal Vout of the power supply circuit. The source terminal of the second NMOS transistor KN2 is connected to the output terminal Vout of the power supply circuit, the drain terminal is connected to the body terminal and connected to the body terminal b of the first NMOS transistor KN1, and the gate terminal is connected to the second terminal of the first capacitor C1.

[0069] Specifically, when Vout is less than Vb1, the conduction level of the first switching NMOS transistor KN1 is greater than that of the second NMOS transistor KN2, and the voltage at the body terminal b of the first NMOS transistor N1 is closer to Vb1. That is, the body terminal b of the first NMOS transistor N1 is used to receive the lower of the second terminal voltage Vb1 of the first capacitor C1 and the output voltage Vout of the power supply circuit. Similarly, when Vout is greater than Vb1, the conduction level of the second NMOS transistor KN2 is greater than that of the first switching NMOS transistor KN1, and the voltage at the body terminal b of the first NMOS transistor N1 is closer to Vout. That is, the body terminal b of the first NMOS transistor N1 is used to receive the lower of the second terminal voltage Vb1 of the first capacitor C1 and the output voltage Vout of the power supply circuit.

[0070] Continue to refer to Figure 7 In some embodiments, the body terminal of the first PMOS transistor P1 is connected to the source terminal, and the body terminal of the second NMOS transistor is connected to the source terminal. That is, the body terminals of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the input terminal Vin of the power supply circuit. By connecting the body terminals of the first PMOS transistor P1 and the second PMOS transistor P2 to the lowest potential point of the power supply circuit, the accuracy of turning on and off the first PMOS transistor P1 and the second PMOS transistor P2 can be achieved.

[0071] It should be noted that the example of connecting the body terminal of the first PMOS transistor P1 to the source terminal, and connecting the body terminal of the second PMOS transistor to the source terminal, can also be applied to... Figures 4-6 In this example, the details will not be repeated.

[0072] In some embodiments, the first control clock CLK1 and the second control clock CLK2 can be set as non-overlapping clocks. "Non-overlapping clocks" means that the first control clock CLK1 and the second control clock CLK2 are out of phase with each other. That is, if the first control clock CLK1 and the second control clock CLK2 are set as non-overlapping clocks, for the power supply circuit, there is no moment when the first control clock CLK1 and the second control clock CLK2 are both at a low level. This setting allows the power supply circuit to continuously output a negative voltage, thereby improving the working stability of the power supply circuit.

[0073] The power supply circuit provided in this embodiment allows the first capacitor C1 and the second capacitor C2 to discharge alternately by the alternating effectiveness of the first control clock CLK1 and the second control clock CLK2. When the power supply circuit discharge time is the same, a larger clock frequency f can be set. Based on the formulas (1) to (4) mentioned above, it can be seen that increasing the clock frequency f can improve the voltage gain G and power conversion efficiency PCE of the power supply circuit providing negative voltage.

[0074] In addition, since both the first capacitor C1 and the second capacitor C2 need to accumulate negative charge during charging, when the control clock switches from a high potential to a low potential, the plate potentials (Vb1, Vb2) of the first capacitor C1 and the second capacitor C2 connected to the corresponding discharge path will be pulled down to a negative potential. For the potential of the input terminal Vin of the power supply circuit, the first capacitor C1 and the second capacitor C2 continuously pull down the potential (Vb1, Vb2) through positive feedback, so that after the subsequent charging circuit is turned on, the accumulation speed of negative charge on the lower plate of the first capacitor C1 and the upper plate of the second capacitor C2 will be accelerated.

[0075] Furthermore, since both capacitors C1 and C2 need to release a large amount of negative charge during discharge, this negative charge flows to the load terminal (output terminal) of the power supply circuit, making the output voltage Vout of the power supply circuit negative. Regarding the potential of the output terminal Vout of the power supply circuit, the alternating discharge of capacitors C1 and C2 allows the potential of Vout to be stably clamped at a lower value, thus enabling the power supply circuit to provide a stable negative voltage.

[0076] It should be noted that in this embodiment, the description of the transistor (whether NMOS or PMOS) is specific to "source" or "drain". The source is the source of the transistor and the drain is the drain of the transistor. However, the specific "source" or "drain" does not constitute a limitation on this embodiment. The reason is that since the transistor mentioned in this embodiment is used for switching, and its purpose is to conduct the circuit in which the transistor is located, the positions of the source and drain of the transistor can be interchanged in other embodiments. In some embodiments, the transistor can even be directly replaced by other devices with switching functions.

[0077] It should also be noted that the features disclosed in the power supply circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new power supply circuit embodiments.

[0078] Another embodiment of this disclosure provides a voltage supply method applied to the power supply circuit provided in the above embodiments, at least for improving the voltage gain and power conversion efficiency of the negative voltage supply circuit.

[0079] Specifically, the voltage supply method includes: step (1) providing a high-level first control clock and a low-level second control clock, so that the first capacitor is charged based on the first control clock. Step (2) providing a second control signal, so that the second terminal of the second capacitor provides a negative voltage to the output terminal of the power supply circuit. Step (3) providing a high-level second control clock and a low-level first control clock, so that the second capacitor is charged based on the second control clock. Step (4) providing a first control signal, so that the second terminal of the first capacitor provides a negative voltage to the output terminal of the power supply circuit.

[0080] Steps (1) and (3) are executed alternately, step (4) is executed after step (1), and step (2) is executed after step (3) to achieve alternating discharge of the first capacitor and the second capacitor, thereby improving the voltage gain and power conversion efficiency of the power supply circuit providing negative voltage.

[0081] In some embodiments, a first control signal is provided based on a second capacitor to enable the second capacitor to provide a negative voltage to the output terminal of the power supply circuit during the charging process; a second control signal is provided based on the first capacitor to enable the second capacitor to provide a negative voltage to the output terminal of the power supply circuit during the charging process.

[0082] That is, steps (1) and (2) are executed simultaneously, and steps (3) and (4) are executed simultaneously, in order to simplify the control logic of the power supply circuit.

[0083] In addition, in some embodiments, the first control clock CLK1 and the second control clock CLK2 can be set as non-overlapping clocks. With the first control clock CLK1 and the second control clock CLK2 set as non-overlapping clocks, for the power supply circuit, there is no moment when the first control clock CLK1 and the second control clock CLK2 are simultaneously at a low level. This setting allows the power supply circuit to continuously output a negative voltage, thereby improving the working stability of the power supply circuit.

[0084] Another embodiment of this disclosure provides an electronic device in which a power supply circuit based on the above embodiments provides a negative voltage, which is used to improve the voltage gain and power conversion efficiency of the negative voltage supply circuit.

[0085] Specifically, by alternating the effectiveness of the first control clock and the second control clock, the first capacitor and the second capacitor can discharge alternately. Under the condition that the power supply circuit discharge time is the same, a larger clock frequency can be set. Based on the formulas (1) to (4) mentioned above, it can be seen that increasing the clock frequency can improve the voltage gain and power conversion efficiency of the power supply circuit providing negative voltage.

[0086] In addition, since both the first and second capacitors need to accumulate negative charge during charging, when the control clock switches from a high potential to a low potential, the potential of the plates of the first and second capacitors connected to the corresponding discharge paths will be pulled down to a negative potential. For the input potential of the power supply circuit, the first and second capacitors continuously pull down the potential through positive feedback, which makes the subsequent charging circuit conduct faster, and the accumulation speed of negative charge on the lower plate of the first capacitor and the upper plate of the second capacitor accelerates.

[0087] Furthermore, since both the first and second capacitors need to release a large amount of negative charge during discharge, the negative charge from both capacitors flows to the load terminal (output terminal) of the power supply circuit, making the output voltage of the power supply circuit negative. Regarding the output potential of the power supply circuit, the alternating discharge of the first and second capacitors allows the potential to be stably clamped to a lower value, thus enabling the power supply circuit to provide a stable negative voltage. Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the protection scope of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A power supply circuit, characterized in that, include: The first capacitor has a first terminal for receiving a first control clock and a second terminal connected to the drain terminal of a first PMOS transistor, the source terminal of which is connected to the input terminal of the power supply circuit. The second capacitor has a first terminal for receiving a second control clock and a second terminal connected to the drain terminal of a second PMOS transistor, the source terminal of which is connected to the input terminal of the power supply circuit. The second terminal of the first capacitor is also connected to the gate terminal of the second PMOS transistor, and the second terminal of the second capacitor is also connected to the gate terminal of the first PMOS transistor. Among them, at most one of the first control clock and the second control clock is at a high level; The first discharge path, with its input terminal connected to the second terminal of the first capacitor and its output terminal connected to the output terminal of the power supply circuit, is configured such that, after being driven, the second terminal of the first capacitor provides a negative voltage to the output terminal of the power supply circuit. The first discharge path includes a first NMOS transistor, the drain of the first NMOS transistor is connected to the second terminal of the first capacitor, the source is connected to the output terminal of the power supply circuit, and the gate is connected to the second terminal of the second capacitor. The second discharge path, with its input terminal connected to the second terminal of the second capacitor and its output terminal connected to the output terminal of the power supply circuit, is configured such that, after being driven, the second terminal of the second capacitor provides a negative voltage to the output terminal of the power supply circuit. The second discharge path includes a second NMOS transistor, the drain of which is connected to the second terminal of the second capacitor, the source of which is connected to the output terminal of the power supply circuit, and the gate of which is connected to the second terminal of the first capacitor.

2. The power supply circuit according to claim 1, characterized in that, Also includes: The body bias circuit is configured to provide a bias voltage to the body terminal of the first NMOS transistor, wherein the bias voltage provided is the lower of the voltage at the second terminal of the first capacitor and the voltage at the output terminal of the power supply circuit.

3. The power supply circuit according to claim 2, characterized in that, The body bias circuit includes: The first switching NMOS transistor has its source terminal connected to the second terminal of the first capacitor, its drain terminal and body terminal connected together and connected to the body terminal of the first NMOS transistor, and its gate terminal connected to the output terminal of the power supply circuit. The second switching NMOS transistor has its source terminal connected to the output terminal of the power supply circuit, its drain terminal and body terminal connected to the body terminal of the first NMOS transistor, and its gate terminal connected to the second terminal of the first capacitor.

4. The power supply circuit according to claim 1, characterized in that, The body terminal of the first PMOS transistor is connected to the source terminal, and the body terminal of the second PMOS transistor is connected to the source terminal.

5. The power supply circuit according to any one of claims 1 to 4, characterized in that, The first control clock and the second control clock are non-overlapping clocks.

6. A method for providing negative voltage, applied to the power supply circuit according to any one of claims 1 to 5, characterized in that, include: A first control clock with a high level and a second control clock with a low level are provided so that the first capacitor is charged based on the first control clock. A second control signal is provided to cause the second terminal of the second capacitor to provide a negative voltage to the output terminal of the power supply circuit. A high-level second control clock and a low-level first control clock are provided so that the second capacitor is charged based on the second control clock; A first control signal is provided to cause the second terminal of the first capacitor to provide a negative voltage to the output terminal of the power supply circuit.

7. The negative voltage providing method according to claim 6, characterized in that, include: The first control signal is provided based on the second capacitor, so that during the charging process of the second capacitor, the second terminal of the first capacitor provides a negative voltage to the output terminal of the power supply circuit; The second control signal is provided based on the first capacitor, so that during the charging process of the first capacitor, the second terminal of the second capacitor provides a negative voltage to the output terminal of the power supply circuit.

8. An electronic device, characterized in that, The power supply circuit according to any one of claims 1 to 5 provides a negative voltage power supply.

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