A cut-off control circuit for a radio frequency power amplifier tube

Abstract

The application discloses a cut-off control circuit of a radio frequency power amplifier tube, which comprises a cut-off pulse generation module, a pulse level conversion module and a cut-off signal control module.The cut-off pulse generation module is used for generating a continuous pulse signal, and the frequency of the pulse signal alternately changes with a period.The pulse level conversion module is used for converting the pulse signal output by the cut-off pulse generation module into a fixed level control signal.The cut-off signal control module is used for controlling the level control signal output by the pulse level conversion module to realize the cut-off of a radio frequency source of the radio frequency power amplifier tube and the cut-off of each stage of power amplifier tubes of the radio frequency power amplifier tube respectively.The application can ensure the effectiveness, availability and safety of the cut-off control.

Description

Technical Field

[0001] This invention relates to a cut-off control circuit for an RF power amplifier tube. Background Technology

[0002] The RF power amplifier tube is a core component of the RF power amplification system. In the event of a RF system failure, the RF cutoff function must be safe, reliable, and available.

[0003] General-purpose RF power amplifier systems emphasize high power amplification efficiency and low distortion, resulting in relatively simple requirements for cutoff functions and low reliability. Current cutoff functions typically employ: power switching of the power amplifier components, level cutoff by the controller, or single-point cutoff. Power switching of the power amplifier components, due to their high power output, generates significant electromagnetic energy during the power cutoff process, easily causing failure of other functional modules. Furthermore, the cutoff circuit is complex and prone to failure. Level cutoff by the controller is susceptible to signal failure when the controller malfunctions, leading to cutoff function failure. Single-point cutoff, upon failure, causes the system to lose its external output cutoff function, impacting availability and resulting in poor reliability.

[0004] The statements herein provide only background information in relation to the present invention and do not necessarily constitute prior art. Summary of the Invention

[0005] The purpose of this invention is to provide a cut-off control circuit for an RF power amplifier tube, which can ensure the effectiveness, availability and safety of the cut-off control.

[0006] To achieve the above objectives, the present invention provides a cutoff control circuit for an RF power amplifier tube, wherein the RF power amplifier tube includes an RF source and a multi-stage power amplifier tube, and the output cutoff control circuit includes:

[0007] The cutoff pulse generation module is used to generate a continuous pulse signal, and the frequency of the pulse signal changes alternately with the period.

[0008] A pulse level conversion module is used to convert the pulse signal output by the cutoff pulse generation module into a fixed level control signal;

[0009] The cut-off signal control module is used to control the level control signals output by the pulse level conversion module to cut off the RF source of the RF power amplifier tube and cut off each stage of the RF power amplifier tube.

[0010] The cutoff pulse generation module includes a dual-channel synchronous pulse generation circuit and a first AND gate. The dual-channel synchronous pulse generation circuit includes a first pulse generation channel and a second pulse generation channel. The first clock pulse output from the first pulse generation channel and the second clock pulse output from the second pulse generation channel are input to the first AND gate, and the first AND gate outputs a continuous pulse signal P1.

[0011] The first pulse generation channel includes: a first FPGA chip and a first NMOS transistor. The input / output interface of the first FPGA chip outputs a drive signal with a first frequency to the gate of the first NMOS transistor, and the drain of the first NMOS transistor generates the first clock pulse with a first frequency.

[0012] The second pulse generation channel includes: a second FPGA chip and a second NMOS transistor. The input / output interface of the second FPGA chip outputs a drive signal with a second frequency to the gate of the second NMOS transistor, and the drain of the second NMOS transistor generates a second clock pulse with a second frequency.

[0013] The first frequency is not equal to the second frequency.

[0014] The first pulse generation channel includes a first isolation resistor, which is connected in series between the input / output interface of the first FPGA chip and the drain of the first NMOS transistor; the second pulse generation channel includes a second isolation resistor, which is connected in series between the input / output interface of the second FPGA chip and the drain of the second NMOS transistor.

[0015] The first FPGA chip and the second FPGA chip are logically synchronized; in the first time period, the first pulse generation channel outputs a first clock pulse with a first frequency, and the second pulse generation channel outputs a low level; in the second time period, the first pulse generation channel outputs a low level, and the second pulse generation channel outputs a second clock pulse with a second frequency.

[0016] The cutoff signal control module includes an RF source cutoff control circuit and a power amplifier tube cutoff control circuit.

[0017] The radio frequency source cutoff control circuit includes a second AND gate. The two input terminals of the second AND gate are respectively input to the signal source output by the radio frequency source and the level control signal P2 output by the pulse level conversion module. The output terminal of the second AND gate outputs a first cutoff control signal to the gate of the first stage power amplifier tube.

[0018] The power amplifier cutoff control circuit includes at least two power amplifier cutoff control circuits. The number of power amplifier cutoff control circuits is the same as the number of stages of the power amplifier tube in the RF power amplifier tube. The power amplifier cutoff control circuit includes an NOT gate and a transistor. The input terminal of the NOT gate is input with the level control signal P2 output by the pulse level conversion module. The output terminal of the NOT gate is connected to the base of the transistor. The emitter of the transistor is grounded. The collector of the transistor is connected to the gate of any stage of the RF power amplifier tube.

[0019] The cutoff pulse generation module also includes a signal filtering and acquisition processing module. The signal filtering and acquisition processing module acquires frequency signals from the coaxial cable at the output end of the RF power amplifier tube. After filtering out the frequency bands of the signal source from the RF source from the acquired frequency signals, it feeds them back to the first FPGA chip and the second FPGA chip respectively to determine whether the output frequencies of the first FPGA chip and the second FPGA chip are abnormal.

[0020] The pulse level conversion module includes: a transformer, a shaping module, and a filtering module. The transformer realizes the amplitude conversion of the pulse signal; the shaping module shapes the pulse signal into a DC signal; and the filtering module filters out noise during the shaping process.

[0021] The cut-off control circuit also includes a magnetic flux detection module, which is used to detect the load magnetic flux at the output of the RF power amplifier tube to determine the effectiveness of the cut-off control.

[0022] Compared with the prior art, the present invention has the following innovative points and beneficial effects (advantages):

[0023] By sampling the pulse cutoff signal from the dual-channel FPGA chip, the failure of the controller can be prevented, and the safety of the controller's cutoff control signal can be guaranteed.

[0024] By setting multiple disconnection nodes on the output link, the output can be effectively disconnected even if a single node fails.

[0025] The final output load status is determined, and the entire closed-loop link converges, effectively ensuring the availability of the system in case of disconnection.

[0026] The cut-off function is independent of the power supply and does not involve controlling the power supply of other modules, effectively reducing the electromagnetic coupling impact on other modules of the system. Attached Figure Description

[0027] Figure 1 This is a circuit diagram of a cut-off control circuit for an RF power amplifier tube provided by the present invention.

[0028] Figure 2 This is a schematic diagram of the pulse signal output by the cutoff pulse generation module.

[0029] Figure 3 This is a schematic diagram of the circuit module for the pulse level conversion module.

[0030] Figure 4 This is a circuit diagram of the cut-off signal control module. Detailed Implementation

[0031] The following is based on Figures 1-4 The preferred embodiments of the present invention will be described in detail below.

[0032] like Figure 1 As shown, the present invention provides a cut-off control circuit for an RF power amplifier transistor, the cut-off control circuit comprising:

[0033] Cut-off pulse generation module 1 is used to generate a continuous pulse signal, and the frequency of the pulse signal changes alternately with the period;

[0034] The pulse level conversion module 2 is used to convert the pulse signal output by the cutoff pulse generation module 1 into a fixed level control signal.

[0035] The cut-off signal control module 3 is used to control the level control signal output by the pulse level conversion module 2 to cut off the RF source of the RF power amplifier tube and each stage of the power amplifier circuit.

[0036] The magnetic flux detection module 4 is used to detect the load magnetic flux at the output of the RF power amplifier tube to determine the effectiveness of the cut-off control.

[0037] Specifically, the cutoff pulse generation module 1 includes a dual-channel synchronous pulse generation circuit and an AND gate A1. The dual-channel synchronous pulse generation circuit includes two pulse generation channels, and the two pulse generation channels have identical structures. The first pulse generation channel includes a first FPGA chip and a first NMOS transistor. The input / output (I / O) interface of the first FPGA chip outputs a drive signal with a first frequency to the gate of the first NMOS transistor, and the drain of the first NMOS transistor generates a first clock pulse with a first frequency. The second pulse generation channel includes a second FPGA chip and a second NMOS transistor. The input / output (I / O) interface of the second FPGA chip outputs a drive signal with a second frequency to the gate of the second NMOS transistor, and the drain of the second NMOS transistor generates a second clock pulse with a second frequency. The first frequency is not equal to the second frequency. In this embodiment, the first frequency is 83kHz and the second frequency is 100kHz because the pulse frequencies generated by the first pulse generation channel and the second pulse generation channel are different. A first isolation resistor R1 is set in the first pulse generation channel, connected in series between the input / output interface of the first FPGA chip and the drain of the first NMOS transistor. Similarly, a second isolation resistor R2 is set in the second pulse generation channel, connected in series between the input / output interface of the second FPGA chip and the drain of the second NMOS transistor. The first isolation resistor R1 and the second isolation resistor R2 achieve frequency isolation between the first pulse generation channel and the second pulse generation channel. The first clock pulse output from the first pulse generation channel and the second clock pulse output from the second pulse generation channel are input to the AND gate A1, and the AND gate A1 outputs a continuous pulse signal P1.

[0038] The first FPGA chip and the second FPGA chip perform logical synchronization through time-division multiplexing. For example... Figure 2As shown, during time period T1, the first FPGA chip of the first pulse generation channel generates a pulse with frequency f1, while the second pulse generation channel outputs a low level at the gate of the second FPGA chip. During time period T2, the first pulse generation channel outputs a low level at the gate of the first FPGA chip, while the second pulse generation channel generates a pulse with frequency f2. The pulse signals output by the two channels are logically ANDed by the AND gate A1 to generate continuous pulse signals P1 with different frequencies at different intervals. The two FPGA chips constitute two channel cutoff redundancy modules. When the FPGA chips of both channels are working normally, a single channel FPGA device can detect its own frequency pulse and also detect the frequency pulse of the FPGA device of the other channel. In other words, the state of a single channel can be monitored by the other channel. When the FPGA device of one channel fails, the FPGA device's I / O port will generate a fixed high level, pulling the entire output pulse down to ground, thereby cutting off the pulse output. The result of the cutoff is judged by sampling the pulse through the first isolation resistor R1 and the second isolation resistor R2 using another I / O port. Finally, the pulse signal P1 output by the AND gate A1 will output a logic "0".

[0039] Furthermore, such as Figure 1 As shown, the cutoff pulse generation module 1 further includes a signal filtering and acquisition processing module 101. This module acquires frequency signals from the coaxial cable at the output of the RF power amplifier tube. After filtering out the frequency band of the RF transmission signal from the RF crystal oscillator 501 from the acquired frequency signals, it feeds them back to the first FPGA chip and the second FPGA chip respectively to determine whether the output frequencies of the first FPGA chip and the second FPGA chip are abnormal. If the pulse frequency output by any FPGA chip is abnormal, that FPGA chip performs a cutoff operation, that is, it directly sets the gate of the corresponding NMOS transistor to a high level, pulling the pulse signal down to ground. This creates a near short circuit between the drain and source of the NMOS transistor, causing the drain of the NMOS transistor to output a low level, thereby cutting off the clock pulse output.

[0040] like Figure 3 As shown, the pulse level conversion module 2 includes: a transformer 201, a shaping module 202, and a filtering module 203. The transformer 201 performs amplitude conversion of the pulse signal; the shaping module 202 shapes the pulse signal into a DC signal; and the filtering module 203 filters out noise during the shaping process to achieve a final stable DC output. In this embodiment, the pulse level conversion module 2 outputs a high-level control signal.

[0041] like Figure 4As shown, this embodiment uses a radio frequency power amplifier tube containing a two-stage power amplifier circuit for illustration. The signal source from the radio frequency crystal oscillator 501 is input to the gate of the first-stage power amplifier tube M1 of the radio frequency power amplifier tube. The first-stage amplified signal output from the drain of the first-stage power amplifier tube M1 is input to the gate of the second-stage power amplifier tube M2. The second-stage amplified signal is output from the drain of the second-stage power amplifier tube M2. The second-stage amplified signal is used as the final amplified signal and is output to the load antenna through a coaxial cable. The cutoff signal control module 3 includes an RF source cutoff control circuit and a power amplifier tube cutoff control circuit. The RF source cutoff control circuit includes an AND gate A2. The two inputs of the AND gate A2 are respectively input to the signal source output by the RF crystal oscillator 501 and the high-level control signal P2 output by the pulse level conversion module 2. The output of the AND gate A2 outputs a first cutoff control signal to the gate of the first-stage power amplifier tube M1. Under normal circumstances, the pulse level conversion module 2 outputs a high-level signal. The signal source output by the RF crystal oscillator 501 and the high-level control signal P2 output by the pulse level conversion module 2 are output through AND logic. When the control signal P2 fails, i.e., in the event of a fault, the output of the pulse level conversion module 2 becomes low, one input of the AND gate A2 becomes low, and the output of the AND gate A2 also becomes low, thereby cutting off the output of the RF crystal oscillator 501. The power amplifier cutoff control circuit includes a first-stage power amplifier cutoff control circuit and a second-stage power amplifier cutoff control circuit. The first-stage power amplifier cutoff control circuit includes a first NOT gate N1 and a first transistor Q1. The input terminal of the first NOT gate N1 receives the high-level control signal P2 output by the pulse level conversion module 2. The output terminal of the first NOT gate N1 is connected to the base of the first transistor Q1. The collector of the first transistor Q1 is connected to the gate of the first-stage power amplifier transistor M1. The emitter of the first transistor Q1 is grounded. Under normal circumstances, the pulse level conversion module 2 outputs a high-level signal, so the first NOT gate N1 outputs a low-level signal to the base of the first transistor Q1, and the first transistor Q1 is cut off. When the control signal P2 fails, i.e., in the event of a fault, the output of the pulse level conversion module 2 becomes low, so the first NOT gate N1 outputs a high-level signal to the base of the first transistor Q1, and the first transistor Q1 is turned on. The collector of the first transistor Q1 outputs a low-level signal to the gate of the first-stage power amplifier transistor M1, causing the first-stage power amplifier transistor M1 to be cut off and stop outputting signals.Similarly, the second-stage power amplifier cutoff control circuit includes a second NOT gate N2 and a second transistor Q2. The input terminal of the second NOT gate N2 receives the high-level control signal P2 output by the pulse level conversion module 2. The output terminal of the second NOT gate N2 is connected to the base of the second transistor Q2. The collector of the second transistor Q2 is connected to the gate of the second-stage power amplifier transistor M2. The emitter of the second transistor Q2 is grounded. Under normal circumstances, the pulse level conversion module 2 outputs a high-level signal, so the second NOT gate N2 outputs a low-level signal to the base of the second transistor Q2, and the second transistor Q2 is cut off. When the control signal P2 fails, i.e., in the event of a fault, the output of the pulse level conversion module 2 becomes low, so the second NOT gate N2 outputs a high-level signal to the base of the second transistor Q2, and the second transistor Q2 is turned on. The collector of the second transistor Q2 outputs a low-level signal to the gate of the second-stage power amplifier transistor M2, causing the second-stage power amplifier transistor M2 to be cut off and stop the output signal. This embodiment sets three cutoff signal input points—the output point of the RF crystal oscillator, the gate of the first-stage power amplifier tube, and the gate of the second-stage power amplifier tube—to perform cutoff control simultaneously. A failure at any of these input points will not affect the final cutoff effect, ensuring safe cutoff.

[0042] When the RF power amplifier tube output is cut off, the output energy, after passing through the antenna system, should result in a transmitted magnetic flux of 0. For example... Figure 1 As shown, the magnetic flux detection module 4 is used to detect whether the magnetic flux at the output end of the RF power amplifier tube is 0, so as to determine whether the final output result meets the expected result of the power amplifier output cutoff.

[0043] It should be noted that, in the embodiments of the present invention, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the embodiments. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0045] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A cutoff control circuit for an RF power amplifier tube, wherein the RF power amplifier tube comprises an RF source and a multi-stage power amplifier tube, characterized in that, The cut-off control circuit includes: The cutoff pulse generation module is used to generate a continuous pulse signal, and the frequency of the pulse signal changes alternately with the period. A pulse level conversion module is used to convert the pulse signal output by the cutoff pulse generation module into a fixed level control signal; The cut-off signal control module is used to control the level control signal output by the pulse level conversion module to cut off the RF source of the RF power amplifier tube and cut off each stage of the RF power amplifier tube respectively. The cutoff signal control module includes an RF source cutoff control circuit and a power amplifier tube cutoff control circuit. The radio frequency source cutoff control circuit includes a second AND gate. The two input terminals of the second AND gate are respectively input to the signal source output by the radio frequency source and the level control signal output by the pulse level conversion module. The output terminal of the second AND gate outputs a first cutoff control signal to the gate of the first stage power amplifier tube. The power amplifier tube cutoff control circuit includes at least two power amplifier cutoff control circuits. The number of power amplifier cutoff control circuits is the same as the number of stages of the power amplifier tube in the RF power amplifier tube. The power amplifier cutoff control circuit includes an NOT gate and a transistor. The input terminal of the NOT gate receives the level control signal output by the pulse level conversion module. The output terminal of the NOT gate is connected to the base of the transistor. The emitter of the transistor is grounded. The collector of the transistor is connected to the gate of any stage of the RF power amplifier tube.

2. The cutoff control circuit for the RF power amplifier tube as described in claim 1, characterized in that, The cutoff pulse generation module includes a dual-channel synchronous pulse generation circuit and a first AND gate. The dual-channel synchronous pulse generation circuit includes a first pulse generation channel and a second pulse generation channel. The first clock pulse output from the first pulse generation channel and the second clock pulse output from the second pulse generation channel are input to the first AND gate, and the first AND gate outputs a continuous pulse signal.

3. The cutoff control circuit for the RF power amplifier tube as described in claim 2, characterized in that, The first pulse generation channel includes: a first FPGA chip and a first NMOS transistor. The input / output interface of the first FPGA chip outputs a drive signal with a first frequency to the gate of the first NMOS transistor, and the drain of the first NMOS transistor generates the first clock pulse with a first frequency. The second pulse generation channel includes: a second FPGA chip and a second NMOS transistor. The input / output interface of the second FPGA chip outputs a drive signal with a second frequency to the gate of the second NMOS transistor, and the drain of the second NMOS transistor generates a second clock pulse with a second frequency.

4. The cutoff control circuit for the RF power amplifier tube as described in claim 3, characterized in that, The first frequency is not equal to the second frequency.

5. The cutoff control circuit for the RF power amplifier tube as described in claim 4, characterized in that, The first pulse generation channel includes a first isolation resistor, which is connected in series between the input / output interface of the first FPGA chip and the drain of the first NMOS transistor; the second pulse generation channel includes a second isolation resistor, which is connected in series between the input / output interface of the second FPGA chip and the drain of the second NMOS transistor.

6. The cutoff control circuit for the RF power amplifier tube as described in claim 4, characterized in that, The first FPGA chip and the second FPGA chip are logically synchronized; during the first time period, the first pulse generation channel outputs a first clock pulse with a first frequency, and the second pulse generation channel outputs a low level. During the second time period, the first pulse generation channel outputs a low level, while the second pulse generation channel outputs a second clock pulse with a second frequency.

7. The cutoff control circuit for the RF power amplifier tube as described in claim 6, characterized in that, The cutoff pulse generation module also includes a signal filtering and acquisition processing module. The signal filtering and acquisition processing module acquires frequency signals from the coaxial cable at the output end of the RF power amplifier tube. After filtering out the frequency bands of the signal source from the RF source from the acquired frequency signals, it feeds them back to the first FPGA chip and the second FPGA chip respectively to determine whether the output frequencies of the first FPGA chip and the second FPGA chip are abnormal.

8. The cutoff control circuit for the RF power amplifier tube as described in claim 1, characterized in that, The pulse level conversion module includes: a transformer, a shaping module, and a filtering module. The transformer realizes the amplitude conversion of the pulse signal; the shaping module shapes the pulse signal into a DC signal; and the filtering module filters out noise during the shaping process.

9. The cutoff control circuit for the RF power amplifier tube as described in any one of claims 1-8, characterized in that, The cut-off control circuit also includes a magnetic flux detection module, which is used to detect the load magnetic flux at the output of the RF power amplifier tube to determine the effectiveness of the cut-off control.

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