A method for constructing and FPGA circuit implementation of a chaotic synchronization system based on a memristor

Abstract

This invention provides a method for constructing and implementing a memristor-based chaotic synchronization system using FPGA circuits, comprising the following steps: Step 1, constructing the memristor chaotic synchronization system; Step 2, discretizing the memristor chaotic synchronization system to obtain discretized equations; Step 3, designing the various modules of the FPGA chaotic signal generator and converting the discretized equations into a hardware design language; Step 4, designing based on a state machine to solve the chaotic sequence; Step 5, simulating and verifying the designed program at the board level, and analyzing the implementation effect. This invention incorporates a memristor into the chaotic synchronization system, giving it more complex dynamic behavior and noise immunity, enabling it to reach synchronization faster and achieve stable error convergence. This solution addresses the shortcomings of current chaotic systems using analog circuits, such as unstable signals and susceptibility to external environmental interference, and can resist temperature changes and electromagnetic interference, generating high-quality chaotic signals.

Description

Technical Field

[0001] This invention relates to the field of analog circuit technology, and in particular to a method for constructing and implementing a chaotic synchronization system based on memristors using FPGA circuits. Background Technology

[0002] Nonlinear science is a comprehensive discipline, its development based on various branches characterized by nonlinearity. Among them, chaos theory, as one of the most important parts of nonlinear science, has broad application prospects in fields such as secure communication systems, neural networks, artificial intelligence, load forecasting, and signal detection, and has received increasing attention in recent years. Chaotic systems exhibit sensitivity to initial conditions and complexity in chaotic signals, which enables their widespread application in nonlinear science, information science, secure communication, and other engineering fields. In the field of signal detection and processing, the nonlinear characteristics of chaotic systems can be used to improve signal recognition and extraction, and chaotic signal processing techniques can be applied to communication systems, radar systems, etc., to improve signal anti-interference capabilities and information extraction efficiency.

[0003] The generation of chaotic phenomena mainly depends on nonlinear devices in the circuit system. The existing method for generating chaotic signals is mainly to build basic operational circuits by combining discrete components such as operational amplifiers, capacitors, and resistors. The shortcomings of this approach are mainly reflected in the following two points: (1) Analog devices are easily affected by temperature and voltage changes, and the parameters of the components will change as the devices age. Environmental factors may also cause electromagnetic interference and noise to the components, causing their values ​​to change and affecting the experimental results; (2) Analog circuits cannot be reused after being built. Each circuit can only correspond to one chaotic circuit, resulting in poor versatility. Summary of the Invention

[0004] This invention proposes a method for constructing and implementing a chaotic synchronization system based on memristors using FPGA circuits. This method expands the state space and dynamic range of the chaotic system, making the dynamic behavior of the system richer and more complex.

[0005] Specifically, this invention provides a method for constructing and implementing a memristor-based chaotic synchronization system using an FPGA circuit. The method includes the following steps:

[0006] Step 1: Construct the memristor chaotic synchronization system;

[0007] Step 2: Discretize the memristor chaotic synchronization system to obtain the discretized equations;

[0008] Step 3: Design the various modules of the FPGA chaotic signal generator and convert the discretized equations into a hardware design language;

[0009] Step 4: Design based on state machine to solve the chaotic sequence;

[0010] Step 5: Simulate and verify the designed program at the board level, and analyze the implementation effect.

[0011] Furthermore, step 1 also includes the following steps:

[0012] Step 11: Add the memristor to the Van der pol-Duffing chaotic system to obtain the mathematical model;

[0013] Step 12: Add a controller u to the mathematical model to obtain a chaotic synchronization system model based on memristors;

[0014] Step 13: Define the error system, transforming the synchronization problem of the synchronization system into the stability problem of the error system.

[0015] Furthermore, in step 11, the mathematical model and its differential equation are as follows:

[0016]

[0017]

[0018] Where x(t) represents voltage, α represents nonlinear damping coefficient, F represents amplitude of sinusoidal signal, and ω represents angular frequency of sinusoidal signal. The memristor value represents the magnetic flux density. It means, that is a and b are both constants, and the magnetic flux is... It equals the integral of the voltage across the memristor over time; x1, x2, and x3 are the state variables of the system.

[0019] Furthermore, in step 12, a controller u is added to the differential equation of the mathematical model, resulting in:

[0020]

[0021] Where y1, y2, and y3 are the state variables of the system, the formula for the chaotic synchronization system based on memristors is:

[0022]

[0023] Where u is the controller, the controller u is designed as follows:

[0024]

[0025] Where u1, u2, u3 are constants, and e1, e2, e3 represent y1-x1, y2-x2, y3-x3 respectively.

[0026] Furthermore, in step 13, the error system is defined as e = yx, then:

[0027]

[0028] The synchronization problem of a synchronous system is transformed into a stability problem of an error system, where the controller u needs to satisfy... i = 1, 2, 3, 4.

[0029] Furthermore, step 2 also includes the following steps:

[0030] Step 21: Construct the oscillator model of the memristor chaotic synchronization system;

[0031] Select controller parameters: u1 = 0, u2 = -2, u3 = -1. The mathematical model of a memristor chaotic synchronization system can be expressed as:

[0032]

[0033] Step 22: Discretize the oscillator model of the memristor chaotic synchronization system.

[0034] The above equation (7) is discretized using the improved Euler algorithm, resulting in the following discretized equation:

[0035]

[0036] in:

[0037]

[0038]

[0039] Where, x n y n z n j n k n l n Let x be the discrete value of the state variable at the current moment. n+1 y n+1 z n+1 j n+1 k n+1 l n+1 Let h be the discrete value of the state variable at the next time step, and h be the iteration step size. This is the driving force signal.

[0040] Furthermore, in step 3, the FPGA chaotic signal generator includes a DDS module, an Euler module, and a DAC output module;

[0041] The DDS module generates the driving force signal required by the system, decomposes the sine signal into 4096 equal parts, stores them in the ROM block of the FPGA, and reads the value of the sine signal by reading the address of the RAM and provides it to the Euler module for calculation.

[0042] The Euler module calculates the discrete values ​​of the state variables at the next iteration time by processing the input discrete signal.

[0043] The DAC output module converts the chaotic variable values ​​calculated by the Euler module into analog signals and transmits them to an oscilloscope for display.

[0044] Furthermore, in step 4, the Euler module uses a state machine to solve the chaotic sequence. The states of the state machine include:

[0045] S0 state: Initializes all registers on the rising edge of the master clock, for x n y n z n Initialize the values ​​and set cnt = 0 and flag = 0, then the state machine jumps to state S1.

[0046] S1 state: The address of the ROM is obtained by calculating the value of w*t, and then the sine value at this time is read out. At the same time, x is calculated. n 2 y n 2 Then set flag = 0, and the state machine jumps to state S2;

[0047] S2 state: Update the calculation of the cubic term y n 2 z n x n 2 y n At the same time, the state machine jumps to state S3;

[0048] S3 state: Calculate f on the rising edge of the master clock. x f y f z At the same time, it checks whether the value of cnt is 0. If cnt is 0, the state machine jumps to state S4; if cnt is not 0, the state machine jumps to state S6.

[0049] S4 state: Save g1, g2, and g3 on the rising edge of the master clock, and simultaneously register x at this time. n y nz n The state machine transitions to state S5 when the value is reached.

[0050] S5 state: Calculate x on the rising edge of the master clock. n+1 y n+1 z n+1 Then set cnt = 1, update the value of t, and the state machine jumps to state S1;

[0051] S6 state: save f1, f2, and f3 on the rising edge of the master clock, and the state machine jumps to the S7 state;

[0052] S7 state: Calculate x n y n z n The output value is set to flag, and the state machine transitions to state S1.

[0053] The beneficial effects achieved by this invention are:

[0054] This invention proposes a method for constructing and implementing a memristor-based chaotic synchronization system using FPGA circuits. Compared with known chaotic synchronization systems, this system incorporates a memristor, resulting in more complex dynamic behavior and noise immunity. It achieves synchronization faster, with stable error convergence. Furthermore, this approach addresses the shortcomings of current chaotic systems using analog circuits, such as signal instability and susceptibility to external environmental interference. It significantly resists temperature changes and electromagnetic interference, generates high-quality chaotic signals, and offers shorter synchronization time and better stability compared to analog circuits. Therefore, it has significant advantages in the field of weak signal detection. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of the overall modular design of a method for constructing and implementing a memristor-based chaotic synchronization system using FPGA circuits, provided in an embodiment of the present invention.

[0056] Figure 2 A schematic diagram of the state machine transition in a method for constructing and implementing a memristor-based chaotic synchronization system using an FPGA circuit, provided in an embodiment of the present invention;

[0057] Figure 3 The system phase diagram of a method for constructing and implementing a memristor-based chaotic synchronization system using FPGA circuits, as provided in this embodiment of the invention, shows the system phase diagram when the system is not synchronized.

[0058] Figure 4 This is a schematic diagram of the error curve when the system is not synchronized in a method for constructing and implementing a memristor-based chaotic synchronization system using an FPGA circuit, as provided in an embodiment of the present invention.

[0059] Figure 5 The zl phase diagram of the unsynchronized system in the construction and FPGA circuit implementation method of a memristor-based chaotic synchronization system provided in this embodiment of the invention;

[0060] Figure 6 The system phase diagram for system synchronization in the construction and FPGA circuit implementation method of a memristor-based chaotic synchronization system provided in this embodiment of the invention;

[0061] Figure 7 This is a schematic diagram of the error curve during system synchronization in a method for constructing and implementing a memristor-based chaotic synchronization system using an FPGA circuit, as provided in an embodiment of the present invention.

[0062] Figure 8 The zl phase diagram during system synchronization is provided in the method for constructing and implementing a memristor-based chaotic synchronization system using FPGA circuits in an embodiment of the present invention.

[0063] Figure 9 This is a schematic diagram of the physical circuit connection in a method for constructing and implementing a memristor-based chaotic synchronization system using an FPGA circuit, as provided in an embodiment of the present invention.

[0064] Figure 10 The XL phase diagram displayed on an oscilloscope in a method for constructing and implementing a memristor-based chaotic synchronization system using an FPGA circuit, as provided in an embodiment of the present invention. Detailed Implementation

[0065] The technical solution of the present invention will be described in more detail below with reference to the accompanying drawings. The present invention includes, but is not limited to, the following embodiments.

[0066] like Figure 1 As shown, this invention provides a method for constructing and implementing a memristor-based chaotic synchronization system on an FPGA circuit. Based on an improved Euler algorithm, this invention converts the chaotic synchronization system into a discrete chaotic system, describes the chaotic system directly using the VerilogHDL hardware description language, implements the memristor chaotic synchronization system on an FPGA, and displays the synchronization curve of the chaotic attractor and the time-domain chaotic signal on an oscilloscope by outputting the generated signal through a high-speed DAC.

[0067] Includes the following steps:

[0068] Step 1: Construct the memristor chaotic synchronization system.

[0069] This invention provides a memristor-based chaotic synchronization system, the construction process of which includes the following steps:

[0070] Step 11, the mathematical model obtained by adding the memristor to the Van der Pohl-Duffing chaotic system is expressed as follows:

[0071]

[0072] Where x(t) represents voltage, α represents nonlinear damping coefficient, F represents amplitude of sinusoidal signal, and ω represents angular frequency of sinusoidal signal. The memristor value represents the magnetic flux density. It means, that is a and b are both constants, and the magnetic flux is... It equals the integral of the voltage across the memristor over time.

[0073] Equation (1) can be expressed as a differential equation as shown in equation (2):

[0074]

[0075] Where x1, x2, and x3 are the state variables of the system.

[0076] Step 12, copy formula (2) and add a controller u to obtain formula (3):

[0077]

[0078] Where y1, y2, and y3 are the state variables of the system, the formula for the chaotic synchronization system based on memristors can be derived from the above formula as follows:

[0079]

[0080] Where u is the controller, the controller u is designed as follows:

[0081]

[0082] Where u1, u2, u3 are constants, and e1, e2, e3 represent y1-x1, y2-x2, y3-x3 respectively.

[0083] Step 13, define the error system as e = yx, then we have:

[0084] (6)

[0086] The synchronization problem of the synchronization system (3) is then transformed into the stability problem of the error system (as shown in formula (5)), that is, the controller u needs to satisfy the following: i = 1, 2, 3, 4.

[0087] Step 2: Discretize the system to obtain the discretized equations.

[0088] Includes the following steps:

[0089] Step 21: Construct the oscillator model of the memristor chaotic synchronization system;

[0090] Select a set of controller parameters: u1 = 0, u2 = -2, u3 = -1. The mathematical model of the above memristor chaotic synchronization system can then be expressed as:

[0091]

[0092] Step 22: Discretize the oscillator model of the memristor chaotic synchronization system;

[0093] The above equation (7) is discretized using the improved Euler algorithm, resulting in the following discretized equation:

[0094]

[0095] in:

[0096]

[0097]

[0098] Where x n y n z n j n k n l n Let x be the discrete value of the state variable at the current moment. n+1 y n+1 z n+1 j n+1 k n+1 l n+1 Let h be the discrete value of the state variable at the next time step, and h be the iteration step size. This is the driving force signal.

[0099] Step 3: Design the various modules of the FPGA chaotic signal generator and convert the discretized equations into a hardware design language.

[0100] To conserve hardware resources, this invention designs a circuit combining sequential and combinational logic. The sequential part mainly uses a state machine to implement the circuit's functional logic, while the combinational logic mainly implements the multiplication and truncation operations of quadratic and cubic terms in the calculation process. A modular design of the chaotic system is achieved using an FPGA, and the overall structure is as follows: Figure 1 As shown.

[0101] The FPGA chaotic signal generator includes: a DDS module, an Euler module, and a DAC output module.

[0102] The DDS module generates the driving force signal required by the system, decomposes the sine signal into 4096 equal parts, stores them in the ROM block of the FPGA, and reads the value of the sine signal by reading the address of the RAM and provides it to the Euler module for calculation.

[0103] The Euler module calculates the discrete values ​​of the state variables at the next time step after the iteration, based on the input discrete signal.

[0104] The DAC output module converts the chaotic variable values ​​calculated by the Euler module into analog signals and transmits them to an oscilloscope for display. Since a 14-bit DAC is used, the chaotic variable values ​​transmitted from the Euler module need to be truncated to 14 bits.

[0105] Step 4: Design based on state machine to solve the chaotic sequence.

[0106] Due to the word length limitations of digital systems, regardless of the computational precision used, the chaotic sequence obtained through digital design can only approximate the actual continuous chaotic system. Therefore, for the system obtained after discretization, the Euler module uses a state machine approach to solve the chaotic sequence, and its state transition is as follows: Figure 2 As shown, the states of the state machine include:

[0107] S0 state: Initializes all registers on the rising edge of the master clock, for x n y n z n Initialize the values ​​and set cnt = 0 and flag = 0, then the state machine jumps to state S1.

[0108] S1 state: The address of the ROM is obtained by calculating the value of w*t, and then the sine value at this time is read out. At the same time, x is calculated. n 2 y n 2 Then set flag = 0, and the state machine jumps to state S2;

[0109] S2 state: Update the calculation of the cubic term y n 2 z n x n 2 y n At the same time, the state machine jumps to state S3;

[0110] S3 state: Calculate f on the rising edge of the master clock. x f y f zAt the same time, it checks whether the value of cnt is 0. If cnt is 0, the state machine jumps to state S4; if cnt is not 0, the state machine jumps to state S6.

[0111] S4 state: Save g1, g2, and g3 on the rising edge of the master clock, and simultaneously register x at this time. n y n z n The state machine transitions to state S5 when the value is reached.

[0112] S5 state: Calculate x on the rising edge of the master clock. n+1 y n+1 z n+1 Then set cnt = 1, update the value of t, and the state machine jumps to state S1;

[0113] S6 state: save f1, f2, and f3 on the rising edge of the master clock, and the state machine jumps to the S7 state;

[0114] S7 state: Calculate x n y n z n The output value is set to flag, and the state machine transitions to state S1.

[0115] Step 5: Simulate and verify the designed program at the board level, and analyze the implementation effect.

[0116] After the design of each functional module of the chaotic digital system is completed, the FPGA programming flow is followed, sequentially executing RTL encoding, functional simulation, timing constraint addition, and program compilation. Finally, the compiled file is burned into the FPGA for experimental verification. This invention uses an FPGA development board with a Cyclone IV EP4CE10F17C8 chip and Altera's Quartus II 13.0 software for Verilog HDL hardware description language programming, thereby completing the hardware implementation of the dynamic behavior of the chaotic system.

[0117] To debug the timing functionality of the hardware code generation circuit, testbench code was written, and the designed circuit was then simulated in Modelsim simulation software. Given different initial values ​​for the synchronous system, and without a controller u, the phase diagram of the system is as follows: Figure 3 As shown, the curve of its error e changing with time is as follows: Figure 4 As shown, the xl phase diagram is as follows Figure 5 As shown, the system exhibits poor correlation, and the synchronization error curve changes continuously over time.

[0118] After controller u is added to the system, the phase diagram of the system is as follows: Figure 6As shown, the curve of its error e changing with time is as follows: Figure 7 As shown, the xl phase diagram is as follows Figure 8 As shown in the figure, the system exhibits good correlation, and the synchronization error curve decreases continuously over time until it reaches 0.

[0119] To more intuitively illustrate the circuit's stability, this design uses a dual-channel 14-bit, 125Msp DAC chip (AD9767) to convert digital signals into analog signals. The system phase diagram is then displayed on an oscilloscope. The physical circuit connections are shown below. Figure 9 As shown.

[0120] Figure 10 The figure shows the XL phase diagram of the circuit on the oscilloscope. The shape is roughly the same as the software simulation, indicating that the designed circuit can maintain chaotic behavior stably for a long time, verifying the feasibility of realizing a chaotic system. The stable output shows that the system has good robustness, verifying the effectiveness and reliability of the design.

[0121] This invention is not limited to the specific embodiments described above. Those skilled in the art can implement this invention using various other specific embodiments based on the disclosed content of the embodiments and accompanying drawings. Therefore, any design that adopts the design structure and concept of this invention and makes some simple changes or modifications falls within the protection scope of this invention.

Claims

1. A method for constructing and implementing a memristor-based chaotic synchronization system using FPGA circuitry, characterized in that, The method for constructing and implementing the memristor-based chaotic synchronization system using FPGA circuits includes the following steps: Step 1: Construct a memristor-based chaotic synchronization system; Step 2: Discretize the chaotic synchronization system based on memristors to obtain the discretized equations; Step 3: Design the various modules of the FPGA chaotic signal generator and convert the discretized equations into a hardware design language; Step 4: Design based on state machine to solve the chaotic sequence; Step 5: Simulate and verify the designed program at the board level, and analyze the implementation effect; Step 1 also includes the following steps: Step 11: Add the memristor to the Van der pol-Duffing chaotic system to obtain the mathematical model; Step 12, add a controller to the mathematical model. Thus, a chaotic synchronization system model based on memristors was obtained; Step 13: Define the error system, transforming the synchronization problem of the memristor-based chaotic synchronization system into the stability problem of the error system; In step 11, the mathematical model and its differential equation are as follows: ； ； Where, x Indicates voltage. Represents the nonlinear damping coefficient. Let ω represent the amplitude of the sinusoidal signal, ω represent the angular frequency of the sinusoidal signal, and W(φ) represent the memristor value, which is represented by the magnetic flux φ, i.e. a and b are both constants, and the magnetic flux φ is equal to the integral of the voltage across the memristor over time. These are the state variables of the Van der Pohl-Duffing chaotic system with added memristors; In step 12, a controller is added to the differential equation of the mathematical model. ,get: ； in, The state variable of the controller, the formula for a chaotic synchronization system based on memristors is: ； in, Design a controller. for: (5) in, It is a constant. They represent ; In step 13, the error system is defined as follows: ,have: ； The synchronization problem of a memristor-based chaotic synchronization system is transformed into a stability problem of an error system for the controller. Need to meet , .

2. The method for constructing and implementing a memristor-based chaotic synchronization system using FPGA circuits according to claim 1, characterized in that, Step 2 also includes the following steps: Step 21: Construct the oscillator model of the chaotic synchronization system based on memristors; Select controller parameters: , The oscillator model of a chaotic synchronization system based on memristors can be represented as: ； Step 22: Discretize the oscillator model of the memristor-based chaotic synchronization system. The oscillator model of the memristor-based chaotic synchronization system is discretized using the improved Euler algorithm, resulting in the following discretized equations: ； in: ； ； in, These are the discrete values ​​of the state variables at the current moment. Let h be the discrete value of the state variable at the next time step, and h be the iteration step size. This is the driving force signal.

3. The method for constructing and implementing a memristor-based chaotic synchronization system using FPGA circuits according to claim 2, characterized in that, In step 3, the FPGA chaotic signal generator includes a DDS module, an Euler module, and a DAC output module; The DDS module generates the driving force signal required by the system, decomposes the sine signal into 4096 equal parts, stores them in the ROM block of the FPGA, and reads the value of the sine signal by reading the address of the RAM and provides it to the Euler module for calculation. The Euler module calculates the discrete values ​​of the state variables at the next iteration time by processing the input discrete signal. The DAC output module converts the chaotic variable values ​​calculated by the Euler module into analog signals and transmits them to an oscilloscope for display.

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