Memory cell read operation techniques

Abstract

This application relates to memory cell read operation techniques. A memory device can determine a starting voltage for a second phase of a read operation on a set of memory cells, which can have a different magnitude than a starting voltage for a first phase of the read operation. For example, the memory device can determine the starting voltage for the second phase using a termination voltage for the first phase. In some cases, the starting voltage for the second phase can correspond to a difference of a voltage offset and the termination voltage for the first phase. As part of the second phase of the read operation, the memory device can apply a sequence of voltages to the set of memory cells according to the determined starting voltage for the second phase.

Description

[0001] Cross-reference

[0002] The present patent application claims priority to U.S. Patent Application No. 17 / 877,613, titled “MEMORY CELL READ OPERATION TECHNIQUES,” by Muzzetto et al., filed July 29, 2022, assigned to the assignee of the present application and expressly incorporated by reference herein. TECHNICAL FIELD

[0003] The technical field relates to memory cell read operation techniques. BACKGROUND

[0004] Memory devices are widely used in electronic systems to store information. Information is stored by programming memory cells within the memory devices into various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logical one or a logical zero. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, components can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the states stored in the memory devices. To store information, components can write (e.g., program, set, assign) states in the memory devices.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selecting memory, chalcogenide memory technology, and others. Memory cells can be described in terms of volatile or non-volatile configurations. Memory cells configured in non-volatile configurations can maintain stored logic states for long periods of time, even in the absence of an external power source. Memory cells configured in volatile configurations can lose stored states when disconnected from an external power source. SUMMARY

[0006] A method is described. The method can include, as part of a first phase of a read operation for a set of memory cells, applying a first sequence of voltages having a first polarity to the set of memory cells, the first sequence of voltages associated with a first start voltage; determining, based at least in part on a termination voltage in the first sequence of voltages, a second start voltage associated with a second sequence of voltages having a second polarity, the second start voltage having a different magnitude than a magnitude of the first start voltage; and as part of a second phase of the read operation, applying the second sequence of voltages to the set of memory cells according to the second start voltage.

[0007] An apparatus is described. The apparatus can include a controller; an array of memory cells; and logic coupled with the controller, the logic configured to: as part of a first phase of a read operation for the array of memory cells, determine a first start voltage in a first sequence of voltages associated with the first phase of the read operation, the first sequence of voltages having a first polarity; as part of the first phase of the read operation, output an indication of the first start voltage for application to the array of memory cells; as part of a second phase of the read operation and based at least in part on a termination voltage in the first sequence of voltages, determine a second start voltage associated with a second sequence of voltages having a second polarity, the second start voltage having a different magnitude than a magnitude of the first start voltage; and as part of the second phase of the read operation, output an indication of the second start voltage for application to the array of memory cells.

[0008] An apparatus is described. The apparatus can include a set of memory cells; and a controller configured to cause the apparatus to: as part of a first phase of a read operation for the set of memory cells, apply a first sequence of voltages having a first polarity to the set of memory cells, the first sequence of voltages associated with a first start voltage; determine, based at least in part on a termination voltage in the first sequence of voltages, a second start voltage associated with a second sequence of voltages having a second polarity, the second start voltage having a different magnitude than a magnitude of the first start voltage; and as part of a second phase of the read operation, apply the second sequence of voltages to the set of memory cells according to the second start voltage. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a memory array supporting memory cell read operation techniques in accordance with examples as disclosed herein is described.

[0010] Figure 2 An example of a memory array supporting memory cell read operation techniques in accordance with examples as disclosed herein is described.

[0011] Figure 3A and 3B A side view illustrating an example of a memory array that supports memory cell read operation techniques, as disclosed herein.

[0012] Figure 4 This document describes an example of a voltage diagram supporting a memory cell read operation technique, as illustrated in the examples disclosed herein.

[0013] Figure 5 This document describes examples of systems that support memory cell read operation techniques, as illustrated in the examples disclosed herein.

[0014] Figure 6 A block diagram illustrating a memory device that supports memory cell read operation techniques according to examples disclosed herein.

[0015] Figure 7 The flowchart illustrates one or more methods for supporting memory cell read operation techniques based on examples disclosed herein. Detailed Implementation

[0016] Some memory devices may include multilevel memory cells configured to store one of a variety (e.g., three or more) of supported logic states, such as ternary memory cells configured to store one of three logic states, and other types of multilevel memory cells. Each supported logic state may correspond to a corresponding threshold voltage of the memory cell. In some cases, the magnitude of the threshold voltage of the memory cell storing a given logic state may depend on the polarity of the voltage applied to the memory cell. This polarity dependency of the threshold voltage can be used to support read operations on a set of memory cells comprising two phases. For example, in an instance of reading a set of ternary memory cells, during the first phase, a first voltage sequence with an incrementing first polarity may be applied to the set of memory cells to determine (e.g., based on a first subset of ternary memory cells activated in response to the application of the first voltage sequence) a first subset of memory cells storing a first logic state. During the second phase, a second voltage sequence with a second polarity having an incremental value can be applied to the set of memory cells to determine (e.g., based on a second subset of ternary memory cells activated in response to the application of the second sequence voltage) a second subset of memory cells storing the second logic state. A third subset of the remaining memory cells not activated in response to the application of the first or second voltage sequence can be determined to store the third logic state. Therefore, the logic state stored by each of the memory cells can be determined during the two-phase read operation.

[0017] However, in some instances, the threshold voltage corresponding to the logic state of a memory cell may drift over time. Therefore, the latency associated with a read operation may increase, for example, as the number of voltages contained in the voltage sequence (e.g., the number of steps) increases to account for the drifting threshold voltage (e.g., to activate a corresponding subset of memory cells). Therefore, techniques are needed to improve the efficiency and latency of read operations.

[0018] As described herein, the memory device can determine the starting voltage (e.g., V) in the voltage sequence of the second phase of a two-phase read operation. init (NEG)), the starting voltage may have the same starting voltage as the starting voltage in the voltage sequence of the first stage of the two-stage read operation (e.g., V). init The values ​​of (POS) can be different. For example, a memory device may use the termination voltage (e.g., V) in the voltage sequence of the first stage. stop (POS, the last voltage in the voltage sequence of the first stage) determines the starting voltage of the second stage of the read operation. In some cases, the magnitude of the starting voltage of the second stage may be based on or correspond to (e.g., equal to) the difference between the voltage offset and the termination voltage of the first stage (e.g., V). init (NEG)=-(V stop (POS)-V offset Therefore, the starting voltage of the second stage may not be based on or correspond to a negative value (e.g., the opposite value) of the starting voltage of the first stage, but may be based on the ending voltage of the first stage. Since the starting voltages have different magnitudes, the second stage of the read operation can contain fewer voltage steps, which in turn reduces read operation latency. For example, using a larger magnitude starting voltage for the second stage may result in fewer steps required to reach the end of the threshold voltage distribution associated with reading the second logic state during the second stage. Therefore, the number of voltages included in the voltage sequence of the second stage can be reduced, thereby reducing read operation latency.

[0019] First refer to Figure 1 , 2 Features of this disclosure are described in the context of memory devices and arrays, 3A and 3B. References Figures 4-5 Features of this disclosure are described in the context of voltage diagrams and systems. (See references...) Figures 6-7 The device diagrams and flowcharts described in connection with the memory cell read operation techniques further illustrate and describe these and other features of this disclosure, and are referred to in the device diagrams and flowcharts.

[0020] Figure 1This describes an example of a memory device 100 that supports memory cell read operation techniques according to the examples disclosed herein. In some examples, the memory device 100 may be referred to as or comprise a memory die, a memory chip, or an electronic memory device. The memory device 100 is operable to provide a location (e.g., a physical memory address) for storing information, which can be used by a system (e.g., by a host device coupled to the memory device 100 for writing information, for reading information).

[0021] Memory device 100 may include one or more memory cells 105, each programmable to store different logic states (e.g., a set of two or more possible states programmed). For example, memory cells 105 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cells 105 (e.g., multilevel memory cells 105) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 105 may be arranged in an array.

[0022] Memory cell 105 may use configurable materials to store logical states. These configurable materials may be referred to as memory elements, storage elements, memory storage elements, material elements, material memory elements, material portions, or polarity write material portions, etc. The configurable material of memory cell 105 may refer to chalcogenide-based storage components. For example, chalcogenide storage elements may be used in phase-change memory cells, thresholding memory cells, or self-selection memory cells, as well as other architectures.

[0023] In some instances, the material of memory cell 105 may comprise chalcogenide materials or other alloys, including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some instances, chalcogenide materials primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some instances, SAG alloys may also comprise silicon (Si), and such chalcogenide materials may be referred to as SiSAG alloys. In some instances, SAG alloys may comprise silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, or combinations thereof, respectively. In some instances, the chalcogenide material may comprise additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each element in atomic or molecular form.

[0024] In some instances, memory cell 105 may be an example of a phase-change memory cell. In such instances, the material used in memory cell 105 may be based on an alloy (e.g., the alloys listed above) and may be operable to change to different physical states (e.g., undergo a phase transition) during normal operation of memory cell 105. For example, phase-change memory cell 105 may be associated with a relatively disordered atomic configuration (e.g., a relatively amorphous state) and a relatively ordered atomic configuration (e.g., a relatively crystalline state). The relatively disordered atomic configuration may correspond to a first logic state (e.g., a reset state, logic 0), while the relatively ordered atomic configuration may correspond to a second logic state (e.g., a logic state different from the first logic state, a set state, logic 1).

[0025] In some instances (e.g., for thresholding memory cell 105, for self-selecting memory cell 105), some or all of a set of logic states supported by memory cell 105 may be associated with a relatively disordered atomic configuration of a chalcogenide material (e.g., amorphous materials are operable to store different logic states). In some instances, the storage element of memory cell 105 may be an example of a self-selecting storage element. In such instances, the material used in memory cell 105 may be based on an alloy (e.g., alloys listed above) and may be operable to undergo changes in different physical states during normal operation of memory cell 105. For example, self-selecting or thresholding memory cell 105 may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logic state (e.g., a reset state, logic 0), while the low threshold voltage state may correspond to a second logic state (e.g., a logic state different from the first logic state, a set state, logic 1).

[0026] During a write operation (e.g., a programming operation) of the self-selected or thresholded memory cell 105, the polarity of the write operation can affect (e.g., determine, set, program) the behavior or characteristics of the material of the memory cell 105, such as the thresholding characteristics of the material (e.g., threshold voltage). The difference between the thresholding characteristics of the material of the memory cell 105 for different logic states stored by the material of the memory cell 105 (e.g., the difference between the threshold voltage when the material stores logic state '0' and the threshold voltage when the material stores logic state '1') can correspond to the read window of the memory cell 105.

[0027] Memory device 100 may include access lines arranged in a pattern such as a grid pattern (e.g., row lines 115 extending along the illustrative x-direction and column lines 125 extending along the illustrative y-direction). The access lines may be formed of one or more conductive materials. In some instances, row line 115 or a portion thereof may be referred to as a word line. In some instances, column line 125 or a portion thereof may be referred to as a number line or bit line. Without loss of understanding, references to access lines or the like are interchangeable. Memory cells 105 may be located, for example, at the intersection of the access lines of row line 115 and column line 125. In some instances, such as in embodiments where several groups of memory cells 105 are located at different levels (e.g., layers, stacks, planes, planes) along the illustrative z-direction, the memory cells 105 may also be arranged (e.g., addressed) along the illustrative z-direction. In some instances, the memory device 100, which contains memory cells 105 at different levels, may be supported by a configuration of access lines, decoders and other supporting circuitry that is different from that shown.

[0028] Read and write operations can be performed on memory cell 105 by activating one or more of the access lines, such as row line 115 or column line 125, and other access lines associated with alternative configurations. For example, by activating row line 115 and column line 125 (e.g., applying voltage to row line 115 or column line 125), memory cell 105 can be accessed based on their intersection point. In various two-dimensional or three-dimensional configurations, the intersection point of row line 115 and column line 125, as well as other access lines, may be referred to as the address of memory cell 105. In some instances, the access line may be a conductive line coupled to memory cell 105 and can be used to perform access operations on memory cell 105. In some instances, memory device 100 may perform operations in response to a command, which may be issued by a host device coupled to memory device 100 or generated by memory device 100 (e.g., by local memory controller 150).

[0029] Access to memory cell 105 can be controlled by one or more decoders (e.g., row decoder 110 or column decoder 120, and other instances). For example, row decoder 110 may receive row addresses from local memory controller 150 and activate row line 115 based on the received row addresses. Column decoder 120 may receive column addresses from local memory controller 150 and activate column line 125 based on the received column addresses.

[0030] Sensing component 130 is operable to detect the state of memory cell 105 (e.g., material state, resistance state, threshold state) and determine the logic state of memory cell 105 based on the detected state. Sensing component 130 may include one or more sensing amplifiers for converting (e.g., amplifying) signals generated by accessing memory cell 105 (e.g., signals from column line 125 or other access lines). Sensing component 130 may compare the signals detected from memory cell 105 with a reference 135 (e.g., reference voltage, reference charge, reference current). The detected logic state of memory cell 105 may be provided as an output of sensing component 130 (e.g., provided to input / output component 140) and may be indicated to another component of memory device 100 or to a host device coupled to memory device 100.

[0031] The local memory controller 150 can control access to memory cells 105 through various components (e.g., row decoder 110, column decoder 120, sensing component 130, and other components). In some instances, one or more of the row decoder 110, column decoder 120, and sensing component 130 may be co-located with the local memory controller 150. The local memory controller 150 is operable to receive information (e.g., commands, data) from one or more different controllers (e.g., an external memory controller associated with a host device, another controller associated with memory device 100), translate the information into signaling usable by memory device 100, perform one or more operations on memory cells 105, and transfer data from memory device 100 to host device based on the performance of one or more operations. The local memory controller 150 can generate row address signals and column address signals to activate access lines, such as target row line 115 and target column line 125. The local memory controller 150 can also generate and control various signals (e.g., voltage, current) used during operation of memory device 100. Generally, the amplitude, shape, or duration of the applied signal discussed herein may vary and may differ for the various operations discussed when operating the memory device 100.

[0032] The local memory controller 150 is operable to perform one or more access operations on one or more memory cells 105 of the memory device 100. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed by the local memory controller 150 in response to an access command (e.g., from a host device) or otherwise coordinated. The local memory controller 150 is operable to perform other access operations not listed herein or other operations related to the operation of the memory device 100 but not directly related to accessing the memory cells 105.

[0033] Memory device 100 may include any number of non-transitory computer-readable media that support memory cell read operation techniques. For example, local memory controller 150, row decoder 110, column decoder 120, sensing component 130, or input / output component 140, or any combination thereof, may include or be accessible one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions attributed to memory device 100 herein. For example, such instructions, when executed by memory device 100, may cause memory device 100 to perform one or more associated functions as described herein.

[0034] According to the examples disclosed herein, memory device 100 can perform a two-stage read operation to read a set of memory cells 105. According to the examples described herein, memory device 100 can determine a starting voltage in a voltage sequence for the second stage of the two-stage read operation, the starting voltage having a magnitude different from the magnitude of the starting voltage in the voltage sequence for the first stage of the read operation. For example, memory device 100 can use the ending voltage in the voltage sequence of the first stage to determine the starting voltage of the second stage. In some cases, the magnitude of the starting voltage of the second stage may correspond to (e.g., equal to) the difference between the voltage offset and the ending voltage of the first stage. Therefore, the starting voltage of the second stage may not correspond to a negative value of the starting voltage of the first stage, but may be based on the ending voltage of the first stage. Because the starting voltages have different magnitudes, the second stage of the read operation can contain fewer voltage steps, which in turn reduces read operation latency. For example, using a larger magnitude starting voltage for the second stage can result in fewer steps to reach the end of the threshold voltage distribution associated with the read logic state during the second stage.

[0035] Figure 2 , 3A Section 3B describes an example of a memory array 200 that supports memory cell read operation technology according to examples disclosed herein. The memory array 200 may be included in a memory device 100, and an example of a three-dimensional arrangement of memory cells 105 accessible by various conductive structures (e.g., access lines) is illustrated. Figure 2 Explain the relationship between memory array 200 and, for example: Figure 3A and 3B The top cross-sectional view of section AA shown in the figure (e.g., section AA). Figure 3A Explain the relationship between memory array 200 and, for example: Figure 2 The side section view of section BB shown in the figure (e.g., section BB). Figure 3B Explain the relationship between memory array 200 and, for example: Figure 2The cross-sectional view shown is a side view of section CC (e.g., section CC). This cross-sectional view may be an example of a cross-sectional view of the memory array 200, where some aspects (e.g., dielectric structures) are omitted for clarity. The elements of the memory array 200 may be described relative to the x, y, and z directions, as shown... Figure 2 , 3A And as explained in each of 3B. Although marked with numerical indicators. Figure 2 , 3A And some elements included in 3B, while other corresponding elements are not labeled, but they are the same or will be understood to be similar, in order to increase the visibility and clarity of the depicted features. In addition, although a number of repeating elements are shown in the illustrative example of memory array 200, the techniques according to the examples described herein are applicable to any number of such elements, or the ratio between the number of one repeating element and another repeating element.

[0036] In an example of memory array 200, memory cells 105 and word lines 205 can be configured according to hierarchy 230 (e.g., stack-up, layer, plane, level, such as...). Figure 3A and 3B (As illustrated herein) Distributed along the z-direction. In some instances, the z-direction may be orthogonal to a substrate (not shown) of the memory array 200, which may be located below the illustrated structure along the z-direction. Although the illustrative example of the memory array 200 includes four layers 230, the memory array 200 according to the examples disclosed herein may include any number of one or more layers 230 along the z-direction (e.g., 64 layers, 128 layers).

[0037] Each word line 205 may be an example of a portion of an access line formed of one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, word lines 205 may be formed as comb-like structures, including portions (e.g., protrusions, forks) extending along the y-direction through gaps (e.g., alternating gaps) between the pillars 220. For example, as illustrated, memory array 200 may include two word lines 205 per level 230 (e.g., odd-number line 205-a-n1 and even-number line 205-a-n2 according to a given level n), wherein such word lines 205 of the same level 230 may be described as interleaved (e.g., wherein portions of odd-number line 205-a-n1 protrude along the y-direction between portions of even-number line 205-a-n2, and vice versa). In some instances, (e.g., level 230) odd-number lines 205 may be associated with a first memory cell 105 on a first side of a given pillar 220 (e.g., along the x-direction), and (e.g., level 230) even-number lines may be associated with a second memory cell 105 on a second side of a given pillar 220 (e.g., along the x-direction, opposite to the first memory cell 105). Therefore, in some instances, memory cells 105 of a given level 230 may be addressed (e.g., selected, activated) based on either even-number lines 205 or odd-number lines 205.

[0038] Each pillar 220 may be an example of an access line (e.g., a conductive pillar portion) formed of one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, the pillars 220 may be arranged in a two-dimensional array (e.g., in the xy plane) having a first number of pillars 220 along a first direction (e.g., eight pillars along the x-direction, eight rows of pillars) and a second number of pillars 220 along a second direction (e.g., five pillars along the y-direction, five columns of pillars). Although the illustrative example of memory array 200 includes a two-dimensional arrangement of eight pillars 220 along the x-direction and five pillars 220 along the y-direction, the memory array 200 according to the examples disclosed herein may include any number of pillars 220 along the x-direction and any number of pillars 220 along the y-direction. Furthermore, as illustrated, each pillar 220 may be coupled to a corresponding set of memory cells 105 (e.g., one or more memory cells 105 per level 230 along the z-direction). The support 220 may have a cross-sectional area in the xy plane extending along the z direction. Although it is described as having a circular cross-sectional area in the xy plane, the support 220 may be formed in different shapes, such as having an elliptical, square, rectangular, polygonal or other cross-sectional area in the xy plane.

[0039] Each memory cell 105 may contain a chalcogenide material. In some instances, memory cells 105 may be instances of thresholded memory cells. Each memory cell 105 may be accessed (e.g., addressed, selected) based on the intersection between word line 205 (e.g., a hierarchy selection, which may include even or odd selections within hierarchy 230) and pillar 220. For example, as illustrated, the selected memory cell 105-a of hierarchy 230-a-3 may be accessed based on the intersection between pillar 220-a-43 and word line 205-a-32.

[0040] An access bias (e.g., access voltage V) can be applied across memory cell 105. access The first voltage (which can be positive or negative) is used to access (e.g., write to, read from) memory cell 105. In some instances, this can be done by using a first voltage (e.g., V). access / 2) Bias the selected word line 205 and by using a second voltage (e.g., -V) access / 2) The selected pillar 220 is biased to apply an access bias voltage, which may have an opposite sign to the first voltage. For the selected memory cell 105-a, a corresponding access bias voltage (e.g., the first voltage) may be applied to word line 205-a-32, while other unselected word lines 205 may be grounded (e.g., biased to 0V). In some instances, the word line bias may be provided by a word line driver (not shown) coupled to one or more of the word lines 205.

[0041] To apply a corresponding access bias (e.g., a second voltage) to the pillar 220, the pillar 220 may be configured to selectively couple to the sensing line 215 (e.g., a digital line, column line, or access line extending along the y-direction) via a corresponding transistor 225 coupled between the pillar 220 and the sensing line 215 (e.g., physical ground, electrical ground). In some instances, the transistor 225 may be a vertical transistor (e.g., a transistor with a channel along the z-direction, a transistor with a semiconductor junction along the z-direction), which may be formed over the substrate of the memory array 200 using various techniques (e.g., thin-film technology). In some instances, the selected pillar 220, the selected sensing line 215, or a combination thereof may serve as a reference. Figure 1 The instance of the selected column line 125 described (e.g., a bit line).

[0042] Transistor 225 (e.g., the channel portion of transistor 225) may be activated by gate lines 210 (e.g., activation lines, select lines, row lines, access lines extending along the x-direction) coupled to the respective gates of a group of transistors 225 (e.g., a group of transistors along the x-direction). In other words, each of the pillars 220 may have a first end (e.g., a bottom end facing the negative z-direction) configured for coupling with an access line (e.g., a sense line 215). In some instances, gate lines 210, transistors 225, or both may be considered components of row decoder 110 (e.g., as pillar decoder components). In some instances, selection (e.g., bias) of pillar 220 or sense line 215, or various combinations thereof, may be supported by column decoder 120 or sense component 130, or both.

[0043] To adjust the corresponding access bias (e.g., -V) access / 2) An access bias voltage can be applied to the pillar 220-a-43 to bias the sensing line 215-a-4, and the gate line 210-a-3 can be grounded (e.g., biased to 0V) or otherwise biased with an activation voltage. In an example where transistor 225 is an n-type transistor, the gate line 210-a-3, biased with a voltage relatively higher than that of the sensing line 215-a-4, can activate transistor 225-a (e.g., cause transistor 225-a to operate in the on state), thereby coupling the pillar 220-a-43 to the sensing line 215-a-4 and biasing the pillar 220-a-43 with the associated access bias voltage. However, transistor 225 may contain different channel types or may operate according to different bias schemes to support various access operations.

[0044] In some instances, when transistor 225-a is activated, unselected pillars 220 of the memory array 200 may be electrically floated or coupled to another voltage source (e.g., ground, via a high-resistance path, via a leakage path) to prevent voltage drift of pillar 220. For example, a ground voltage applied to gate line 210-a-3 may not activate other transistors coupled to gate line 210-a-3 because the ground voltage of gate line 210-a-3 may not be greater than the voltage of other sensing lines 215 (e.g., which may be biased with ground voltage or may be floating). Furthermore, a voltage equal to or similar to the access bias (e.g., -V) can be used. access / 2, or some other negative bias or a bias voltage relatively close to the access bias voltage) bias other unselected gate lines 210 (including such as Figure 3AThe gate line 210-a-5 shown in the diagram is configured such that transistor 225 along the unselected gate line 210 is not activated. Therefore, transistor 225-b coupled to gate line 210-a-5 can be deactivated (e.g., operated in a non-conductive state), thereby isolating the voltage of sensing line 215-a-4 from pillar 220-a-45 and the other pillars 220.

[0045] During a write operation, a write bias can be applied across memory cell 105 (e.g., where V...). access =V write The write bias (which can be a positive or negative voltage) is used to write to memory cell 105. In some instances, the polarity of the write bias can affect (e.g., determine, set, program) the behavior or characteristics of the material of memory cell 105, such as the threshold voltage of the material. For example, applying a write bias with a first polarity can set the material of memory cell 105 with a first threshold voltage, which may be associated with storing logic 0. Furthermore, applying a write bias with a second polarity (e.g., opposite to the first polarity) can set the material of memory cell 105 with a second threshold voltage, which may be associated with storing logic 1. The difference between the threshold voltages of the material of memory cell 105 for different logic states stored by the material of memory cell 105 (e.g., the difference between the threshold voltage when the material stores logic state '0' and the threshold voltage when the material stores logic state '1') may correspond to the read window of memory cell 105.

[0046] During a read operation, a read bias voltage (e.g., where V) can be applied across memory cell 105. access =V read The memory cell 105 is read using a voltage (which can be positive or negative). In some instances, the logic state of the memory cell 105 can be evaluated based on whether the memory cell 105 is thresholded in the presence of an applied read bias. For example, this read bias may cause the memory cell 105 storing a first logic state (e.g., logic 0) to be thresholded (e.g., allowing current flow, allowing current above a threshold current), and may not cause the memory cell 105 storing a second logic state (e.g., logic 1) to be thresholded (e.g., not allowing current flow, allowing current below a threshold current).

[0047] The memory array 200 can support reading the logical states of a selected set of memory cells 105. For example, the memory array 200 can support a two-stage read operation, wherein a first read bias sequence of a first polarity can be applied across the set of ternary memory cells 105 during a first stage of the read operation, and a second read bias sequence of a second polarity can be applied across the set of ternary memory cells 105 during a second stage of the read operation. Ternary memory cells 105 that are thresholded in response to the application of the first read bias sequence can be determined to store a first logical state, and ternary memory cells 105 that are thresholded in response to the application of the second read bias sequence can be determined to store a second logical state. Ternary memory cells 105 that are not thresholded in response to the application of either the first or second read bias sequence can be determined to store a third logical state. Therefore, the logical state stored by each of the ternary memory cells 105 can be determined based on the application of the first and second read bias sequences across the ternary memory cells 105.

[0048] According to the examples disclosed herein, circuitry associated with memory array 200 can determine the starting read bias of a second read bias sequence for a second stage of a read operation, such that the starting read bias has a different magnitude than the starting read bias of a first read bias sequence for a first stage of the read operation. For example, the circuitry can identify a terminating read bias in the first read bias sequence and determine the starting read bias of the second read bias sequence based on the terminating read bias. In some cases, the magnitude of the starting read bias of the second read bias sequence can be equal to the difference between the voltage offset and the terminating read bias in the first read bias sequence. Therefore, the starting read bias of the second read bias sequence may not correspond to a negative value of the starting read bias of the first read bias sequence, but may be based on the terminating voltage in the first read bias sequence. Since the starting read bias of the second read bias is determined based on the terminating read bias, the second read bias sequence can contain fewer read biases than the first read bias sequence, which further reduces read operation latency. For example, the magnitude of the initial read bias of the second read bias sequence may be greater than the magnitude of the initial read bias of the first read bias sequence, which may result in fewer steps used to reach the end of the threshold voltage distribution associated with reading the second logic state during the second phase.

[0049] Figure 4 This describes an example of a voltage diagram 400 supporting memory cell read operation technology, as disclosed herein. The voltage diagram 400 can be derived from the examples described herein (including references to...). Figure 1 and 2This can be implemented by aspects of the memory device 100 or memory array 200 (up to 3B). For example, voltage diagram 400 can be implemented by the memory device (e.g., memory device 100, memory device including memory array 200) to support a two-stage read operation technique with reduced latency.

[0050] Voltage diagram 400 depicts the threshold voltage distribution of memory cells in a memory device that can be configured to store one of three supported logic states (e.g., the threshold voltage distribution of ternary memory cells). For example, voltage diagram 400 may include a threshold voltage distribution 405 corresponding to a first group of memory cells storing a first logic state, a threshold voltage distribution 410 corresponding to a second group of memory cells storing a second logic state, and a threshold voltage distribution 415 corresponding to a third group of memory cells storing a third logic state. That is, the first group of memory cells may have a threshold voltage within threshold voltage distribution 405 and therefore can store the first logic state, the second group of memory cells may have a threshold voltage within threshold voltage distribution 410 and therefore can store the second logic state, and so on.

[0051] In some instances, the magnitude of the threshold voltage of a memory cell may depend on the polarity of the voltage applied to the memory cell. For example, a first memory cell storing a first logic state may have a first threshold voltage of a first polarity within a threshold voltage distribution 405-a of a first polarity (e.g., positive polarity) and a second threshold voltage of a second polarity within a threshold voltage distribution 405-b of a second polarity (e.g., negative polarity). The first threshold voltage may have a different magnitude than the second threshold voltage. Similarly, a second memory cell storing a second logic state may have a first threshold voltage of a first polarity within a threshold voltage distribution 410-a and a second threshold voltage of a second polarity within a threshold voltage distribution 410-b, the second threshold voltage having a different magnitude than the first threshold voltage within the threshold voltage distribution 410-a. A third memory cell storing a third logic state may have a first threshold voltage of a first polarity within a threshold voltage distribution 415-a and a second threshold voltage of a second polarity within a threshold voltage distribution 415-b, the second threshold voltage having a different magnitude than the first threshold voltage within the threshold voltage distribution 415-a.

[0052] The memory device can perform a two-stage (e.g., two-part, two-sub-operation) read operation that utilizes the polarity dependence of threshold voltages to determine the corresponding number of memory cells storing each of the three supported logic states. As part of the first stage of the read operation, the memory device can determine the number of memory cells storing the first logic state by applying a first voltage sequence 420 with a first polarity having an incrementing value to the set of memory cells. The first voltage sequence 420 may be associated with a first starting voltage 425 having a first magnitude 455, which may be predetermined or otherwise stored in the memory device (e.g., read from a register or lookup table (LUT)). For each voltage in the first voltage sequence 420 applied to the set of memory cells, the memory device can determine the number of memory cells having a value less than the threshold voltage applied. That is, the memory device can determine the number of memory cells activated (e.g., thresholded) in response to the application of each voltage in the first voltage sequence 420. In some instances, the memory device may use a determined number of memory cells (e.g., the number of memory cells that have been activated so far in the first voltage sequence 420) to identify the step size (e.g., the magnitude of the next voltage in the first voltage sequence 420) of the next voltage in the first voltage sequence 420.

[0053] The memory device may determine the total number of memory cells storing a first logic state based at least in part on a termination voltage 430 applied in a first voltage sequence 420. For example, the termination voltage 430 may be the last voltage in the first voltage sequence 420 applied to the set of memory cells as part of a first phase of a read operation. The memory device may determine which memory cells (e.g., those with threshold voltages within threshold voltage distribution 405-a) are activated in response to the voltages of the first voltage sequence 420 and store the first logic state. In some instances, the memory device may determine the termination voltage 430 based on a threshold number of memory cells activated in response to the first voltage sequence 420. For example, as the memory device applies voltages to the first voltage sequence 420, it may track the total number of memory cells activated since the application of a first start voltage 425. If the total number of activated memory cells meets (e.g., reaches or exceeds) a threshold number, the memory device may determine the last applied voltage as the termination voltage 430. In some cases, the memory device may determine the termination voltage 430 based on a determined number. For example, if the determined number drops below a threshold, the memory device can determine that each memory cell having a threshold voltage within the threshold voltage distribution 405-a has been read. In some instances, the memory device can determine the termination voltage 430 based at least in part on the number of detected errors. For example, the memory device may include an error correction circuitry system capable of detecting the presence of errors associated with memory cells identified as storing a first logic state based on activation in response to voltages in a first voltage sequence 420. If the number of detected errors meets (e.g., reaches or exceeds) a threshold, the memory device can determine that the last applied voltage is the termination voltage 430.

[0054] As part of the second phase of the read operation, the memory device may determine the number of memory cells storing a third logic state by applying a second voltage sequence 435 with a second polarity having an incrementing value to a group of memory cells. The memory device may determine a second starting voltage 440 of the second voltage sequence having a second magnitude 460. In some cases, the second magnitude 460 may differ from a first magnitude 455. For each voltage in the second voltage sequence 435 applied to the group of memory cells, the memory device may determine the number of memory cells having a voltage less than a threshold voltage of the applied voltage (e.g., the number of cells activated in response to the application of each voltage in the second voltage sequence 435). In some instances, the memory device may use the determined number of memory cells (e.g., the number of memory cells that have been activated so far in the second voltage sequence 435) to identify the step size of the next voltage in the second voltage sequence 435 (e.g., the magnitude of the next voltage in the first voltage sequence 420). In some cases, such as based on the number of memory cells activated in response to the second voltage sequence 435, the determined number of memory cells falling below a threshold, the number of bit errors meeting a threshold, or a combination thereof, the memory device can determine a termination voltage 445 in the second voltage sequence 435. Based on determining the termination voltage 445, the memory device can determine that each memory cell having a threshold voltage within the threshold voltage distribution 415-b has been read, and thus can determine the total number of memory cells storing the third logic state.

[0055] The memory device can determine the number of memory cells storing the second logic state using the number of memory cells storing the first logic state and the number of memory cells storing the third logic state. For example, the number of memory cells storing the second logic state may correspond to (e.g., equal to) the difference between the total number of memory cells in the memory device (e.g., the total number of memory cells read as part of a read operation) and the number of memory cells storing the first or third logic state.

[0056] In some cases, the voltage threshold of a memory cell (e.g., one or both of the positive and negative voltage thresholds) may drift over time, which can lead to increased latency in read operations (e.g., the time t used to perform the read operation). read For example, because the threshold voltage distribution 405-a may drift to a higher voltage of the first polarity, the first stage of the read operation may include an increased amount of voltage in the first voltage sequence 420 to reach the termination voltage 430. Similarly, because the threshold voltage distribution 415-b may drift to a lower voltage of the second polarity, the second stage of the read operation may include an increased amount of voltage in the second voltage sequence 435 to reach the termination voltage 445.

[0057] To reduce latency associated with read operations, the memory device can use information from the first stage of the read operation (e.g., termination voltage 430) to improve aspects of the second stage of the read operation. For example, the memory device can use the termination voltage 430 in the first voltage sequence 420 to determine a second start voltage 440. For example, the memory device can determine (e.g., calculate) the magnitude of the second start voltage 440 as the difference between the magnitude of the termination voltage 430 and a voltage offset 450. In some cases, the voltage offset 450 can be selected such that the magnitude of the second start voltage 440 is greater than the magnitude of the first start voltage 425. In some instances, the memory device can determine the magnitude of the second start voltage 440 based on the magnitude of the termination voltage 430. For example, different magnitudes of the termination voltage 430 can correspond to (e.g., map to) different magnitudes of the second start voltage 440, such that the memory device can determine the magnitude of the second start voltage 440 as a value corresponding to the magnitude of the termination voltage 430 (e.g., using the magnitude of the termination voltage 430 to read the value of the second start voltage 440 from a register). In some instances, the memory device may select the value of the second start voltage 440 such that it is between the value of the stop voltage 430 and the value of the first start voltage 425.

[0058] Therefore, the second start voltage 440 can be closer to the end of the threshold voltage distribution 415-b (e.g., compared to the end of the first start voltage 425 and the threshold voltage distribution 405-a), which may result in fewer voltages in the second voltage sequence 435 compared to the number of voltages in the first voltage sequence 420. That is, the magnitude difference between the second start voltage 440 and the termination voltage 445 can be smaller than the magnitude difference between the first start voltage 425 and the termination voltage 430. Therefore, fewer voltage steps can be used to reach the termination voltage 445 from the second start voltage 440 compared to reaching the termination voltage 430 from the first start voltage 425. Therefore, the latency of the read operation can be reduced compared to a read operation using the same magnitude for the first start voltage 425 and the second start voltage 440.

[0059] although Figure 4 The example described herein uses the positive polarity of the first voltage sequence 420 and the termination voltage 430 to determine the second starting voltage 440 with negative polarity, but those skilled in the art will understand that other arrangements are possible. For example, the first stage of a read operation may be associated with a voltage sequence with negative polarity, and the memory device may accordingly use the negative polarity termination voltage of the first stage of the read operation to determine the positive polarity starting voltage of the second stage of the read operation.

[0060] Figure 5This describes an example of a system 500 that supports memory cell read operation techniques, as disclosed herein. System 500 can be implemented as described herein (including references). Figures 1-4 The system 500 may be implemented by or by aspects of a memory device or memory array. For example, the system 500 may be implemented by (e.g., included in) a memory device (e.g., memory device 100, a memory device including memory array 200) to support a two-stage read operation technique with reduced latency.

[0061] In some cases, system 500 may include logic 505 configured to determine a digital signal and output it to signal converter 510, which may be an instance of a digital-to-analog converter (DAC). In some cases, the digital signal output by logic 505 may be used as part of one or more stages of a read operation on a set of memory cells of a memory array coupled to logic 505. For example, signal converter 510 may convert the digital signal into a voltage (e.g., an analog value of the voltage) that can be applied to the set of memory cells as a voltage sequence (e.g., a first voltage sequence 420, a second voltage sequence 435).

[0062] System 500 may include a controller 550 coupled to logic 505 to control aspects of the read operation, the controller 550 being as referenced Figure 1 An example of the described local memory controller 150. System 500 may further include a set of registers 520 coupled to logic 505. The set of registers 520 may be an example of a LUT and may store indications of one or more steps of a voltage sequence for read operations.

[0063] In some cases, system 500 may include sensing component 530, which may be as described in reference... Figure 1 An example of the described sensing component 130. Sensing component 130 may be coupled to counter 525, which is coupled to logic 505. Counter 525 may be configured to provide logic 505 with an indication of the number of memory cells storing a particular logic state (e.g., a logic state sensed by sensing component 530). For example, counter 525 may track the number of memory cells determined by sensing component 530 to store a particular logic state and may output an indication to logic 505.

[0064] In some cases, the number of memory cells storing a specific logic state can be used to determine or select the step size of the voltage sequence for a read operation. For example, as part of the first stage of a read operation, logic 505 may determine the current voltage (e.g., the current step, the starting voltage) in a first voltage sequence and store the current voltage in a first register 515. The first register 515 may output the current voltage (e.g., an indication of the current voltage, a digital signal representing the current voltage) to a signal converter 510, and may apply the current voltage to the set of memory cells to determine the number of memory cells having a threshold voltage less than the current voltage (e.g., the number of memory cells activated by the current voltage), and thus, for example, use sensing component 530 and counter 525 to determine the number of memory cells storing the first logic state. In some instances, if a starting voltage is determined in the first voltage sequence, then logic 505 may read the value of the starting voltage from the set of registers 520 and output an indication of the starting voltage to the signal converter 510.

[0065] To determine the next voltage in the first voltage sequence, logic 505 may read a step size from a set of registers 520. In some cases, the step size may depend on the number of activated memory cells. For example, the set of registers 520 may contain a mapping between or associated with the number of activated memory cells (e.g., a range of activated memory cells) and the step size of the voltage sequence. For example, the step size read from the set of registers 520 may be applied to the current voltage by inputting the step size from the set of registers 520 and the current voltage from the first register 515 into the second logic 535.

[0066] The second logic 535 can be configured to add the step size to the current voltage (e.g., to increase the current voltage by the step size) to generate the next voltage (e.g., a subsequent voltage in the first voltage sequence) and output the next voltage (an indication of the next voltage, a digital signal representing the next voltage) to the multiplexer 540. In some cases, the controller 550 can use the multiplexer 540 to select the next voltage (e.g., by sending a selection signal indicating the multiplexer 540 to select and output the input received from the second logic 535 to the multiplexer 540), and logic 505 can store the next voltage in the first register 515 and output an indication of the next voltage to the signal converter 510 to be applied to the set of memory cells.

[0067] In some cases, logic 505 can determine a termination voltage in the first voltage sequence. For example, if the total number of memory cells activated by the first voltage sequence in response to the application of a voltage in the first voltage sequence meets a threshold number of memory cells, then logic 505 can determine that the first voltage sequence has activated each memory cell of the memory device storing the first state, and therefore can determine that the voltage is a termination voltage. Thus, logic 505 can store the termination voltage in the second register 545 and can terminate the first phase of the read operation. For example, the first register 515 can output an indication of the termination voltage to the second register 545, and the second register 545 can store the indication of the termination voltage. In some instances, the first register 515 can be configured to output an indication of the current voltage to the second register 545. That is, at each step of the first voltage sequence, the first register 515 can output an indication of the current voltage to the second register 545, and the second register 545 can be configured to replace the stored voltage (e.g., a previously indicated voltage) with the indicated current voltage. Therefore, after the termination voltage is reached, the first register 515 can output an indication of the current voltage, which may be the termination voltage, and the second register 545 can update the stored voltage to the termination voltage. In some cases, after terminating the first stage of the read operation, logic 505 may issue an indication to the controller 550 to begin the second stage of the read operation (e.g., an indication that the first stage of the read operation is complete).

[0068] Logic 505 can use the termination voltage stored in the second register 545 to determine the starting voltage of the second stage of the read operation. For example, logic 505 can read a voltage offset (e.g., margin) from the set of registers 520 and can apply the voltage offset to the termination voltage. Logic 505 can input the voltage offset from the set of registers 520 and the termination voltage from the second register 545 into the third logic 560. In some cases, the set of registers 520 can store multiple voltage offsets, and the voltage offset read from the set of registers 520 can depend on the parameters of the read operation. For example, the set of registers 520 can contain a mapping between the magnitude of the termination voltage and the corresponding voltage offset, a mapping between the number of memory cells activated by the termination voltage and the corresponding voltage offset, or both, or be associated with them. Alternatively or additionally, the voltage offset can depend on the step size of the first stage of the read operation. For example, the voltage offset can depend on the average step size of the first voltage sequence, the step size used to reach the termination voltage, or a combination thereof. Alternatively, the voltage offset may correspond to (e.g., equal to) the sum of one or more steps used in the first voltage sequence (e.g., the sum of the last two steps used in the first voltage sequence, and other instances).

[0069] Third logic 560 can be configured to subtract a step size (e.g., to reduce the magnitude of the termination voltage to a voltage offset) from the termination voltage to determine (e.g., generate, calculate) the magnitude of the starting voltage in the second voltage sequence. Third logic 560 can output the magnitude of the starting voltage in the second voltage sequence (e.g., an indication of the difference between the termination voltage and the voltage offset) to multiplexer 540. In some cases, in response to receiving an indication to begin a second phase of a read operation, controller 550 can use multiplexer 540 (e.g., by transmitting an indication to determine the starting voltage in the second voltage sequence based on the termination voltage) to select the magnitude of the starting voltage in the second voltage sequence as the difference between the termination voltage and the voltage offset. In response, multiplexer 540 can select to output the input received from third logic 560 to first register 515 for storage and application to the set of memory cells. Additionally, logic 505 can be configured to invert the polarity of the starting voltage in the second voltage sequence relative to the termination voltage. That is, if the first phase of the read operation uses a first polarity (e.g., positive polarity), then logic 505 can use a second polarity (e.g., negative polarity) for the second phase of the read operation.

[0070] Therefore, system 500 can use a starting voltage determined by utilizing the voltage offset and the termination voltage of the first stage of the read operation to perform the second stage of the read operation. This reduces the number of steps in the second stage of the read operation and thus reduces the total read latency of the read operation (e.g., t). read ).

[0071] In some instances, controller 550 may be configured to determine whether to select the starting voltage calculated by third logic 560 for the second stage of the read operation, or to select a different starting voltage for the second stage. For example, controller 550 may determine to use a starting voltage of the same magnitude as the starting voltage of the first stage of the read operation for the second stage.

[0072] In some instances, system 500 may support updating or configuring parameters for read operations. For example, controller 550 may rewrite or update one or more values ​​stored in the set of registers 520, such as mappings of one or more step sizes stored in the set of registers 520, mappings of one or more voltage offsets stored in the set of registers 520, or both. In some cases, controller 550 may update the voltage offset based on the temperature of the memory device containing the set of memory cells (e.g., the temperature of the set of memory cells). For example, a higher temperature of the memory device may be associated with a larger drift in the threshold voltage distribution, while a lower temperature may be associated with a smaller drift in the threshold voltage distribution, and controller 550 may adjust the voltage offset accordingly to compensate for the distribution of the threshold voltage drift. Alternatively or additionally, the set of registers 520 may store different voltage offset values ​​corresponding to different temperature ranges of the memory device, and logic 505 may read from the set of registers 520 the voltage offset corresponding to a temperature range that includes (e.g., spans) the current temperature of the memory device.

[0073] In some instances, system 500 may include an error control component 555, which may be an example of an error correction code (ECC) circuit. The error control component 555 may be configured to determine whether an error exists associated with the logic state of a memory cell determined by sensing component 530. For example, the error control component 555 may determine whether any memory cell is incorrectly determined to store a first logic state in response to the application of a voltage in a first voltage sequence. The error control component 555 may (e.g., via a counter) track the number of errors (e.g., the total number of errors determined across voltages in the first voltage sequence, or the number of errors determined for a specific voltage in the first voltage sequence) and output the number of errors to logic 505. Logic 505 may use the number of errors to determine whether the last applied voltage in the first voltage sequence is a termination voltage. For example, if the number of errors meets (e.g., reaches or exceeds) a threshold number of errors, then logic 505 may determine that the most recently applied voltage is a termination voltage in the first voltage sequence. The error control component 555 can similarly track and output the number of errors associated with the voltages in the second voltage sequence, and the logic 505 can determine the termination voltage in the second voltage sequence based on the number of errors.

[0074] In some instances, error control component 555 may compare the number of memory cells storing a specific logical state with an expected pattern to determine whether an error exists in the data read from the memory cells. For example, during a test phase of operation of system 500, error control component 555 may receive an indication of a logical state stored in memory cells read during a read operation and may compare the indication with a supplied or predetermined expected pattern of the logical state. If the supplied logical state does not match the expected logical state, or if the error control code associated with the supplied logical state and the error correction code associated with the expected pattern of the logical state do not match, then error control component 555 may determine that an error exists in the supplied logical state. In some instances, this error information may be used, for example, to set a step size stored in the set of registers 520, a range of activated memory cells stored in the set of registers 520, or a combination thereof.

[0075] Figure 6 A block diagram 600 illustrates a memory device 620 supporting memory cell read operation technology according to an example disclosed herein. The memory device 620 may be as described in the references... Figures 1-5 Examples of aspects of the described memory device. Memory device 620 or its various components may be examples of means for performing various aspects of the memory cell read operation techniques described herein. For example, memory device 620 may include voltage application component 625, voltage determination component 630, offset determination component 635, voltage value storage component 640, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0076] Voltage application component 625 may be configured or otherwise support components for performing the following actions: as part of a first stage of a read operation on a set of memory cells, applying a first voltage sequence having a first polarity to the set of memory cells, the first voltage sequence being associated with a first starting voltage. Voltage determination component 630 may be configured or otherwise support components for performing the following actions: determining a second starting voltage associated with a second voltage sequence having a second polarity, based at least in part on a termination voltage in the first voltage sequence, the second starting voltage having a magnitude different from that of the first starting voltage. In some instances, voltage application component 625 may be configured or otherwise support components for performing the following actions: as part of a second stage of the read operation, applying a second voltage sequence to the set of memory cells according to the second starting voltage.

[0077] In some instances, to support the determination of the second starting voltage, the offset determination component 635 may be configured or otherwise supported to determine a voltage offset based at least in part on the completion of the first phase of the read operation, wherein the magnitude of the second starting voltage is at least in part based on the voltage offset.

[0078] In some instances, to support the determination of the second starting voltage, the voltage determination component 630 may be configured or otherwise supported to perform the following action: determining the difference between the termination voltage and the voltage offset, wherein the magnitude of the second starting voltage is equal to the difference between the termination voltage and the voltage offset.

[0079] In some instances, to support the determination of the voltage offset, the voltage value storage component 640 may be configured or otherwise supported to read the value of the voltage offset from a register associated with determining the voltage in a voltage sequence associated with the phase of the read operation.

[0080] In some instances, the voltage offset is based at least in part on the step size associated with the first voltage sequence.

[0081] In some instances, the voltage offset is based at least in part on the temperature of the memory device containing the set of memory cells.

[0082] In some instances, the voltage offset is at least partially based on the magnitude of the termination voltage.

[0083] In some instances, the voltage determination component 630 may be configured or otherwise support a component for performing the following actions: as part of the first phase of the read operation, determining the termination voltage based at least in part on the activation of a threshold number of memory cells in response to the first voltage sequence, wherein determining the second start voltage is further based at least in part on applying a voltage offset to the termination voltage.

[0084] In some instances, the number of the first voltage sequences is greater than the number of the second voltage sequences.

[0085] In some instances, the magnitude of the second starting voltage is greater than the magnitude of the first starting voltage.

[0086] In some instances, the first polarity corresponds to a positive voltage and the second polarity corresponds to a negative voltage.

[0087] In some instances, the set of memory cells includes a ternary memory cell configured to store one of three logical states.

[0088] Figure 7 The flowchart illustrates a method 700 supporting memory cell read operation techniques according to examples disclosed herein. Operation of method 700 can be implemented by a memory device or its components described herein. For example, operation of method 700 can be performed by, as referenced herein... Figures 1-6 The described memory device is used to perform this function. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0089] At 705, the method may include, as part of a first stage of a read operation on a set of memory cells, applying a first voltage sequence having a first polarity to the set of memory cells, the first voltage sequence being associated with a first starting voltage. Operation 705 may be performed according to examples disclosed herein. In some examples, aspects of operation 705 may be as described in references... Figure 6 The voltage application component 625 is used to perform the described operation.

[0090] At 710, the method may include determining a second starting voltage associated with a second voltage sequence having a second polarity, based at least in part on the termination voltage in the first voltage sequence, the second starting voltage having a magnitude different from that of the first starting voltage. Operation 710 may be performed according to examples as disclosed herein. In some instances, aspects of operation 710 may be as described in references... Figure 6 The voltage determination component 630 described herein performs this function.

[0091] At 715, the method may include, as part of a second stage of the read operation, applying the second voltage sequence to the set of memory cells according to the second start voltage. Operation 715 may be performed according to examples disclosed herein. In some instances, aspects of operation 715 may be as described in references... Figure 6 The voltage application component 625 is used to perform the described operation.

[0092] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include operations, features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing processor-executable instructions) or any combination thereof for performing aspects of this disclosure:

[0093] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing: as part of a first stage of a read operation on a set of memory cells, applying a first voltage sequence having a first polarity to the set of memory cells, the first voltage sequence being associated with a first start voltage; determining, at least in part, a second start voltage associated with a second voltage sequence having a second polarity, the second start voltage having a magnitude different from that of the first start voltage, based on a termination voltage in the first voltage sequence; and as part of a second stage of the read operation, applying the second voltage sequence to the set of memory cells according to the second start voltage.

[0094] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, wherein determining the second starting voltage comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for performing the following: determining a voltage offset at least in part based on the completion of the first phase of the read operation, wherein the magnitude of the second starting voltage is at least in part based on the voltage offset.

[0095] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to aspect 2, wherein determining the second starting voltage includes an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for performing the following actions: determining the difference between the termination voltage and the voltage offset, wherein the magnitude of the second starting voltage is equal to the difference between the termination voltage and the voltage offset.

[0096] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 2 to 3, wherein determining the voltage offset comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for performing the following action: reading the value of the voltage offset from a register associated with determining a voltage in a voltage sequence associated with a phase of the read operation.

[0097] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 2 to 4, wherein the voltage offset is based at least in part on a step size associated with the first voltage sequence.

[0098] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 2 to 5, wherein the voltage offset is based at least in part on the temperature of the memory device comprising the set of memory cells.

[0099] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 2 to 6, wherein the voltage offset is at least partially based on the magnitude of the termination voltage.

[0100] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for performing the following: as part of the first stage of the read operation, determining the termination voltage based at least in part on the activation of a threshold number of memory cells in response to the first voltage sequence, wherein determining the second start voltage is further based at least in part on applying a voltage offset to the termination voltage.

[0101] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 8, wherein the number of the first voltage sequences is greater than the number of the second voltage sequences.

[0102] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, wherein the magnitude of the second starting voltage is greater than the magnitude of the first starting voltage.

[0103] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 10, wherein the first polarity corresponds to a positive voltage and the second polarity corresponds to a negative voltage.

[0104] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, wherein the set of memory cells includes a ternary memory cell configured to store one of three logical states.

[0105] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods can be combined.

[0106] Describe a device. An overview of aspects of the device as described herein is provided below:

[0107] Aspect 13: An apparatus comprising: a controller; a memory cell array; and logic coupled to the controller, the logic being configured to: as part of a first stage of a read operation on the memory cell array, determine a first starting voltage in a first voltage sequence associated with the first stage of the read operation, the first voltage sequence having a first polarity; as part of the first stage of the read operation, output an indication for applying the first starting voltage to the memory cell array; as part of a second stage of the read operation and at least partially based on a termination voltage in the first voltage sequence, determine a second starting voltage associated with a second voltage sequence having a second polarity, the second starting voltage having a magnitude different from the magnitude of the first starting voltage; and as part of the second stage of the read operation, output an indication for applying the second starting voltage to the memory cell array.

[0108] Aspect 14: The device according to aspect 13, wherein the logic is further configured to: receive an indication from the controller and at least in part based on the completion of the first phase of the read operation to determine the second start voltage based at least in part on the termination voltage.

[0109] Aspect 15: The device according to any one of aspects 13 to 14, wherein the logic comprises: a first register configured to output an indication of a voltage applied to the memory cell array; and a second register coupled to the first register, the second register being configured to store an indication of the termination voltage in the first voltage sequence output by the first register, wherein the determination of the second start voltage is at least in part based on the storage of the indication of the termination voltage.

[0110] Aspect 16: The device according to aspect 15 further includes a set of registers associated with determining a voltage in a voltage sequence associated with a phase of the read operation, wherein the logic is further configured to read a value of a voltage offset from a register in the set of registers, wherein the determination of the second starting voltage is based at least in part on the voltage offset.

[0111] Aspect 17: The apparatus according to any one of aspects 15 to 16, wherein the logic further comprises: second logic configured to determine the difference between the termination voltage and the voltage offset stored in the second register; and a multiplexer configured to: receive from the controller an indication for determining the second start voltage based at least in part on the termination voltage; receive from the second logic an indication of the difference between the termination voltage and the voltage offset; and output the indication of the difference between the termination voltage and the voltage offset to the first register based at least in part on the indication for determining the second start voltage based at least in part on the termination voltage.

[0112] Aspect 18: The device according to aspect 17, wherein the logic further comprises third logic configured to: determine the next voltage in the sequence based at least in part on an indication of a previous voltage and a step size in the voltage sequence associated with a phase of the read operation; and output the indication of the next voltage to the multiplexer, wherein the multiplexer is configured to select, at least in part on the indication for determining the second start voltage based at least in part on the stop voltage, the indication of the difference between the stop voltage and the voltage offset to output to the first register.

[0113] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, which may have various bit widths.

[0114] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) with each other if any conductive path exists between them that can readily support the flow of signals between them. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) may be open or closed depending on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between the components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0115] The term "coupling" refers to a condition that moves from an open-circuit relationship between components (where signals cannot currently travel between components via conductive paths) to a closed-circuit relationship between components (where signals can travel between components via conductive paths). When a component (e.g., a controller) couples other components together, the component initially allows signals to flow between the other components via conductive paths that were previously not permitted.

[0116] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, when a switch positioned between components is open, the two components separated by the switch are isolated from each other. When a controller isolates two components, it prevents changes in the conductive path that previously allowed signal flow between the components.

[0117] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or any other doping method.

[0118] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped with an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the transistor threshold voltage is applied to the transistor gate, the transistor may be “turned on” or “activated.” When a voltage less than the transistor threshold voltage is applied to the transistor gate, the transistor may be “turned off” or “deactivated.”

[0119] The descriptions set forth herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to other instances." The detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described instances.

[0120] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a dash after the reference label and a second label to differentiate similar components. When only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0121] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored or transmitted as one or more instructions or code on or through a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0122] For example, the various illustrative blocks and modules described in this disclosure may be implemented or performed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0123] As used herein (included in the claims), the word "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0124] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave), then the definition of media includes coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave). As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0125] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating a memory device, comprising: As part of the first stage of a read operation on a set of memory cells, a first voltage sequence having a first polarity is applied to the set of memory cells, the first voltage sequence being associated with a first starting voltage; A second starting voltage associated with a second voltage sequence having a second polarity is determined, at least in part, based on the termination voltage in the first voltage sequence, the second starting voltage having a magnitude different from that of the first starting voltage; and As part of the second phase of the read operation, the second voltage sequence is applied to the set of memory cells according to the second start voltage.

2. The method of claim 1, wherein determining the second starting voltage comprises: The voltage offset is determined at least in part based on the completion of the first phase of the read operation, wherein the magnitude of the second starting voltage is at least in part based on the voltage offset.

3. The method of claim 2, wherein determining the second starting voltage comprises: Determine the difference between the termination voltage and the voltage offset, wherein the magnitude of the second starting voltage is equal to the difference between the termination voltage and the voltage offset.

4. The method of claim 2, wherein determining the voltage offset comprises: The voltage offset value is read from a register associated with the voltage in a voltage sequence that is determined in relation to the phase of the read operation.

5. The method of claim 2, wherein the voltage offset is at least partially based on a step size associated with the first voltage sequence.

6. The method of claim 2, wherein the voltage offset is at least partially based on the temperature of the memory device comprising the set of memory cells.

7. The method of claim 2, wherein the voltage offset is at least partially based on the magnitude of the termination voltage.

8. The method of claim 1, further comprising: As part of the first phase of the read operation, the termination voltage is determined at least in part based on the activation of a threshold number of memory cells in response to the first voltage sequence, wherein the determination of the second start voltage is further at least in part based on applying a voltage offset to the termination voltage.

9. The method of claim 1, wherein the number of the first voltage sequences is greater than the number of the second voltage sequences.

10. The method of claim 1, wherein the magnitude of the second starting voltage is greater than the magnitude of the first starting voltage.

11. The method of claim 1, wherein the first polarity corresponds to a positive voltage and the second polarity corresponds to a negative voltage.

12. The method of claim 1, wherein the set of memory units comprises a ternary memory unit configured to store one of three logical states.

13. A memory device comprising: Controller; Memory cell array; and Logic, coupled to the controller, is configured to: As part of a first phase of a read operation on the memory cell array, a first starting voltage is determined in a first voltage sequence associated with the first phase of the read operation, the first voltage sequence having a first polarity; As part of the first phase of the read operation, an indication for the first starting voltage applied to the memory cell array is output. As part of the second phase of the read operation and at least in part based on the termination voltage in the first voltage sequence, a second starting voltage associated with a second voltage sequence having a second polarity is determined, the second starting voltage having a magnitude different from that of the first starting voltage; and As part of the second phase of the read operation, an indication for the second starting voltage applied to the memory cell array is output.

14. The memory device of claim 13, wherein the logic is further configured to: The controller receives an indication to determine the second start voltage based at least in part on the termination voltage, based on the completion of the first phase of the read operation.

15. The memory device of claim 13, wherein the logic comprises: A first register is configured to output an indication of the voltage applied to the memory cell array; and A second register, coupled to the first register, is configured to store an indication of the termination voltage in the first voltage sequence output by the first register, wherein the determination of the second start voltage is based at least in part on the storage of the indication of the termination voltage.

16. The memory device of claim 15, further comprising a set of registers associated with determining a voltage in a voltage sequence associated with a phase of the read operation, wherein the logic is further configured to: The voltage offset value is read from a register in the set of registers, wherein the determination of the second starting voltage is based at least in part on the voltage offset.

17. The memory device of claim 15, wherein the logic further comprises: The second logic is configured to determine the difference between the termination voltage and the voltage offset stored in the second register; and Multiplexer, configured to: Receive from the controller an indication for determining the second start voltage based at least in part on the termination voltage; Receive an indication of the difference between the termination voltage and the voltage offset from the second logic; and The indication of the difference between the termination voltage and the voltage offset is output to the first register, based at least in part on the indication used to determine the second start voltage based at least in part on the termination voltage.

18. The memory device of claim 17, wherein the logic further comprises third logic, the third logic being configured to: The next voltage in the sequence is determined at least in part based on an indication of the previous voltage and step size in the voltage sequence associated with the stage of the read operation; and The indication of the next voltage is output to the multiplexer, wherein the multiplexer is configured to select, at least in part, the indication of the difference between the termination voltage and the voltage offset based on the indication used to determine the second start voltage at least in part based on the termination voltage, and output the indication to the first register.

19. A memory device comprising: A set of memory units; and A controller configured to cause the memory device to perform the following actions: As part of the first stage of a read operation on the set of memory cells, a first voltage sequence having a first polarity is applied to the set of memory cells, the first voltage sequence being associated with a first starting voltage; A second starting voltage associated with a second voltage sequence having a second polarity is determined, at least in part, based on the termination voltage in the first voltage sequence, the second starting voltage having a magnitude different from that of the first starting voltage; and As part of the second phase of the read operation, the second voltage sequence is applied to the set of memory cells according to the second start voltage.

20. The memory device of claim 19, wherein, in order to determine the second start voltage, the controller is configured to cause the memory device to perform the following actions: The voltage offset is determined at least in part based on the completion of the first phase of the read operation, wherein the magnitude of the second starting voltage is at least in part based on the voltage offset.

21. The memory device of claim 20, wherein, in order to determine the second start voltage, the controller is configured to cause the memory device to perform the following actions: Determine the difference between the termination voltage and the voltage offset, wherein the magnitude of the second starting voltage is equal to the difference between the termination voltage and the voltage offset.

22. The memory device of claim 20, wherein, in order to determine the voltage offset, the controller is configured to cause the memory device to perform the following actions: The voltage offset value is read from a register associated with the voltage in a voltage sequence that is determined in relation to the phase of the read operation.

23. The memory device of claim 20, wherein the voltage offset is at least partially based on a step size associated with the first voltage sequence.

24. The memory device of claim 20, wherein the voltage offset is at least partially based on the temperature of the memory device comprising the set of memory cells.

25. The memory device of claim 20, wherein the voltage offset is at least partially based on the magnitude of the termination voltage.

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