Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises a substrate, a first metal layer located on the substrate and comprising a common signal line, a second metal layer located on a side of the first metal layer away from the substrate and comprising a data line, an electrode layer located on a side of the second metal layer away from the first metal layer and comprising a plurality of pixel electrodes and at least one connecting electrode, the pixel electrode comprising a trunk electrode, and a shielding layer comprising a plurality of transparent shielding electrodes, the transparent shielding electrode being located between the data line and the pixel electrode, the transparent shielding electrode being electrically connected to the common signal line through a plurality of first vias, the connecting electrode being electrically connected to the transparent shielding electrode through a second via, the first via and the second via being spaced apart, the first via being located in an area of the pixel electrode, and the second via being located in an area of the connecting electrode. The array substrate and the display panel can avoid the risk of disconnection.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] The existing TSS (Transparent Storage Capacity and Shielding Layer) pixel structure adds a transparent TSS electrode layer to replace the DBS (data line BM less). The TSS transparent electrode layer overlaps with the data line, which can shield the electric field of the data line, and a large transparent storage capacitance is formed between the TSS transparent electrode layer and the pixel electrode layer, which can significantly improve transmittance and storage capacitance. However, in the TSS pixel structure, because the TSS transparent electrode layer is connected to the metal layer where the pixel electrode is located through a series of interconnected deep and shallow holes, and connected to the common signal line through shallow holes, the interconnected deep and shallow holes may cause the risk of undercut during the line splicing process. Summary of the Invention

[0003] In view of this, this application provides an array substrate and display panel that can avoid the risk of wire breakage.

[0004] To solve the above problems, the technical solution provided in this application is as follows:

[0005] This application provides an array substrate, comprising:

[0006] Base;

[0007] A first metal layer is located on the substrate and includes a common signal line;

[0008] A second metal layer is located on the side of the first metal layer opposite to the substrate and includes data lines;

[0009] An electrode layer, located on the side of the second metal layer opposite to the first metal layer, includes a plurality of pixel electrodes spaced apart and at least one connection electrode, wherein the pixel electrodes include a main electrode; and

[0010] A shielding layer includes multiple transparent shielding electrodes; the transparent shielding electrodes are located between the data line and the pixel electrode.

[0011] The transparent shielding electrode is electrically connected to the common signal line through multiple first vias, and the connecting electrode is electrically connected to the transparent shielding electrode through a second via. The first vias and the second vias are spaced apart, with the first vias located in the area where the pixel electrode is located and the second vias located in the area where the connecting electrode is located.

[0012] In an optional embodiment of this application, the pixel electrode includes a main electrode, and the projection of the first via onto the pixel electrode falls on the main electrode of the pixel electrode.

[0013] In an optional embodiment of this application, the main electrode includes a first main electrode and a second main electrode that crosses and connects to the first main electrode. The first main electrode is parallel to the data line, and the second main electrode is perpendicular to the data line.

[0014] The projection of the first via onto the pixel electrode falls on the first main electrode, the second main electrode, or the junction of the first and second main electrodes.

[0015] In an optional embodiment of this application, the array substrate includes a plurality of pixel electrode regions and at least one driving circuit region. The pixel electrodes are located within the pixel electrode regions, and the connection electrodes are located within the driving circuit region. The connection electrodes are located between two adjacent pixel electrodes within two adjacent pixel electrode regions. Each pixel electrode region has a first via, and the driving circuit region has a second via.

[0016] In an optional embodiment of this application, the common signal line includes a first common signal line and a second common signal line, the first common signal line and the second common signal line being perpendicularly connected; one of the first common signal line and the second common signal line is parallel to the data line; and

[0017] The transparent shielding electrode is electrically connected to one of the first common signal line and the second common signal line through the first via, and the second via is located above the other of the first common signal line and the second common signal line.

[0018] In an optional embodiment of this application, the first metal layer further includes a scan line, and the second via is located above one of the first common signal lines and the second common signal line, which is parallel to the scan line.

[0019] In an optional embodiment of this application, the transparent shielding electrode is sheet-shaped and includes a first sub-transparent shielding electrode. The first sub-transparent shielding electrode covers the data line and is electrically connected to the first common signal line through the first via. The orthogonal projection of the first sub-transparent shielding electrode on the substrate covers the orthogonal projection of the pixel electrode on the substrate.

[0020] In an optional embodiment of this application, the transparent shielding electrode further includes a second sub-transparent shielding electrode extending from one side of the first sub-transparent shielding electrode;

[0021] The second sub-transparent shielding electrode covers a portion of the second common signal line and one of the second common signal lines parallel to the scan line; and

[0022] The connecting electrode is electrically connected to the second sub-transparent shielding electrode through the second via.

[0023] In an optional embodiment of this application, the transparent shielding electrode includes a plurality of third sub-transparent shielding electrodes, each of the third sub-transparent shielding electrodes covering one of the data lines, and the orthographic projection of a pixel electrode on the substrate at least partially falls between the orthographic projections of two adjacent third sub-transparent shielding electrodes on the substrate.

[0024] In an optional embodiment of this application, the transparent shielding electrode further includes a fourth sub-transparent shielding electrode and a fifth sub-transparent shielding electrode, wherein the fourth sub-transparent shielding electrode and the fifth sub-transparent shielding electrode are connected to at least one of the third sub-transparent shielding electrodes;

[0025] The fourth sub-transparent shielding electrode is electrically connected to the common signal line through the first via; and

[0026] The connecting electrode is electrically connected to the fifth sub-transparent shielding electrode through the second via.

[0027] In an optional embodiment of this application, the array substrate includes at least one pixel, the pixel includes a plurality of sub-pixels, and the first via and the second via are located in two different sub-pixels.

[0028] In an optional embodiment of this application, the array substrate further includes a plurality of color resist blocks formed between the second metal layer and the shielding layer, and a first via penetrates one of the color resist blocks. The color resist block is at least one of a blue color resist block, a red color resist block, and a green color resist block, and the first via penetrates the blue color resist block.

[0029] In an optional embodiment of this application, the pixel electrode includes a cutout portion, and the orthographic projection of the first via on the pixel electrode at least partially overlaps with the cutout portion.

[0030] This application also provides a display panel, including a color filter substrate and a liquid crystal, wherein the display panel further includes an array substrate as described above, and the liquid crystal is located between the color filter substrate and the array substrate.

[0031] The array substrate and display panel provided in this application improve the connection between the first and second vias by spacing them apart, such that the first via is located within the region where the pixel electrode is located, and the second via is located within the region where the connecting electrode is located. In this way, the first and second vias are not connected, eliminating the undercut structure. During the wiring process, the array substrate and display panel provided in this application can avoid the risk of wire breakage. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a cross-sectional view of a display panel provided in the first embodiment of this application.

[0034] Figure 2 for Figure 1 The diagram shows a schematic of the array substrate of the display panel.

[0035] Figure 3 for Figure 2 The diagram shows an array substrate located within a display area and an adjacent driving circuit area.

[0036] Figure 4 For along Figure 3 The image shows a cross-sectional view of the array substrate cut through the first via.

[0037] Figure 5 For along Figure 3 A cross-sectional view of the array substrate cut by the second via shown.

[0038] Figure 6 for Figure 3 The cross-sectional view of the first metal layer shown.

[0039] Figure 7 for Figure 3 The cross-sectional view of the second metal layer shown.

[0040] Figure 8 for Figure 3 The cross-sectional view of the electrode layer shown.

[0041] Figure 9 for Figure 3 The diagram shows a cross-sectional view of the shielding layer.

[0042] Figure 10 This is a schematic diagram of an array substrate provided for another embodiment of this application.

[0043] Figure 11 This is a schematic diagram of an array substrate provided in the second embodiment of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0045] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0046] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0047] The array substrate and display panel provided in this application will be described in detail below with reference to specific embodiments and accompanying drawings.

[0048] Please see Figure 1 The first embodiment of this application provides a display panel 1000, which includes an array substrate 100, a color filter substrate 200 and a liquid crystal 300, wherein the liquid crystal 300 is located between the color filter substrate 200 and the array substrate 100.

[0049] Please see Figure 2 and Figure 3 The array substrate 100 includes at least one pixel electrode region 101 and at least one driving circuit region 102, wherein the driving circuit region 102 is located on one side of the pixel electrode region 101. In this embodiment, the number of pixel electrode regions 101 is at least two, and one driving circuit region 102 is located between two adjacent pixel electrode regions 101.

[0050] Please see Figure 3 The array substrate 100 includes multiple sub-pixels, such as red sub-pixels, green sub-pixels, blue sub-pixels, etc. Each sub-pixel includes a pixel electrode.

[0051] Please see Figures 3 to 9 The array substrate 100 includes a substrate 10, a first metal layer 20, a second metal layer 30, an electrode layer 50, and a shielding layer 40. The first metal layer 20 is located on the substrate 10 and includes a common signal line 21. The second metal layer 30 is located on the side of the first metal layer 20 facing away from the substrate 10 and includes a data line 31. The electrode layer 50 is located on the side of the second metal layer 30 facing away from the first metal layer 20 and includes a plurality of pixel electrodes 51 spaced apart and at least one connection electrode 52. The shielding layer 40 includes a plurality of transparent shielding electrodes 41 located between the second metal layer 30 and the electrode layer 50; specifically, the transparent shielding electrodes 41 are located between the data line 31 and the pixel electrode 51. The transparent shielding electrodes 41 are electrically connected to the common signal line 21 through a plurality of first vias 71, and the connection electrodes 52 are electrically connected to the transparent shielding electrodes 41 through second vias 72. The first via 71 and the second via 72 are spaced apart. The first via 71 is located in the area where the pixel electrode 51 is located, and the second via 72 is located in the area where the connection electrode 52 is located.

[0052] Specifically, the first via 71 and the second via 72 are spaced apart, with the first via 71 located within the region of the pixel electrode 51 and the second via 72 located within the region of the connecting electrode 52. Thus, the first via 71 and the second via 72 are not connected, preventing undercut structures. During the wiring process, the array substrate 100 and the display panel 1000 provided in this application can avoid the risk of wire breakage.

[0053] Furthermore, the first via 71 and the second via 72 are separately arranged. Compared with the first via and the second via being connected, the array substrate 100 provided in this application can not only adjust the density of the first via 71 and the second via 72 according to the distance between them as needed, but also increase the aperture ratio of the array substrate 100 provided in this application while keeping the hole size consistent, thus improving the display effect of the display panel 1000 provided in this application.

[0054] In addition, one of the first via 71 and the second via 72 is located in the pixel electrode region 101 and the other is located in the driving circuit region 102. Compared with the first via 71 and the second via 72 being located in the driving circuit region 102, the arrangement of the first via 71 and the second via 72 in this case can have more positional options, and the density of the first via 71 and the second via 72 can also be adjusted as needed.

[0055] In an optional embodiment of the application, the pixel electrode 51 is located within the pixel electrode region 101, and the connection electrode 52 is located within the driving circuit region 102; the connection electrode 52 is located between two adjacent pixel electrodes 51 within two adjacent pixel electrode regions 101, each pixel electrode region 101 has a first via 71, and the driving circuit region 102 has a second via 72.

[0056] Please see Figure 3 , Figure 4 and Figure 6 In this application, the common signal line 21 includes a first common signal line 211 and a second common signal line 212. The first common signal line 211 and the second common signal line 212 are perpendicularly connected, and one of the first common signal line 211 and the second common signal line 212 is parallel to the data line 31. The transparent shielding electrode 41 is electrically connected to one of the first common signal line 211 and the second common signal line 212 through the first via 71, and the second via 72 is located above the other of the first common signal line 211 and the second common signal line 212.

[0057] In this embodiment, the first common signal line 211 is parallel to the data line 31, the transparent shielding electrode 41 is electrically connected to the first common signal line 211 through the first via 71, and the second via 72 is located above the second common signal line 212.

[0058] Please see Figure 3 The first metal layer 20 further includes a scan line 22, the extension direction of which is perpendicular to the extension direction of the data line 31. The second via 72 is located above one of the first common signal lines 211 and 212, which is parallel to the scan line 22. In this embodiment, the second common signal line 212 is parallel to the scan line 22, and the second via 72 is located above the second common signal line 212.

[0059] The area between two adjacent scan lines 22 and two adjacent data lines 31 is a sub-pixel.

[0060] Please see Figure 3 , Figure 6 and Figure 7 The first metal layer 20 further includes a gate 23 disposed on the same layer as the scan line 22. The second metal layer 30 further includes a source 33 and a drain 32 disposed at intervals and on the same layer as the data line 31. The source 33 is electrically connected to the data line 31, and the source 33 and the drain 32 are respectively positioned opposite to the gate 23. The array substrate 100 further includes an active layer (not shown) located on one side of the gate 23. The array substrate 100 also includes a plurality of transistors, each transistor including a gate 23, an active layer, and a source 33 and a drain 32 disposed opposite to the gate 23 and the active layer. The pixel electrode 51 is electrically connected to the drain 32. The data signal enters the source 33, the drain 32, and the pixel electrode 51 sequentially from the data line 31, and the common signal enters the connection electrode 52 and the transparent shielding electrode 41 sequentially from the common signal line 21.

[0061] Each pixel electrode region 101 includes a plurality of pixel electrodes 51 and a connection electrode 52.

[0062] Please refer to it again. Figure 3 and Figure 8 Each pixel electrode 51 includes a main electrode 511 and a plurality of branch electrodes 512. One end of each branch electrode 512 is connected to the main electrode 511, and the other end extends obliquely away from the main electrode 511. Specifically, in this embodiment, the pixel electrode 51 has 4 domains. The main electrode 511 includes a first main stem 5111 and a second main stem 5112 that is cross-connected to the first main stem 5111. One end of each of the plurality of branch electrodes 512 is connected to the first main stem 5111 and the second main stem 5112, and the other end extends obliquely away from either the first main stem 5111 or the second main stem 5112. The first main stem 5111 and the second main stem 5112 are arranged in a cross shape. In other embodiments, the number of domains of the pixel electrode 51 is not limited to 4 and can be other numbers. The shape of the pixel electrode 51 is also not limited to the above structure.

[0063] The first main stem 5111 is parallel to the data line 31, and the second main stem 5112 is perpendicular to the data line 31.

[0064] The projection of the first via 71 onto the pixel electrode 51 falls on the main electrode 511 of the pixel electrode 51. That is, the first via 71 and the main electrode 511 of the pixel electrode 51 are positioned opposite each other. Thus, the presence of the first via 71 will not affect the deflection of the liquid crystal 300 which is positioned opposite the branch electrode 512 of the pixel electrode 51, thereby not affecting the display effect of the display panel 1000.

[0065] The projection of the first via 71 onto the pixel electrode 51 falls on the first main stem 5111, or on the second main stem 5112, or at the connection between the first main stem 5111 and the second main stem 5112.

[0066] In this embodiment, please refer to Figure 3 The projection of the first via 71 onto the pixel electrode 51 falls at the connection between the first main stem 5111 and the second main stem 5112.

[0067] Please see Figure 4 Each pixel electrode 51 further includes a cutout portion 513, and the orthographic projection of the first via 71 on the pixel electrode 51 at least partially overlaps with the cutout portion 513.

[0068] Please see Figure 3 , Figure 5 and Figure 8 The connecting electrode 52 includes a first connecting portion 521 and a second connecting portion 522 perpendicularly connected to the first connecting portion 521. The extending direction of the first connecting portion 521 is the same as the extending direction of the scan line 22, and the extending direction of the second connecting portion 522 is the same as the extending direction of the data line 31. The second connecting portion 522 is electrically connected to the transparent shielding electrode 41 through the second via 72.

[0069] Both the pixel electrode 51 and the connecting electrode 52 are transparent, and the material of the pixel electrode 51 and the connecting electrode 52 is indium tin oxide (ITO). Of course, the material of the pixel electrode 51 and the connecting electrode 52 is not limited to ITO, and can also be other transparent electrode materials.

[0070] Please see Figures 3 to 5 and Figure 9The transparent shielding electrode 41 is sheet-shaped and includes a first sub-transparent shielding electrode 411 and a second sub-transparent shielding electrode 412 extending from one side of the first sub-transparent shielding electrode 411. The first sub-transparent shielding electrode 411 covers the data line 31 and is electrically connected to the first common signal line 211 through the first via 71. The orthographic projection of the pixel electrode 51 on the substrate 10 falls on the orthographic projection of the first sub-transparent shielding electrode 411 on the substrate 10. The orthographic projection of the first sub-transparent shielding electrode 411 on the substrate 10 covers the orthographic projection of the pixel electrode 51 on the substrate 10. The second sub-transparent shielding electrode 412 covers a portion of the second common signal line 212, and the connection electrode 52 is electrically connected to the second sub-transparent shielding electrode 412 through the second via 72.

[0071] Specifically, the second connection portion 522 of the connecting electrode 52 is electrically connected to the second sub-transparent shielding electrode 412 through the second through hole 72.

[0072] Please see Figure 4 The array substrate 100 further includes a plurality of color resist blocks 60 formed between the second metal layer 30 and the shielding layer 40, and a first via 71 penetrates one of the color resist blocks 60.

[0073] In an optional embodiment of this application, the color resist block 60 is at least one of a blue color resist block, a red color resist block, and a green color resist block, and the first via 71 penetrates the blue color resist block. Because the blue color resist block has low light transmittance, allowing the first via 71 to penetrate the blue color resist block can increase the light transmittance of the blue color resist block, thereby maximizing the aperture ratio.

[0074] Of course, the first via 71 can also pass through color resist blocks of other colors, such as the red color resist block or the green color resist block, which can be set according to the actual situation.

[0075] Please see Figure 4 and Figure 5 In an optional embodiment of this application, the array substrate 100 further includes a first insulating layer 61, a planarization layer 62, and a second insulating layer 63. The first insulating layer 61 covers the first metal layer 20, the planarization layer 62 covers the second metal layer 30, the color resist block 60 is located on the planarization layer 62, the second insulating layer 63 is located on the shielding layer 40, and the electrode layer 50 is located on the second insulating layer 63. The first via 71 penetrates the color resist block 60, the planarization layer 62, and the first insulating layer 61, and the second via 72 penetrates the second insulating layer 63.

[0076] Please see Figure 3 In an optional embodiment of this application, the first via 71 and the second via 72 are located within the same sub-pixel. For example, the first via 71 and the second via 72 are located within one of the blue sub-pixel, red sub-pixel, green sub-pixel, etc.

[0077] Please see Figure 10 In an optional embodiment of this application, the first via 71 and the second via 72 are located in two different sub-pixels. Specifically, the first via 71 and the second via 72 can be located in two adjacent sub-pixels, or they can be located in two non-adjacent sub-pixels. In particular, the density of the first via 71 and the second via 72 can be set according to the actual needs.

[0078] The color filter substrate 200 includes a second substrate (not shown), a patterned black matrix (not shown) formed on the second substrate, and a common electrode formed on the second substrate and covering the black matrix, wherein the common electrode faces the pixel electrode 51.

[0079] Please see Figure 11 and Figure 4 The second embodiment of this application also provides an array substrate 400. The structure of the array substrate 400 is different from that of the array substrate 100 in that: the transparent shielding electrode 81 of the array substrate 400 includes a plurality of third sub-transparent shielding electrodes 811, each of the third sub-transparent shielding electrodes 811 covering one of the data lines 31, and the orthographic projection of a pixel electrode 51 on the substrate 10 at least partially falls between the orthographic projections of two adjacent third sub-transparent shielding electrodes 811 on the substrate 10. In this embodiment, each third sub-transparent shielding electrode 811 also covers a portion of the pixel electrode 51. In other embodiments, the orthographic projection of a pixel electrode 51 on the substrate 10 falls entirely between the orthographic projections of two adjacent third sub-transparent shielding electrodes 811 on the substrate 10.

[0080] The transparent shielding electrode 81 further includes a fourth sub-transparent shielding electrode 812 and a fifth sub-transparent shielding electrode 813. The fourth sub-transparent shielding electrode 812 and the fifth sub-transparent shielding electrode 813 are connected to at least one of the third sub-transparent shielding electrodes 811. The fourth sub-transparent shielding electrode 812 is electrically connected to the first common signal line 211 through the first via 71. The connecting electrode 52 is electrically connected to the fifth sub-transparent shielding electrode 813 through the second via 72.

[0081] The array substrate provided in this application partially hollows out the transparent shielding electrode 81, which is located opposite to other parts of the data line 31, so that the transparent shielding electrode 81 covers the data line 31 or also covers a small part of the pixel electrode 51, which can reduce the load on the display panel 1000 and improve the charging rate.

[0082] The array substrate and display panel provided in this application improve the connection between the first and second vias by setting them apart, with the first via located in the area where the pixel electrode is located and the second via located in the area where the connecting electrode is located. In this way, the first and second vias are not connected, eliminating the undercut structure. During the wiring process, the array substrate and display panel provided in this application can avoid the risk of wire breakage.

[0083] In addition, the first via and the second via are set separately. Compared with the first via and the second via being connected, the array substrate provided by this application can not only adjust the density of the first via and the second via according to the distance between them as needed, but also increase the aperture ratio of the array substrate provided by this application while keeping the size of the holes consistent, thus improving the display effect of the display panel provided by this application.

[0084] In addition, one of the first via and one of the second vias is located in the pixel electrode area and the other is located in the driving circuit area. Compared with the first via and one of the second vias being located in the driving circuit area, the arrangement of the first via and one of the second vias in this case can have more positional options, and the density of the first via and one of the second vias can also be adjusted as needed.

[0085] In addition, since the projection of the first via onto the pixel electrode falls on the main electrode of the pixel electrode, that is, the first via is positioned opposite to the main electrode of the pixel electrode, the presence of the first via will not affect the deflection of the liquid crystal opposite to the branch electrode of the pixel electrode, thus not affecting the display effect of the display panel.

[0086] In addition, the array substrate provided in this application partially hollows out the transparent shielding electrode that is located opposite to other parts of the data line, so that the transparent shielding electrode covers the data line or also covers a small part of the pixel electrode, which can reduce the load on the display panel and improve the charging rate.

[0087] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. An array substrate, characterized in that, include: Base; A first metal layer is located on the substrate and includes a common signal line; A second metal layer is located on the side of the first metal layer opposite to the substrate and includes data lines; An electrode layer, located on the side of the second metal layer opposite to the first metal layer, includes a plurality of pixel electrodes spaced apart and at least one connection electrode, wherein the pixel electrodes include a main electrode; and A shielding layer includes multiple transparent shielding electrodes; the transparent shielding electrodes are located between the data line and the pixel electrode. The transparent shielding electrode is electrically connected to the common signal line through a first via, and the connecting electrode is electrically connected to the transparent shielding electrode through a second via. The first via and the second via are spaced apart. The first via is located in the area where the pixel electrode is located, and the second via is located in the area where the connecting electrode is located. The transparent shielding electrode is located between the common signal line and the connecting electrode in the thickness direction of the array substrate.

2. The array substrate as described in claim 1, characterized in that, The pixel electrode includes a main electrode, and the projection of the first via onto the pixel electrode falls on the main electrode of the pixel electrode.

3. The array substrate as described in claim 2, characterized in that, The main electrode includes a first main electrode and a second main electrode that is cross-connected to the first main electrode. The first main electrode is parallel to the data line, and the second main electrode is perpendicular to the data line. and The projection of the first via onto the pixel electrode falls on the first main electrode, the second main electrode, or the junction of the first and second main electrodes.

4. The array substrate as described in claim 1, characterized in that, The array substrate includes a plurality of pixel electrode regions and at least one driving circuit region. The pixel electrodes are located within the pixel electrode regions, and the connection electrodes are located within the driving circuit region. The connection electrodes are located between two adjacent pixel electrodes within two adjacent pixel electrode regions. Each pixel electrode region has a first via, and the driving circuit region has a second via.

5. The array substrate as described in claim 1, characterized in that, The common signal line includes a first common signal line and a second common signal line, wherein the first common signal line and the second common signal line are perpendicularly connected; the first common signal line is parallel to the data line; and The transparent shielding electrode is electrically connected to the first common signal line through the first via, and the second via is located above the second common signal line.

6. The array substrate as described in claim 5, characterized in that, The first metal layer also includes scan lines, and the second common signal line is parallel to the scan lines.

7. The array substrate as described in claim 6, characterized in that, The transparent shielding electrode is sheet-shaped and includes a first sub-transparent shielding electrode. The first sub-transparent shielding electrode covers the data line and is electrically connected to the first common signal line through the first via. The orthographic projection of the first sub-transparent shielding electrode on the substrate covers the orthographic projection of the pixel electrode on the substrate.

8. The array substrate as claimed in claim 7, characterized in that, The transparent shielding electrode also includes a second sub-transparent shielding electrode extending from one side of the first sub-transparent shielding electrode; The second sub-transparent shielding electrode covers a portion of the second common signal line; and The connecting electrode is electrically connected to the second sub-transparent shielding electrode through the second via.

9. The array substrate as described in claim 6, characterized in that, The transparent shielding electrode includes a plurality of third sub-transparent shielding electrodes, each of the third sub-transparent shielding electrodes covering one of the data lines, and the orthographic projection of a pixel electrode on the substrate at least partially falls between the orthographic projections of two adjacent third sub-transparent shielding electrodes on the substrate.

10. The array substrate as claimed in claim 9, characterized in that, The transparent shielding electrode further includes a fourth sub-transparent shielding electrode and a fifth sub-transparent shielding electrode, wherein the fourth sub-transparent shielding electrode and the fifth sub-transparent shielding electrode are connected to at least one of the third sub-transparent shielding electrodes; The fourth sub-transparent shielding electrode is electrically connected to the first common signal line through the first via; and The connecting electrode is electrically connected to the fifth sub-transparent shielding electrode through the second via.

11. The array substrate according to any one of claims 1-6, characterized in that, The array substrate includes at least one pixel, and the pixel includes multiple sub-pixels, wherein the first via and the second via are located in two different sub-pixels.

12. The array substrate according to any one of claims 1-6, characterized in that, The array substrate further includes a plurality of color resist blocks formed between the second metal layer and the shielding layer, and a first via penetrates one of the color resist blocks; the color resist block is at least one of a blue color resist block, a red color resist block and a green color resist block, and the first via penetrates the blue color resist block.

13. The array substrate according to any one of claims 1-6, characterized in that, The pixel electrode includes a cutout portion, and the orthographic projection of the first via on the pixel electrode at least partially overlaps with the cutout portion.

14. A display panel, comprising a color filter substrate and a liquid crystal, characterized in that, The display panel further includes an array substrate as described in any one of claims 1-13, wherein the liquid crystal is located between the color filter substrate and the array substrate.

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