A data power-on / off processing method, system, device and computer storage medium

Abstract

The application discloses a data power-on and power-off processing method, system, device and computer storage medium. When power-off, target data not written in TLC and a first LBA address of the target data in the TLC are acquired; the target data and the first LBA address are stored in SLC; a second LBA address and a second PBA address of the target data stored in the SLC are acquired; a mapping relationship between the second LBA address and the first LBA address and the second PBA address is established; after power-on, the target data and the first LBA address are read from the SLC, the target data is sorted according to the first LBA address, and a target sorting result is obtained; the target sorting result is classified into a first sorting result meeting a minimum data write amount of the TLC and a second sorting result not meeting the minimum data write amount of the TLC, and the target data is written into the TLC based on the first sorting result and the second sorting result. The data storage performance of the SSD during power-on and power-off is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more specifically, to a data power-on / off processing method, system, device, and computer storage medium. Background Technology

[0002] Currently, in the application of SSDs (Solid State Disks) for data storage, data security and integrity are extremely important. Data loss or errors can cause incalculable losses to customers. Since power outages or disk insertions / removals can occur at any time during host data writing, ensuring data security in such situations is a critical issue that the storage industry needs to focus on and resolve. Especially in sequential write scenarios such as ZNS, combined with the read / write characteristics of NAND, upon power failure, the cache may contain data that is not yet filled for a write command, as well as data that has been filled but not yet written to NAND. To address this scenario, it is necessary to urgently save the data that has not yet been written to NAND. However, since the SSD is already powered off at this time, the capacitors within the SSD can only sustain operation for a limited time, often failing to securely, completely, and quickly store user data, resulting in poor data storage performance of SSDs during power outages.

[0003] In conclusion, improving the ability of SSDs to safely, completely, and quickly store user data during power-on and power-off cycles to enhance data storage performance is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a data power-on / off processing method, which can, to some extent, solve the technical problem of how to improve the data storage performance of SSDs during power-on and power-off. This application also provides a data power-on / off processing system, an electronic device, and a computer-readable storage medium.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] A data power-on / off processing method, characterized in that it includes:

[0007] When power is lost, the target data not written to the TLC and its first LBA address in the TLC are obtained; the target data and the first LBA address are stored in the SLC; the second LBA address and the second PBA address of the target data stored in the SLC are obtained; and a mapping relationship is established between the second LBA address and the first LBA address and the second PBA address, respectively.

[0008] After power-on, the target data and the first LBA address are read from the SLC according to the second LBA address and the second PBA address. The target data is sorted according to the first LBA address to obtain a target sorting result. The target sorting result is classified into a first sorting result that meets the minimum data write volume of the TLC and a second sorting result that does not meet the minimum data write volume of the TLC. The target data is written into the TLC based on the first sorting result and the second sorting result.

[0009] Preferably, the step of reading the target data and the first LBA address from the SLC based on the second LBA address and the second PBA address includes:

[0010] The target data and the first LBA address are read from the SLC and stored in the cache.

[0011] Preferably, writing the target data into the TLC based on the first sorting result and the second sorting result includes:

[0012] Write the first data corresponding to the first sorting result into the TLC;

[0013] Write the second data corresponding to the second sorting result back from the cache to memory. After the second data reaches the minimum data write volume of the TLC, write the second data into the TLC.

[0014] Preferably, writing the target data into the TLC includes:

[0015] Identify the block in the TLC where the target data is to be written;

[0016] Determine whether there are data holes in the block to be written;

[0017] If the block to be written has data gaps, the data already written in the block to be written and the target data are sequentially written into another block;

[0018] If the block to be written does not have any data gaps, the target data will be written sequentially into the block to be written.

[0019] Preferably, the step of sorting the target data according to the first LBA address to obtain the target sorting result includes:

[0020] The target data is sorted according to the first LBA address in ascending order to obtain the target sorting result.

[0021] Preferably, the step of sorting the target data according to the first LBA address to obtain the target sorting result includes:

[0022] The target data is sorted according to the first LBA address and the zone type in which the target data is stored, to obtain the target sorting result that corresponds one-to-one with the zone.

[0023] Preferably, the process of storing the target data and the first LBA address into the SLC includes:

[0024] If the target data does not meet the minimum data write size of the SLC, then concatenated data is determined, and the target data and the concatenated data are written together into the SLC. The data size of the concatenated data is the difference between the minimum data write size of the SLC and the data size of the target data.

[0025] A data power-on / off processing system, comprising:

[0026] A power-down processing module is used to, when power is lost, acquire the target data not written to the TLC and its first LBA address in the TLC; store the target data and the first LBA address into the SLC; acquire the second LBA address and the second PBA address of the target data stored in the SLC; and establish a mapping relationship between the second LBA address and the first LBA address and the second PBA address, respectively.

[0027] The power-on processing module is used to, after power-on, read the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address, sort the target data according to the first LBA address to obtain a target sorting result; classify the target sorting result into a first sorting result that meets the minimum data write volume of the TLC and a second sorting result that does not meet the minimum data write volume of the TLC, and write the target data into the TLC based on the first sorting result and the second sorting result.

[0028] An electronic device, comprising:

[0029] Memory, used to store computer programs;

[0030] A processor, configured to implement the steps of any of the above-described data power-on / off processing methods when executing the computer program.

[0031] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above-described data power-on / off processing methods.

[0032] This application provides a data power-on / off processing method. When power is off, the method involves: acquiring target data not yet written to a TLC and its first LBA address in the TLC; storing the target data and the first LBA address in an SLC; acquiring the second LBA address and second PBA address of the target data stored in the SLC; establishing mapping relationships between the second LBA address and the first LBA address and the second PBA address respectively; after power-on, reading the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address; sorting the target data according to the first LBA address to obtain a target sorting result; classifying the target sorting result into a first sorting result that meets the minimum data write volume of the TLC and a second sorting result that does not meet the minimum data write volume of the TLC; and writing the target data into the TLC based on the first sorting result and the second sorting result. In this application, during power failure, the first LBA address and target data are stored in the SLC. Since the SLC has the fastest read / write speed, data can be quickly saved after power failure. After power-on, the target data is sorted according to the first LBA address to obtain a sequential target sorting result. This sorting result is further categorized into a first sorting result that meets the minimum data write limit of the TLC and a second sorting result that does not meet the minimum data write limit of the TLC. Finally, the target data is written to the TLC based on the first and second sorting results. This allows for accurate and systematic writing of target data to the TLC, improving the data write rate after power-on and ultimately enhancing the data storage performance of the SSD during power-on and power-off cycles. The data power-on / off processing system, electronic device, and computer-readable storage medium provided in this application also solve the corresponding technical problems. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0034] Figure 1 This is a first flowchart of a data power-on / off processing method provided in an embodiment of this application;

[0035] Figure 2 This is a schematic diagram illustrating the mapping principle between LBA and PBA.

[0036] Figure 3 This is a schematic diagram of the internal structure of a NAND flash memory.

[0037] Figure 4 A diagram illustrating the amount of data written in a single TLC NAND flash memory operation;

[0038] Figure 5 This is a diagram illustrating the zone divisions within a ZNS.

[0039] Figure 6 A schematic diagram illustrating the writing of data to TLC nand in a non-power-loss scenario for ZNS;

[0040] Figure 7 This is a schematic diagram illustrating the formation of voids in TLC (Transverse Cavities).

[0041] Figure 8 Flowchart for power-down data flushing;

[0042] Figure 9 A second flowchart of a data power-on / off processing method provided in an embodiment of this application;

[0043] Figure 10 A schematic diagram illustrating the mapping relationship between the first LBA address and the second LBA address;

[0044] Figure 11 A schematic diagram illustrating the generation of the target sorting results;

[0045] Figure 12 A schematic diagram illustrating the results of sorting the target.

[0046] Figure 13 This is a schematic diagram of the buffer;

[0047] Figure 14 This is a schematic diagram illustrating the generation of the first and second sorting results;

[0048] Figure 15 This is a schematic diagram of the first and second sorting results;

[0049] Figure 16 This is a diagram illustrating data integration and recovery.

[0050] Figure 17 A schematic diagram of a data power-on / off processing system provided in an embodiment of this application;

[0051] Figure 18 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0052] Figure 19 This is another structural schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] Please see Figure 1 , Figure 1 This is a first flowchart of a data power-on / off processing method provided in an embodiment of this application.

[0055] This application provides a data power-on / off processing method, which may include the following steps:

[0056] Step S101: When power is off, obtain the target data that has not been written to the TLC and its first LBA address in the TLC; store the target data and the first LBA address into the SLC; obtain the second LBA address and the second PBA address of the target data stored in the SLC; establish the mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively.

[0057] In practical applications, after an SSD loses power, to ensure continued data reading and writing upon power-up, it is necessary to obtain the target data not yet written to the TLC in the NAND flash memory and its first LBA address within the TLC. In this application, the target data and the first LBA address need to be stored in the SLC within the NAND flash memory. Since the SLC has the fastest read / write speed, it can quickly store the data address and the first LBA address. During this process, the target data not yet written to the TLC can be data that has not yet been written to the TLC, or data that was being written to the TLC but failed, etc. Its type can be determined according to actual needs, and this application does not impose specific limitations here. Furthermore, it is also necessary to obtain the second LBA address and the second PBA address of the target data stored in the SLC, and establish a mapping relationship between the second LBA address and the first LBA address and the second PBA address, respectively, so that the target data and the first LBA address can be read from the SLC subsequently based on this mapping relationship.

[0058] It should be noted that the LBA (Logical Block Address) in this application is a general mechanism used to represent the location of data, referring to the logical address of a data block. Its size can be determined according to the SSD's data format; for example, an LBA can be 512 bytes or 4KB. Furthermore, the LBA needs to rely on the PBA (Physical Block Address) to interact with the SSD. The PBA refers to the actual physical address of the LBA data after it has been written to the SSD's NAND flash memory. During firmware management, the size of a PBA can be fixed at 4KB, and one PBA can correspond to one or more LBAs. In addition, the NAND flash memory used by SSDs requires erasure before writing, and the characteristics of reading and writing in units of pages, while erasure is done in units of blocks (composed of multiple pages), mean that the relationship between LBA and PBA is no longer fixed. Therefore, the SSD's main controller uses an LBA and PBA mapping table to manage the flash memory. When new data needs to be written, the controller writes the new data to an empty flash memory space (in an erased state), and then updates the mapping table data, pointing the LBA to the new PBA, such as... Figure 2 As shown.

[0059] It should also be noted that NAND flash memory has limitations on the amount of data that can be written. Figure 3 Taking the internal architecture of the plane TLC as an example, NAND has two LUNs. The LUN is the smallest independent unit in NAND that can execute commands and report its own status. The plane is the smallest unit in NAND that can be operated according to read, write, erase and other commands. A plane is a storage matrix containing several blocks. The block is the smallest unit of the erase command, which contains several pages. The page is the smallest unit in flash memory that can be read and written. The size of each page can be 16KB, etc. Taking the 4KB format of SSD disk as an example, 4 LBAs (1 LBA 4KB) can be written in one page. When writing 4KB of data, the entire page must be written at the NAND level, resulting in an actual data write of 16KB. If multi-plane page programming is used, a single write command operates on pages with the same number in both plane 0 and plane 1. However, with TLC NAND, three pages need to be written simultaneously. For example, if the data written in one operation consists of pages 0, 1, and 2 in plane 0 and pages 0, 1, and 2 in plane 1, then 16KB * 2 * 3 = 96KB of data needs to be written at once. The write volume in a single TLC programming operation is as follows... Figure 4As shown. Furthermore, in order to meet the characteristics of NAND, after a write command is issued, the data will first be cached in a segment of DDR memory. When the required 96KB of data for a single write command is accumulated, it will be actually written to NAND. In other words, a single data write to TLC NAND contains multiple LBAs and is written to multiple PBAs.

[0060] Step S102: After power-on, read the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address, sort the target data according to the first LBA address to obtain the target sorting result; classify the target sorting result into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC, and write the target data into the TLC based on the first sorting result and the second sorting result.

[0061] In practical applications, after the SSD powers on, the target data and the first LBA address need to be read from the SLC based on the second LBA address and the second PBA address. For example, the mapping relationship can be used to determine the various second LBA addresses that store the first LBA address, and then the mapping relationship can be used to determine the second PBA address corresponding to the second LBA address. Finally, the target data and the first LBA address are read from the second PBA address. Considering that the data is written to the TLC in the order of the first LBA address, the target data can be sorted according to the first LBA address to obtain a sequential target sorting result. Considering that the TLC has a minimum data write limit, data that meets the minimum write limit can be directly written to the TLC, while data that does not meet the minimum write limit cannot be directly written to the TLC. Therefore, in order to accurately write these two types of data to the TLC, the target sorting result can be classified into a first sorting result that meets the minimum data write limit of the TLC and a second sorting result that does not meet the minimum data write limit of the TLC. Finally, the target data is written to the TLC based on the first sorting result and the second sorting result.

[0062] It should be noted that when ZNS (Zoned Namespace) technology is applied to an SSD, it divides the entire LBA range of the SSD namespace into several equal-length intervals. These equal-length LBA intervals are called a zone; that is, a zone is a continuous and non-overlapping range of LBAs. Figure 5As shown, assuming each zone has n LBAs, where LBA 0 is the smallest LBA in zone 0 and LBA n-1 is the largest LBA in zone 0, for zone 1, LBA n is the smallest LBA and LBA 2n-1 is its largest LBA, so the smallest LBA in zone m is LBA n*(m-1) and the largest LBA is LBAnm-1. Furthermore, the ZNS protocol stipulates that data can be read in any order within each zone, but must be written sequentially, i.e., it supports random reads and sequential writes. Therefore, the host needs to ensure that the transmitted LBAs are ordered and non-repeating. According to the protocol specification, each zone has its own independent state management. Before rewriting, the zone's state management information must be reset, and then writing must start from LBA 0. In this application, during the power-on process, the data addresses are first sorted according to the first LBA address to obtain the target sorting result. Then, the target sorting result is classified into a first sorting result that meets the minimum data write volume of TLC and a second sorting result that does not meet the minimum data write volume of TLC. The target data is written into TLC based on the first sorting result and the second sorting result, which can meet the sequential write requirements of ZNS technology. Therefore, the solution of this application is also applicable to SSDs processed by ZNS technology.

[0063] For ease of understanding, let's assume the process of writing data to TLC NAND in a non-power-loss scenario using ZNS is as follows: Figure 6 As shown, because data is written to NAND concurrently, multiple data entries are written to the TLC NAND on different data channels at the same time. If a power outage occurs, some data may have already been written to the TLC NAND, while some data may not have been processed. In this case, some parts of the TLC NAND will have been written to, while others will not, creating gaps in the NAND. Figure 7 As shown in the diagram, LBA0-23, LBA24-47, and LBA48-71 in zone 0 represent three TLC data writes, which were written together before the power failure. However, due to the power failure, LBA0-23 and LBA48-71 had already been flushed to the TLC, while LBA24-47 had not yet been flushed to the TLC NAND. In zone 1, LBA0-23 was written to the TLC before the power failure, while LBA24-40 was not yet full and was temporarily stored in the cache, not written to the TLC. At this point, the method described in this application can be applied to process the SSD. The processing procedure is as follows: Figure 8 As shown, FE refers to the front end, FTL refers to the flash memory conversion layer, and BE refers to the back end.

[0064] This application provides a data power-on / off processing method. When power is off, the method involves: acquiring target data not yet written to a TLC and its first LBA address in the TLC; storing the target data and the first LBA address in an SLC; acquiring the second LBA address and second PBA address of the target data stored in the SLC; establishing mapping relationships between the second LBA address and the first LBA address and the second PBA address respectively; after power-on, reading the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address; sorting the target data according to the first LBA address to obtain a target sorting result; classifying the target sorting result into a first sorting result that meets the minimum data write volume of the TLC and a second sorting result that does not meet the minimum data write volume of the TLC; and writing the target data into the TLC based on the first sorting result and the second sorting result. In this application, when power is lost, the first LBA address and the target data are stored in the SLC. Since the SLC has the fastest read and write speed, it can quickly save the data after power loss. After power is restored, the target data is sorted according to the first LBA address to obtain a sequential target sorting result. The target sorting result is classified into a first sorting result that meets the minimum data write volume of the TLC and a second sorting result that does not meet the minimum data write volume of the TLC. Finally, the target data is written into the TLC based on the first sorting result and the second sorting result. The target data can be written into the TLC accurately and systematically, which improves the data write rate after power-on and ultimately improves the data storage performance of the SSD during power-on and power-off.

[0065] Please see Figure 9 , Figure 9 This is a second flowchart of a data power-on / off processing method provided in an embodiment of this application.

[0066] This application provides a data power-on / off processing method, which may include the following steps:

[0067] Step S201: When power is off, obtain the target data in the TLC that has not been written to NAND and its first LBA address in the TLC; store the target data and the first LBA address in the SLC; obtain the second LBA address and the second PBA address of the target data stored in the SLC; establish the mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively.

[0068] Step S202: After power-on, read the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address and put them into the cache. Sort the target data according to the first LBA address to obtain the target sorting result. Classify the target sorting result into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC. Write the first data corresponding to the first sorting result into the TLC. Write the second data corresponding to the second sorting result back from the cache to the memory. After the second data reaches the minimum data write amount of the TLC, write the second data into the TLC.

[0069] In practical applications, during the process of reading target data and the first LBA address from the SLC, the data address and the first LBA address can be read from the SLC into the cache so that the data address and the first LBA address can be processed in the cache.

[0070] In specific application scenarios, during the process of writing target data into TLC based on the first sorting result and the second sorting result, the first data corresponding to the first sorting result can be written into TLC; the second data corresponding to the second sorting result can be written back from the cache to memory, and after the second data reaches the minimum data write volume of TLC, the second data can be written into TLC.

[0071] In specific application scenarios, because SSDs can read data in any order after being processed by ZNS technology, but must be written in a sequential manner, i.e., supporting random reads and sequential writes, during the process of writing target data to TLC, it is necessary to determine the block in TLC where the target data is to be written; determine whether there are data gaps in the block to be written; if there are data gaps in the block to be written, then the data already written in the block to be written and the target data are sequentially written to another block, and the block to be written can only be written to again after it has been reset; if there are no data gaps in the block to be written, then the target data is sequentially written to the block to be written.

[0072] In practical applications, when sorting target data according to the first LBA address to obtain the target sorting result, the target data can be sorted in ascending order of the first LBA address. Furthermore, in specific application scenarios, the target data can be sorted in ascending order of the first LBA address based on the category of the zone to which the target data is to be written, resulting in target sorting results corresponding one-to-one with each zone, such as the sorting result corresponding to zone1, the sorting result corresponding to zone2, etc. Each sorting result can include the target data and the first LBA address, etc., but this application does not impose specific limitations on these aspects.

[0073] In specific application scenarios, if the target data does not meet the minimum data write size of the SLC during the process of storing the target data and the first LBA address into the SLC, then it is possible to determine the concatenation data and write the target data and the concatenation data together into the SLC. The data size of the concatenation data is the difference between the minimum data write size of the SLC and the data size of the target data.

[0074] In practical applications, to quickly locate LBA 0 from the PBA in the SLC for data processing, a `SLC start PBA` character can be set in the SLC to record the first physical address PBA (which block, page) of LBA 0 in the SLC. The initial value of `SLC start PBA` can be set to an invalid value of 0xFFFFFFFF. As data is stored in the SLC, the value of `SLC start PBA` is modified accordingly. At this point, the mapping relationship reflecting the storage relationship between the first LBA address and the second LBA address can be as follows: Figure 10 As shown, furthermore, the mapping relationship can also store data such as which zone it belongs to, what the data format is, and which LBAs correspond to the user data. Correspondingly, the process of reading the target data and the first LBA address from the SLC into the cache, and sorting the target data according to the first LBA address to obtain the target sorting result can be as follows: Figure 11 As shown, and considering that SSDs under ZNS technology process data according to zones, a linked list can be used to record the LBA information of the corresponding zone. That is, this process includes the following steps:

[0075] After power-on, the mapping relationship between the LBA and PBA of the SLC is read from the NAND flash memory;

[0076] Traverse the mapping relationship of SLC and determine whether the current LBA of SLC is less than the maximum LBA. This maximum LBA is also the maximum number of LBAs stored in a single page of SLC.

[0077] If the current LBA of the SLC is greater than or equal to the maximum LBA, then all data has been read and sorted according to zone. For ease of understanding, assume that data is read from pages 0 to 5 of the SLC nand and placed into the buffer. The data in page 1 is not sequential (TLC LBA 32, 33, 34, 41, 42, 43, 44, 45), and page 5 contains only one 4KB valid data (TLCLBA 31). After sorting, the SLC nand stores data from zone 0 and zone 1. After the data is read into the buffer, two linked lists are allocated: list 0 for zone 0 and list 1 for zone 1. After the data is read sequentially, the list to be linked is selected according to the zone ID, and the insertion position is found by traversing the list backwards according to the TLC LBA of the data. The final storage order in the list is as follows. Figure 12 As shown, the linked list can record the LBA value of the TLC and the corresponding data address, etc.

[0078] If the current LBA of the SLC is less than the maximum LBA, then the mapping relationship corresponding to the current LBA is obtained;

[0079] Determine if the current LBA's SLC start PBA is valid;

[0080] If the SLC start PBA of the current LBA is invalid, then increment the value of the current LBA by 1 and return to the step of determining whether the current LBA of the SLC is less than the maximum LBA.

[0081] If the current LBA's SLC start PBA is valid, then a buffer is allocated. This buffer is a pre-allocated contiguous block of DDR memory, divided into several parts, each with the same page size as the SLC (multi-plane page, 16KB * 2 planes = 32KB). Figure 13 As shown; obtain the NAND physical address through the SLC PBA, read the data on the SLC page into the buffer; LBA_Count starts from zero and traverses the TLC LBA in the mapping relationship[8];

[0082] Check if LBA_Count is less than 8. LBA_Count is used to record the number of PBAs corresponding to LBA. 8 represents the maximum number of PBAs corresponding to a single LBA.

[0083] If LBA_Count is greater than or equal to 8, then increment the current LBA value by 1 and return to the step of determining whether the current LBA of the SLC is less than the maximum LBA;

[0084] If LBA_Count is less than 8, then check if the TLC LBA array elements are valid;

[0085] If an element in the TLC LBA array is invalid, increment the value of LBA_Count by 1 and return to the step of determining whether the current LBA of the SLC is less than the maximum LBA.

[0086] If the TLC LBA array element is valid, select the data list according to the zone id, add the list in ascending order of LBA size, increment the LBA_Count value by 1, and return to execute the step of determining whether the current LBA of the SLC is less than the maximum LBA.

[0087] Furthermore, based on the above embodiments, such as Figure 14 As shown, in the process of classifying the target sorting results into a first sorting result that satisfies the minimum data write amount of TLC and a second sorting result that does not satisfy the minimum data write amount of TLC, different linked lists can be used to record the first sorting result and the second sorting result. This can include the following steps:

[0088] Initialize the current list to 0;

[0089] Determine if the current value in the list is less than the maximum value in the list;

[0090] If the current value in the list is greater than or equal to the maximum value in the list, the data classification ends and subsequent data processing begins;

[0091] If the current value of the list is less than the maximum value of the list, then check if there are any data nodes in the current list;

[0092] If there are no data nodes in the current list, increment the current list value by 1 and return to the step of checking whether the current list value is less than the maximum value of the list;

[0093] If there are data nodes in the current list, then determine whether management resources have been requested. Management resources are used to temporarily store LBA data addresses and other information.

[0094] If you have not applied for management resources, then apply for management resources;

[0095] If management resources have already been requested, then retrieve the head node and store the LBA data address into the management resources;

[0096] Determine whether the LBA address recorded in the management resources has reached the write limit of TLC;

[0097] If the LBA address recorded in the management resource has not reached the write limit of TLC, then check if there are still data nodes in the current list. If there are still data nodes in the current list, return to the step of retrieving the head node and storing the LBA data address in the management resource; if there are no more data nodes in the current list, restore the cache used, the management resource storage linked list Y, and check again if there are still data nodes in the current list. If yes, return to the step of requesting management resources; if no, increment the value of the current list by 1, and return to the step of checking if the value of the current list is less than the maximum value of the list.

[0098] If the LBA addresses recorded in the management resources reach the write limit of the TLC, then determine whether linked list X has been requested.

[0099] If linked list X has not been allocated, then linked list X will be allocated in zone n;

[0100] If linked list X has already been applied for, it will be used during data processing, and management resources will be stored in linked list X.

[0101] Determine if there are any data nodes in the current list. If yes, return to the step of requesting management resources; otherwise, increment the current list value by 1 and return to the step of checking if the current list value is less than the maximum value of the list. In this way, as... Figure 15 As shown, after sorting, the SLC data is organized and appended to the corresponding linked lists. Data that meets the requirements for TLC writing is placed in linked list A, which records the first sorting result. Subsequent data sorting will write this data to the TLC. Data that does not meet the requirements for TLC to write at once is placed in linked list B, which records the second sorting result. This data will be restored to the cache later. Once host data is received and sufficient data is accumulated, a write command will be issued to write the data to the TLC. Correspondingly, the process of writing the target data into the TLC based on the first and second sorting results can be described as follows: Figure 16 As shown.

[0102] Please see Figure 17 , Figure 17 This is a schematic diagram of a data power-on / off processing system provided in an embodiment of this application.

[0103] This application provides a data power-on / off processing system, which may include:

[0104] The power-down processing module 101 is used to, when power is lost, obtain the target data that has not been written to the TLC and its first LBA address in the TLC; store the target data and the first LBA address into the SLC; obtain the second LBA address and the second PBA address of the target data stored in the SLC; and establish a mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively.

[0105] The power-on processing module 102 is used to read the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address after power-on, sort the target data according to the first LBA address to obtain the target sorting result; classify the target sorting result into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC, and write the target data into the TLC based on the first sorting result and the second sorting result.

[0106] This application provides a data power-on / off processing system, wherein the power-on processing module may include:

[0107] The read unit is used to read the target data and the first LBA address from the SLC into the cache.

[0108] This application provides a data power-on / off processing system, wherein the power-on processing module may include:

[0109] The first write unit is used to write the first data corresponding to the first sorting result into the TLC; write the second data corresponding to the second sorting result back from the cache to the memory; and write the second data into the TLC after the second data reaches the minimum data write amount of the TLC.

[0110] This application provides a data power-on / off processing system, wherein the power-on processing module may include:

[0111] The second writing unit is used to determine the block in the TLC where the target data is to be written; to determine whether there are data gaps in the block to be written; if there are data gaps in the block to be written, the already written data and the target data in the block to be written are sequentially written into another block; if there are no data gaps in the block to be written, the target data is sequentially written into the block to be written.

[0112] This application provides a data power-on / off processing system, wherein the power-on processing module may include:

[0113] The first sorting unit is used to sort the target data in ascending order according to the first LBA address to obtain the target sorting result.

[0114] This application provides a data power-on / off processing system, wherein the power-on processing module may include:

[0115] The second sorting unit is used to sort the target data according to the first LBA address and the zone type in which the target data is stored, so as to obtain the target sorting result that corresponds one-to-one with the zone.

[0116] This application provides a data power-on / off processing system. The power-off processing module can be used to: during the process of storing target data and the first LBA address into the SLC, if the target data and the first LBA address do not meet the minimum data write volume of the SLC, then determine the concatenation data, and write the target data and the concatenation data together into the SLC. The data volume of the concatenation data is the difference between the minimum data write volume of the SLC and the data volume of the target data.

[0117] This application also provides an electronic device and a computer-readable storage medium, both of which have the corresponding effects of the data power-on / off processing method provided in the embodiments of this application. Please refer to... Figure 18 , Figure 18 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0118] An electronic device provided in this application includes a memory 201 and a processor 202. The memory 201 stores a computer program, and when the processor 202 executes the computer program, it implements the steps of the data power-on / off processing method described in any of the above embodiments.

[0119] Please see Figure 19 Another electronic device provided in this application embodiment may further include: an input port 203 connected to the processor 202 for transmitting commands input from the outside to the processor 202; a display unit 204 connected to the processor 202 for displaying the processing results of the processor 202 to the outside; and a communication module 205 connected to the processor 202 for realizing communication between the electronic device and the outside. The display unit 204 may be a display panel, a laser scanner, or the like; the communication method adopted by the communication module 205 includes, but is not limited to, Mobile High-Definition Link (MHL), Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), wireless connectivity: Wireless Fidelity (WiFi), Bluetooth communication technology, Bluetooth Low Energy communication technology, and communication technology based on IEEE 802.11s.

[0120] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the steps of the data power-on / off processing method described in any of the above embodiments.

[0121] The computer-readable storage media involved in this application include random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs (Compact Disc Read-Only Memory), or any other form of storage media known in the art.

[0122] For descriptions of relevant parts in the data power-on / off processing system, electronic device, and computer-readable storage medium provided in the embodiments of this application, please refer to the detailed descriptions of the corresponding parts in the data power-on / off processing method provided in the embodiments of this application, which will not be repeated here. Furthermore, parts of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0123] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0124] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data power-on / off processing method, characterized in that, include: During power failure, retrieve the target data that has not been written to the TLC and its first LBA address in the TLC; Store the target data and the first LBA address into the SLC; Obtain the second LBA address and the second PBA address of the target data and store them in the SLC; Establish mapping relationships between the second LBA address and the first LBA address and the second PBA address, respectively; After power-on, the target data and the first LBA address are read from the SLC according to the second LBA address and the second PBA address, and the target data is sorted according to the first LBA address to obtain the target sorting result; The target sorting results are classified into a first sorting result that meets the minimum data write volume of the TLC and a second sorting result that does not meet the minimum data write volume of the TLC. The target data is written into the TLC based on the first sorting result and the second sorting result. The step of reading the target data and the first LBA address from the SLC based on the second LBA address and the second PBA address includes: Read the target data and the first LBA address from the SLC into the cache; The step of writing the target data into the TLC based on the first sorting result and the second sorting result includes: Write the first data corresponding to the first sorting result into the TLC; Write the second data corresponding to the second sorting result back from the cache to memory. After the second data reaches the minimum data write volume of the TLC, write the second data into the TLC.

2. The method according to claim 1, characterized in that, Writing the target data into the TLC includes: Identify the block in the TLC where the target data is to be written; Determine whether there are data holes in the block to be written; If the block to be written has data gaps, the data already written in the block to be written and the target data are sequentially written into another block; If the block to be written does not have any data gaps, the target data will be written sequentially into the block to be written.

3. The method according to any one of claims 1 to 2, characterized in that, The step of sorting the target data according to the first LBA address to obtain the target sorting result includes: The target data is sorted according to the first LBA address in ascending order to obtain the target sorting result.

4. The method according to claim 3, characterized in that, The step of sorting the target data according to the first LBA address to obtain the target sorting result includes: The target data is sorted according to the first LBA address and the zone type in which the target data is stored, to obtain the target sorting result that corresponds one-to-one with the zone.

5. The method according to claim 4, characterized in that, The process of storing the target data and the first LBA address into the SLC includes: If the target data does not meet the minimum data write size of the SLC, then concatenated data is determined, and the target data and the concatenated data are written together into the SLC. The data size of the concatenated data is the difference between the minimum data write size of the SLC and the data size of the target data.

6. A data power-on / off processing system, characterized in that, include: The power-down processing module is used to obtain the target data that has not been written to the TLC and its first LBA address in the TLC when power is lost. Store the target data and the first LBA address into the SLC; Obtain the second LBA address and the second PBA address of the target data and store them in the SLC; Establish mapping relationships between the second LBA address and the first LBA address and the second PBA address, respectively; The power-on processing module is used to read the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address after power-on, and sort the target data according to the first LBA address to obtain the target sorting result; The target sorting results are classified into a first sorting result that meets the minimum data write volume of the TLC and a second sorting result that does not meet the minimum data write volume of the TLC. The target data is written into the TLC based on the first sorting result and the second sorting result. The power-on processing module includes: A reading unit is used to read the target data and the first LBA address from the SLC into a cache; The power-on processing module includes: The first writing unit is used to write the first data corresponding to the first sorting result into the TLC; write the second data corresponding to the second sorting result back from the cache to the memory; and write the second data into the TLC after the second data reaches the minimum data write amount of the TLC.

7. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the data power-on / off processing method as described in any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data power-on / off processing method as described in any one of claims 1 to 5.

Images