High-density optoelectronic integrated three-dimensional packaging structure and manufacturing method thereof

Abstract

The present invention provides a high-density optoelectronic integrated three-dimensional packaging structure and a manufacturing method thereof, comprising: a packaging substrate and an optical chip, a redistribution layer, and an electrical chip sequentially stacked on the packaging substrate; the electrical chip including a functional surface and arranged so that its functional surface is in direct contact with the redistribution layer; the electrical chip being electrically interconnected with the optical chip via metal wiring within the redistribution layer to allow output signals of the optoelectronic conversion element to be transmitted to a transimpedance amplifier chip via the metal wiring within the redistribution layer; an electrical connection component further provided on the redistribution layer, electrically coupled to the transimpedance amplifier chip via the metal wiring within the redistribution layer to enable signal extraction from the transimpedance amplifier chip, thereby shortening the transmission path, reducing losses, increasing the transmission rate, and reducing the package height. The manufacturing method of the present invention omits the bumping process below the electrical chip by forming a redistribution layer on one side of the functional surface of the electrical chip, making the entire manufacturing process simple and easy.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-density optoelectronic integrated three-dimensional packaging structure and a manufacturing method thereof. Background Art

[0002] With the development of high-speed data communication technology, the requirements for optical modules in terms of transmission speed, bandwidth, and high energy efficiency are becoming increasingly stringent. Optical modules offer advantages such as minimal signal attenuation, low energy consumption, and high bandwidth. Therefore, silicon photonics is being introduced to increase I / O bandwidth and minimize energy consumption. Among these, the optimal integration and packaging of optical integrated circuits (PICs) and electrical integrated circuits (EICs) is a key research area.

[0003] At present, there are three main types of optoelectronic chip packaging methods: two-dimensional planar integration, 2.5-dimensional integration and 3-dimensional stacking integration. Figure 1 As shown, the optical chip (PIC) 110 and the electrical chip (EIC) 130 are directly interconnected using wires and two-dimensional integrated assembly is achieved through COB packaging technology. This method is easy to implement, but the high-speed signal interconnection between the PIC and the EIC will be relatively long and the occupied area will be relatively large, which seriously limits the number of I / Os. Figures 2 and 3 As shown, the 2.5-dimensional and 3-dimensional integration of the optical chip 110 and the electrical chip 130 can achieve higher-density packaging integration, wherein the 3-dimensional integration shown realizes vertical electrical interconnection between the optical chip 110 and the electrical chip 130 through the silicon adapter board 120, more chips can be integrated per unit area, and the number of I / Os is further increased.

[0004] For the application of multi-channel optical transceiver modules, high-density interconnection of optical chips and electrical chips is required, thus necessitating the accommodation of more electrical chips per unit area and a higher I / O density. Existing three-dimensional optoelectronic integration solutions present the following problems in the application of optical transceiver modules: First, optical chips and electrical chips can be vertically interconnected through dielectric through vias (TMVs), but it is difficult for dielectric through vias (TMVs) to achieve a through-hole diameter below 50μm. The pad size above the through-holes is too large to meet the requirements of multi-channel signals and high-density interconnection within a limited area. Second, in optoelectronic integration solutions based on silicon adapters, optical chips and electrical chips are vertically interconnected through TSVs. Although TSVs can achieve a through-hole diameter below 50μm, the electrical connection between the silicon adapter and the chip requires a bump process, that is, both the front and back sides of the silicon adapter must have bumps or micro-bumps, which leads to greater process implementation difficulties and reliability issues.

[0005] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of this application and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a three-dimensional packaging structure for high-density optoelectronic integration and a manufacturing method thereof, so as to solve the problems that the existing optoelectronic integration adopts high-density packaging and the wiring becomes more difficult, and cannot meet the requirements of miniaturization, high integration, reliability, etc. of the optoelectronic module.

[0007] To achieve the above objectives and other related objectives, the present invention provides a high-density optoelectronic integrated three-dimensional packaging structure, comprising:

[0008] A packaging substrate and an optical chip, a rewiring layer and an electrical chip stacked in sequence on the packaging substrate;

[0009] The optical chip includes a photoelectric conversion element;

[0010] The electrical chip includes a functional surface and is arranged to be in direct contact with the rewiring layer with its functional surface, the electrical chip includes a transimpedance amplifier chip, and the electrical chip is electrically interconnected with the optical chip via metal wiring in the rewiring layer to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal wiring in the rewiring layer;

[0011] An electrical connection component is also provided on the rewiring layer. The electrical connection component is spaced apart from the electrical chip and is electrically coupled to the transimpedance amplifier chip through a metal line in the rewiring layer, so as to realize signal extraction of the transimpedance amplifier chip. A plastic packaging layer is also provided to cover the electrical connection component and the electrical chip.

[0012] Optionally, the transimpedance amplifier chip is configured to process multi-channel signals, and pads are provided on a functional surface of the transimpedance amplifier chip and have a pad layout with a center-to-center spacing of no more than 85 μm.

[0013] Optionally, the pads of the transimpedance amplifier chip directly contact the first main surface of the redistribution layer and are electrically interconnected with the photoelectric conversion element through metal lines and solder bumps in the redistribution layer, wherein the photoelectric conversion element includes a photodetector.

[0014] Optionally, the electrical connection component includes a silicon bridge chip, and the silicon bridge chip and the electrical chip are arranged side by side on the first main surface of the rewiring layer.

[0015] Optionally, the silicon bridge chip also includes a conductive through-hole and a contact pad connected to one end of the conductive through-hole, and the contact pad of the silicon bridge chip directly contacts the first main surface of the redistribution layer and is electrically coupled to the transimpedance amplifier chip through the metal line in the redistribution layer.

[0016] Optionally, the silicon bridge chip is configured with multiple conductive through-holes that allow the multi-channel signals of the transimpedance amplifier chip to be output in parallel to the outside. The height of the silicon bridge chip is greater than the height of the electrical chip so that the top of the silicon bridge chip is exposed and electrically connected to the packaging substrate through wire bonding, so as to realize the signal output of the transimpedance amplifier chip.

[0017] Optionally, the silicon bridge chip is further configured to supply power to the transimpedance amplifier chip.

[0018] Optionally, the optical chip includes a photosensitive area and an optical coupler, and the photosensitive area is optically coupled to an optical fiber inserted from a side of the optical chip through the optical coupler.

[0019] The present invention also provides a method for manufacturing a high-density optoelectronic integrated three-dimensional packaging structure, comprising the following steps:

[0020] Providing a mold frame, wherein a sacrificial material layer is formed on the mold frame;

[0021] Disposing an electrical chip and an electrical connection component at intervals and fixing them on the sacrificial material layer, wherein the functional surface of the electrical chip faces the sacrificial material layer, and the electrical chip includes a transimpedance amplifier chip;

[0022] Covering the electric chip and the electrical connection components to form a plastic packaging material layer;

[0023] Removing the sacrificial material layer, peeling off the mold frame to expose the functional surface of the electronic chip, and forming a redistribution layer on the side of the plastic encapsulation layer that exposes the functional surface of the electronic chip, wherein the redistribution layer includes a first main surface and a second main surface that are opposite to each other, a dielectric layer, and a metal circuit located within the dielectric layer, wherein the functional surface of the electronic chip is in direct contact with the first main surface of the redistribution layer;

[0024] Bonding an optical chip to the second main surface of the rewiring layer, the optical chip including a photoelectric conversion element, the optical chip being electrically interconnected with the electrical chip via metal wiring within the rewiring layer, so as to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal wiring within the rewiring layer;

[0025] The optical chip is fixed on a packaging substrate and electrically interconnected with the packaging substrate. The electrical connection component is electrically connected to the packaging substrate by wire bonding to realize signal extraction of the transimpedance amplifier chip.

[0026] Optionally, it also includes: before the step of forming the rewiring layer, forming a metallization pattern based on a graphic mask on the side of the plastic packaging material layer that exposes the functional surface of the electrical chip, wherein the transimpedance amplifier chip includes a solder pad located on its functional surface, and the metallization pattern is joined to the metal line in the rewiring layer by forming the rewiring layer on the metallization pattern.

[0027] Optionally, the electrical connection component includes a silicon bridge chip, and the manufacturing method further includes: directly contacting a contact pad located at one end of the silicon bridge chip with the redistribution layer, so that the electrical chip is electrically connected to the silicon bridge chip through a metal line in the redistribution layer.

[0028] Optionally, the optical chip further includes a bonding pad located on its functional surface, and the manufacturing method further includes: electrically coupling the bonding pad of the optical chip with the packaging substrate by wire bonding to receive external signals.

[0029] The present invention provides an optical transceiver module having the aforementioned high-density optoelectronic integrated three-dimensional packaging structure.

[0030] As described above, the high-density optoelectronic integrated three-dimensional packaging structure and its manufacturing method of the present invention have the following beneficial effects:

[0031] The present invention provides a high-density optoelectronic integrated three-dimensional packaging structure. An optical chip, a redistribution layer, and an electrical chip are stacked in sequence. The optical chip and the electrical chip are electrically interconnected using the redistribution layer, allowing the electrical chip to directly electrically contact the redistribution layer. This eliminates the need for a silicon adapter plate and microbumps, shortens the transmission path between the optoelectronic conversion element and the electrical chip, increases transmission rate, reduces transmission loss, effectively improves the reliability of the optoelectronic chip integration, and reduces the package height. Furthermore, a silicon bridge chip and the electrical chip are arranged side by side on the redistribution layer, and signals from the electrical chip are extracted through the silicon bridge chip, meeting external wiring requirements while increasing packaging density. Therefore, the present invention demonstrates the advantages of optoelectronic integration in high-density interconnection. The present invention also provides a method for fabricating a high-density optoelectronic integrated three-dimensional packaging structure. By forming a redistribution layer on one side of the electrical chip's functional surface, the bump process beneath the electrical chip is omitted, avoiding the impact on reliability caused by fine spacing between bonding pads of electrical chips, such as transimpedance amplifier chips. The entire fabrication process is simple and easy, reducing package height and packaging costs, thus laying the foundation for large-scale application of optoelectronic systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 3 A schematic diagram showing a typical implementation of optoelectronic co-packaging; wherein, Figure 1 Schematic diagram of the 2D optoelectronic co-packaging structure shown. Figure 2 Schematic diagram of the 2.5-dimensional optoelectronic co-packaging structure shown. Figure 3 Schematic diagram of the 3D optoelectronic co-packaging structure shown.

[0033] Figure 4 Shown is a schematic diagram of the pad layout of a transimpedance amplifier chip used in the high-density optoelectronic integrated three-dimensional packaging structure of the present invention.

[0034] Figure 5 Shown is a schematic structural diagram of a high-density optoelectronic integrated three-dimensional packaging structure of a comparative example of the present invention.

[0035] Figure 6 Shown is a structural schematic diagram of a three-dimensional packaging structure of high-density optoelectronic integration according to an embodiment of the present invention.

[0036] Figure 7A Shown is a SEM image of a silicon bridge chip used in the high-density optoelectronic integrated three-dimensional packaging structure of the present invention.

[0037] Figure 7B The figure is a chart illustrating exemplary structural parameters of a silicon bridge chip used in the three-dimensional packaging structure of high-density optoelectronic integration of the present invention.

[0038] Figures 8A and 8B Shown is a top view of the three-dimensional packaging structure of high-density optoelectronic integration of the present invention; wherein, Figure 8B for Figure 8A The local structure diagram at the location marked P.

[0039] Figures 9 to 14 Schematic diagrams showing the structures obtained at various stages of the method for manufacturing a high-density optoelectronic integrated three-dimensional packaging structure of the present invention.

[0040] Figure 15 Shown is a schematic diagram of a three-dimensional packaging structure of high-density optoelectronic integration, indicating the packaging height in an embodiment of the present invention.

[0041] Figure 16 The figure is a graph illustrating the results of an S-parameter model simulation test of the transmission characteristics of the electrical channel of the TIA chip in the high-density optoelectronic integrated three-dimensional packaging structure of the present invention using differential signals.

[0042] Component number description

[0043] 10, 110 optical chips

[0044] 120 Silicon Adapter Board

[0045] 130, 30 electrical chips

[0046] 1410 micro bumps

[0047] 1420 lead

[0048] 1440 BGA

[0049] 150 fiber

[0050] 160 package substrate

[0051] 20 Rewiring Layer

[0052] 220 Silicon Adapter Board

[0053] 310 transimpedance amplifier chip

[0054] 320 silicon bridge chip

[0055] 33 Plastic material layer

[0056] 330 plastic layer

[0057] 340 heat dissipation structure

[0058] 420 First Lead

[0059] 430 Second lead

[0060] 440 solder bumps

[0061] 450 bonding pads

[0062] 460 wire bonding pad

[0063] 510 Model Framework

[0064] 520 sacrificial material layer

[0065] 600 package substrate DETAILED DESCRIPTION

[0066] The following describes the implementation of the present invention through specific embodiments. People skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0067] See also Figures 4 to 16. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without changes in the substantive technical content.

[0068] An optical transceiver module consists of an optical transmitter and an optical receiver. The optical transceiver converts the received optical signal into an electrical signal that can be processed by an integrated circuit (IC). The integrated circuit (IC) includes a transimpedance amplifier (TIA) and a driver chip. With the development of high-speed data communication technology, more electrical chips need to be accommodated per unit area, as well as higher I / O density. Taking a 16-channel optical transceiver module as an example, the applicable transimpedance amplifier chip often has a fine-pitch pad layout. The typical layout structure can be seen in Figure 4 This type of electrical chip originally used wire bonding to electrically interconnect with other chips. However, this method limited packaging density and transmission speed, and could no longer meet the requirements for high-speed electrical signal transmission quality between the switching chip and the optical engine (used to implement the photoelectric conversion function). In other words, it could not meet the demand for high-density interconnection between the electrical chip and the optical chip.

[0069] like Figure 5 As shown, it shows a typical structure of a three-dimensional integrated optoelectronic co-package, wherein the optical chip 10 and the electrical chip 30 are stacked on the upper and lower surfaces of the silicon adapter plate 220, so that the electrical chip 30 is vertically interconnected with the optical chip 10 through the silicon adapter plate 220. A redistribution layer is also provided on the surface of the silicon adapter plate 220 near the electrical chip 300 to redistribute the solder joint positions of the silicon adapter plate 220 on the electrical chip side. Figure 5 As shown, the silicon interposer is provided with bumps on both sides, and the silicon interposer is electrically connected to the chips stacked above and below it through the bumps. The bumps need to fall on the chip's pads to form electrical contact, so the bumps are generally smaller than the chip's pads. As the chip size is scaled down, the pad layout of some chips tends to have a smaller spacing and size, and it is necessary to produce bumps with a smaller ball diameter and / or pitch. Figure 4For the TIA chip shown, bumps are made on the pads of this type of electrical chip. Depending on the size and spacing of the pads, bumps with a ball diameter of 50μm and a pitch of 85μm or smaller should be used. This will lead to problems such as high process implementation difficulty and high cost. In addition, because the pads of this type of electrical chip are distributed around the chip, even if the required bumps are made, underfill cannot be performed between the chips, which will lead to problems such as stress mismatch and reliability. Therefore, it can be seen that the above-mentioned three-dimensional packaging solution for optoelectronic integration is applied to multi-channel optical transceiver modules. Due to the increase in pin density, it will be difficult to increase the packaging density. It will also face problems such as the difficulty of implementing the underfill process and reliability.

[0070] To this end, the inventors have proposed an improved structure and manufacturing method for a high-density optoelectronic integrated three-dimensional packaging structure after long-term research.

[0071] like Figure 6 As shown, an embodiment of the present application provides a high-density optoelectronic integrated three-dimensional packaging structure, comprising: a packaging substrate 600 and an optical chip 10, a rewiring layer 20 and an electrical chip 30 stacked in sequence on the packaging substrate, wherein the optical chip 10 includes a photoelectric conversion element; the electrical chip 30 includes a functional surface and is configured to directly contact the rewiring layer 20 with its functional surface, wherein the electrical chip 30 includes a transimpedance amplifier chip 310, and the electrical chip 30 is electrically interconnected with the optical chip 10 through the metal wires in the rewiring layer to allow the output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip 310 via the metal wires in the rewiring layer.

[0072] It should be noted here that in the present invention, the electrical chip and the optical chip respectively use the side with the solder pad or solder pad as their functional surface. For example, the transimpedance amplifier chip 310 includes a functional surface and a solder pad located on the functional surface, and the optical chip 10 includes a functional surface and a bonding pad 450 located on the functional surface.

[0073] An electrical connection component is also provided on the rewiring layer 20. The electrical connection component is spaced apart from the electrical chip 30 and is electrically coupled to at least the transimpedance amplifier chip 310 through the metal line in the rewiring layer, so as to realize the signal extraction of the transimpedance amplifier chip. A plastic packaging layer 330 is also provided to cover the electrical connection component and the electrical chip.

[0074] In this embodiment, the transimpedance amplifier chip 310 is configured for multi-channel signal processing. A pad is provided on the functional surface of the transimpedance amplifier chip and has a pad layout with a center spacing of no more than 85 μm. The pad of the transimpedance amplifier chip directly contacts the first main surface of the rewiring layer and is electrically interconnected with the optical chip 10 through the metal lines in the rewiring layer.

[0075] Compared with the typical structure of the above-mentioned three-dimensional optoelectronic integration based on the adapter board, the technical solution based on the present application is to directly contact the electrical chip with the rewiring layer, especially to directly contact the transimpedance amplifier chip with the rewiring layer and realize electrical interconnection with the optical chip through the rewiring layer, thereby omitting the micro-bumps under the electrical chip, shortening the transmission path of the high-frequency transmission signal, reducing the transmission loss, reducing signal attenuation, avoiding the bottom filling after the bump connection and the reliability problems caused by it, and reducing the package height.

[0076] In one implementation, Figure 6 As shown, the electrical connection component includes a silicon bridge chip 320, and the silicon bridge chip 320 and multiple electrical chips 301, 302, 303, and 304 are arranged side by side on the first main surface of the rewiring layer. The electrical chip includes a transimpedance amplifier chip, wherein the fine-pitch pads of the transimpedance amplifier chip fan out the I / O end via the rewiring layer, and one end of the silicon bridge chip 320 is electrically contacted with the first main surface of the rewiring layer, thereby realizing signal lead-out of the electrical chip, which can not only meet the requirements of external wiring, but also improve the packaging density.

[0077] Figure 7A Shown is a microscopic image of a silicon bridge chip used in the high-density optoelectronic integrated three-dimensional packaging structure of the present invention. The silicon bridge chip is provided with conductive through-hole vias (TSVs) vertically penetrating and filled with metal. As an example, silicon bridge chip 320 includes a conductive via and a contact pad bonded to one end of the conductive via. The contact pad of the silicon bridge chip directly contacts the redistribution layer 20 and is electrically coupled to the transimpedance amplifier chip 310 via metal traces within the redistribution layer. Silicon bridge chip 320 is electrically coupled to the packaging substrate 600 via wire bonding to enable signal extraction from the transimpedance amplifier chip 310.

[0078] For example, Figure 8A As shown, the silicon bridge chip 320 is configured with multiple conductive through-holes that allow the multi-channel signals of the transimpedance amplifier chip to be output in parallel to the outside. The height of the silicon bridge chip is greater than the height of the electrical chip so that the top of the silicon bridge chip is exposed. The silicon bridge chip is electrically connected to the packaging substrate 600 through wire bonding to realize the signal output of the transimpedance amplifier chip.

[0079] It should be noted that the embodiment of the present invention uses four transimpedance amplifier chips to illustrate a three-dimensional packaging structure for high-density optoelectronic integration, but this does not mean that the types and numbers of electrical chips applicable to the present invention are limited thereto.

[0080] As an example, a bonding position is also provided on the top of the silicon bridge chip 320 , which is electrically connected to the packaging substrate 600 through, for example, gold wire leads, and the transimpedance amplifier chip leads the output signal to the bonding position of the silicon bridge chip 320 through the lateral channel of the rewiring layer 20 .

[0081] Furthermore, the silicon bridge chip 320 is also configured to supply power to the transimpedance amplifier chip, such as Figure 8A As shown, a portion of the DC signal between the power signal and the ground terminal of the transimpedance amplifier chip can also be led to the top of the silicon bridge chip 320, and connected to the transimpedance amplifier chip through the conductive vias of the silicon bridge chip and the metal lines in the redistribution layer.

[0082] Figure 7B Exemplary structural parameters of a silicon bridge chip used in the high-density optoelectronic integrated three-dimensional packaging structure of the present invention are provided. The silicon bridge chip 320 and the electrical chip 30 are electrically contacted with the first main surface of the redistribution layer. The height of the silicon bridge chip is greater than that of the electrical chip, so that the top of the silicon bridge chip is exposed. The TSV diameter and spacing of the silicon bridge chip can be adjusted according to the number of channels and the package size, and are not particularly limited here.

[0083] like Figure 8B As shown in FIG, compared with the traditional silicon transfer board, the silicon bridge chip has a smaller TSV size, which allows the routing required for multi-channel signals to be arranged accordingly in a limited area, so that the contact pad (PAD) spacing of the silicon bridge chip can be reduced, for example Figure 8B The contact pad pitch shown is reduced to 150μm, thereby increasing the circuit operating speed while taking into account the wiring requirements of external interconnections.

[0084] In a specific example, a heat dissipation structure 340 is also provided on the top of the electrical chip. The heat dissipation structure 340 can dissipate heat from the top of the electrical chip 30 to reduce heat conduction from the electrical chip to the optical chip. The height of the silicon bridge chip is greater than the sum of the heights of the electrical chip and the heat dissipation structure.

[0085] Those skilled in the art will appreciate that the height of the silicon bridge chip can be flexibly determined according to the thickness of the electrical chip covered by the plastic packaging layer, as long as the top of the silicon bridge chip is exposed while ensuring that the periphery of the electrical chip is covered.

[0086] In another implementation, the electrical connection component includes a metal conductive column, one end of which is substantially flush or level with the surface of the plastic encapsulation layer 330 and the other end of which contacts the contact on the first main surface of the redistribution layer.

[0087] In some embodiments, the optical chip 10 includes a functional surface and a wire bonding pad 460 located on the functional surface. The wire bonding pad 460 is electrically connected to the package substrate 600 via wire bonding for receiving external signals. In a specific example, the optical chip 10 also includes a photosensitive area and an optical coupler. The photosensitive area is optically coupled to the optical fiber 150 inserted from the side of the optical chip via the optical coupler.

[0088] For example, the optical chip 10 includes a photoelectric conversion element, each photoelectric conversion element includes a bonding pad located on its functional surface, and a solder joint or solder layer is formed between the bonding pad and the solder bump 440. The transimpedance amplifier chip receives and processes multi-channel signals in parallel via the rewiring layer, and transmits high-speed electrical signals to external chips and / or systems through electrical connection components.

[0089] It should be noted that, although the external interconnection of the package structure is achieved based on the solder ball method, the present invention also covers metal bumps, solder bumps and other methods of achieving external interconnection.

[0090] In order to verify the advantages of the implementation of the present invention in terms of package size and transmission quality, the preferred method of the three-dimensional packaging structure of high-density optoelectronic integration of the present invention was used to carry out package height and transmission loss simulation tests, and the comparative example of the present invention was used to carry out package height tests as a control. The obtained package height test results are respectively marked on Figure 6 and Figure 15 The transmission characteristics simulation test and transmission loss results of the electrical channel of the transimpedance amplifier chip according to the preferred embodiment of the present invention are shown in FIG. Figure 16 The differential signal transmission path follows the metal traces within the TIA chip and the redistribution layer, passing through the conductive vias of the silicon bridge chip to the bonding point. Simulation results based on the differential signal show that the transmission loss of the differential signal is less than 0.71dB at 25GHz. The entire package structure achieves high-density optoelectronic integration using only a single layer of a mature bumping process, reducing package height and signal attenuation, facilitating high-speed electrical signal transmission within the optical receiver module.

[0091] This embodiment further provides an optical transceiver module having a high-density optoelectronic integrated three-dimensional packaging structure as described above.

[0092] The present invention also provides a method for manufacturing a high-density optoelectronic integrated three-dimensional packaging structure. The aforementioned high-density optoelectronic integrated three-dimensional packaging structure is preferably manufactured using the manufacturing method of this embodiment, but of course it can also be manufactured using other manufacturing methods.

[0093] Afterwards, combined Figures 9 to 14 , the high-density optoelectronic integrated three-dimensional packaging structure provided by the present invention is specifically described, which includes the following steps:

[0094] S1: Provide a model frame, on which a sacrificial material layer is formed, and the resulting structure is as follows Figure 9 As shown;

[0095] S2: The electric chip and the electric connection component are spaced apart and fixed on the sacrificial material layer, wherein the functional surface of the electric chip is fixed toward the sacrificial material layer, and the electric chip includes a transimpedance amplifier chip. The obtained structure is as follows Figure 10 As shown;

[0096] S3: Wrap the electric chip and the electric connection components to form a plastic packaging material layer, and the resulting structure is as follows Figure 11 As shown;

[0097] S4: removing the sacrificial material layer, peeling off the mold frame to expose the functional surface of the electric chip, forming a rewiring layer on the side of the plastic packaging material layer that exposes the functional surface of the electric chip, the rewiring layer comprising a first main surface and a second main surface opposite to each other, a dielectric layer and a metal line located in the dielectric layer, the functional surface of the electric chip is in direct contact with the first main surface of the rewiring layer, and the obtained structure is as follows Figure 13 As shown;

[0098] S5: electrically connecting an optical chip to the second main surface of the rewiring layer, the optical chip including a photoelectric conversion element, the optical chip being electrically interconnected with the electrical chip via a metal line in the rewiring layer, so as to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal line in the rewiring layer;

[0099] S6: Fix the optical chip on the packaging substrate and form an electrical interconnection with the packaging substrate, and electrically connect the electrical connection component to the packaging substrate by wire bonding to realize signal extraction of the transimpedance amplifier chip. The obtained structure is as follows: Figure 14 shown.

[0100] Based on the above technical solution, a chip-first fan-out packaging method is adopted, and the electric chip is reshaped with its functional surface facing the model frame. Then, after peeling off the model frame, a rewiring layer is made through the welding pads on the functional surface of the electric chip, so that the welding pads of the electric chip directly contact the surface of the rewiring layer and electrically contact the metal circuits exposed on its surface, so that the electric chip and the optical chip are electrically interconnected through the rewiring layer, without the use of a bump process, which can meet the optoelectronic integration requirements in multi-channel signal application scenarios and also improve the packaging density.

[0101] It should be noted that the above steps are only distinguished for the convenience of description and are not a limitation to the actual process flow. In fact, the order of the steps can be adjusted or combined. For example, step S5 and step S6 can be performed simultaneously or sequentially.

[0102] like Figure 9 As shown, in step S1 , the sacrificial material layer 520 includes one of a carrier tape and a thermal release material to facilitate peeling of the carrier frame.

[0103] In another specific example, a thermo-releasing material can be applied to a mold frame by spin coating, and then in step S2, an electrical chip and an electrical connection component are arranged on the mold frame at intervals and fixed by curing the thermo-releasing material, wherein the electrical connection component includes a silicon bridge chip, a metal conductive column, a local silicon interconnect (LSI) or a similar component.

[0104] like Figure 10 As shown, as an example, step S2 includes arranging multiple transimpedance amplifier chips 3101, 3102, 3103, and 3104 and a silicon bridge chip 320 side by side and fixing them on a sacrificial material layer 520. The transimpedance amplifier chips 3101, 3102, 3103, and 3104 can be configured for multi-channel signal processing. In this embodiment, the silicon bridge chip 320 includes a conductive channel and a contact pad connected to one end of the conductive via.

[0105] like Figure 11 As shown, as an example, at step S3, the first main surface of the rewiring layer 20 is integrally plastic-encapsulated to form a plastic encapsulation material layer 33 that covers the electrical chip and the electrical connection components. The plastic encapsulation material layer 33 can be used to integrally cover the electrical chip and the electrical connection components by methods well known to those skilled in the art, including but not limited to, for example, compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating. The material of the plastic encapsulation material layer 33 includes one of polyimide, silicone and epoxy resin.

[0106] As an example, step S3 also includes: after forming the molding material layer 33, grinding or chemical mechanical polishing can be used on the upper surface of the molding material layer 33 to improve the surface flatness of the molding material layer 33, thereby improving the quality of the subsequently produced rewiring layer.

[0107] Specifically, if Figure 12As shown, step S4 includes: removing the sacrificial material layer 520, peeling off the mold frame 510 to expose the pads of the transimpedance amplifier chip and the contact pads of the silicon bridge chip; forming a rewiring layer 20 on the side of the plastic packaging material layer where the transimpedance amplifier chip is exposed, so that the pads of the transimpedance amplifier chip and the contact pads of the silicon bridge chip directly contact the surface of the rewiring layer.

[0108] like Figure 13 As shown, as an example, the rewiring layer 20 includes a dielectric layer 20b and a metal wiring layer 20a located within the dielectric layer; the material of the dielectric layer 20b includes one or more of the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the metal wiring layer 20a includes one or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium. The rewiring layer 20 can be formed by the following method, specifically including the following steps: forming a dielectric layer; forming through holes or grooves in the dielectric layer using a damascene process; filling the through holes or grooves with a metal material to form a metal wiring layer and contact plugs connecting adjacent metal wiring layers, wherein the metal wiring layer and the contact plugs are connected to form a metal circuit, wherein one end of the metal circuit is exposed on the first main surface of the rewiring layer, so that the electrical chip 30 is electrically interconnected with the optical chip 10 through the metal circuit within the rewiring layer. The Damascus process can be used to form a fine-pitch metal wiring layer, which can increase the density of metal lines, thereby achieving improved conduction and connection reliability. In addition, the fine-pitch metal wiring layer has a smaller surface roughness than other types of wiring, and can also reduce the signal transmission loss of high-speed electrical signals. In the application of an optical transceiver module with 16 receive and 16 transmit, four 4-channel transimpedance amplifier chips are arranged side by side on the rewiring layer, and the rewiring layer has 5 layers of metal wiring layers. It should be noted here that the material, number of layers and distribution morphology of the dielectric layer and the metal wiring layer can be set according to the specific situation of the chip and are not limited here.

[0109] In another specific example, step S4 further includes: prior to forming the rewiring layer, using photolithography technology, based on a pattern mask, forming a metallization pattern on the side of the plastic encapsulation material layer that exposes the functional surface of the electronic chip, such as the side that exposes the pads of the transimpedance amplifier chip, by electroplating, chemical plating, or a similar deposition method; then, removing the remaining etched polymer or residue, and depositing an underlying dielectric layer on the metallization pattern to form fine-pitch contacts, where the metallization pattern includes bonding pads or RDL pads. The rewiring layer 20 is formed on the metallization pattern to bond the metallization pattern to the metal lines within the rewiring layer.

[0110] Furthermore, if Figure 13As shown, an opening is further formed in the top dielectric layer of the rewiring layer to form a lower metallization (UBM) in the opening for bonding an interconnect structure, wherein the interconnect structure includes a ball grid array (BGA), a solder bump, a solder ball, a controlled collapse chip connection (C4) bump, or a similar connector. In this embodiment, the interconnect structure includes a solder bump 440 and a solder joint or solder layer formed by soldering it to the bonding pad 450 of the optical chip.

[0111] Specifically, the optical chip 10 includes a functional surface and a contact pad located on its functional surface. Step S5 includes: by bonding the interconnection structure to the contact pad of the optical chip, the optical chip 10 is electrically interconnected with the electrical chip 30 through the metal line of the rewiring layer, so as to allow the output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal line in the rewiring layer.

[0112] Step S6 includes: electrically connecting the electrical connection component to the package substrate 600 by wire bonding, so that the transimpedance amplifier chip 310 is electrically interconnected with the package substrate 600 through the metal lines in the rewiring layer.

[0113] As an example, Figure 14 As shown, the silicon bridge chip 320 is electrically connected to the package substrate 600 by wire bonding using the first lead 420 .

[0114] Furthermore, while or after the optical chip 10 is secured to the package substrate 600, the second lead 430 is used to electrically connect the optical chip 10 to the package substrate 600 via wire bonding. The optical chip includes a functional surface and a wire bonding pad 460 located on the functional surface. The wire bonding pad 460 of the optical chip is electrically connected to the package substrate 600 via wire bonding to receive external signals. In one example, a photoelectric conversion element is provided on the optical chip 10, and the photoelectric conversion element also includes a bonding pad provided on the functional surface. For example, the photoelectric conversion element includes a photodetector and a laser, and the photodetector is selected as a passive component.

[0115] As an example, the optical chip 10 further includes a photosensitive region and an optical coupler, and the photosensitive region is optically coupled to the optical fiber 150 inserted from the side of the optical chip through the optical coupler.

[0116] Step S6 further includes thinning the top surface of the molding material layer 33 by a planarization process to expose the top surface of the silicon bridge chip and improve the flatness of the obtained molding layer 330 , wherein the planarization process includes grinding or chemical mechanical polishing.

[0117] As an example, a bonding position is provided on the top of the silicon bridge chip. After the planarization process, at least the bonding position is exposed from the top surface of the plastic encapsulation layer 330 .

[0118] In summary, the present invention provides a high-density optoelectronic integrated three-dimensional packaging structure and a method for manufacturing the same. In the high-density optoelectronic integrated three-dimensional packaging structure of the present invention, an optical chip, a rewiring layer, and an electrical chip are stacked in sequence. The rewiring layer is used to electrically interconnect the optical chip and the electrical chip, allowing the electrical chip to directly electrically contact the rewiring layer. This eliminates the need for a silicon adapter plate and microbumps, effectively improving the reliability of optoelectronic chip integration, shortening the transmission path between the optoelectronic conversion element and the electrical chip, reducing losses, increasing transmission rate, and reducing package height. The method for manufacturing the high-density optoelectronic integrated three-dimensional packaging structure of the present invention eliminates the need for a bump process to achieve electrical contact between the chip pads and the interconnection structure, avoiding the impact of fine spacing between the pads of electrical chips such as transimpedance amplifier chips, which can affect reliability. The entire preparation process is simple and easy, reducing packaging costs, and thus laying the foundation for large-scale application of optoelectronic systems. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0119] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A high-density optoelectronic integrated three-dimensional packaging structure, characterized in that: include: A packaging substrate and an optical chip, a rewiring layer and an electrical chip stacked in sequence on the packaging substrate; The optical chip includes a photoelectric conversion element; The electrical chip includes a functional surface and is arranged to be in direct contact with the rewiring layer with its functional surface, the electrical chip includes a transimpedance amplifier chip, and the electrical chip is electrically interconnected with the optical chip via metal wiring in the rewiring layer to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal wiring in the rewiring layer; An electrical connection component is also provided on the rewiring layer, and the electrical connection component includes a silicon bridge chip, and the silicon bridge chip and the electrical chip are arranged side by side on the first main surface of the rewiring layer; the silicon bridge chip also includes a conductive through-hole and a contact pad connected to one end of the conductive through-hole, and the contact pad of the silicon bridge chip directly contacts the first main surface of the rewiring layer and is electrically coupled to the transimpedance amplifier chip through the metal line in the rewiring layer; the electrical connection component is spaced apart from the electrical chip and is electrically coupled to the transimpedance amplifier chip through the metal line in the rewiring layer, so as to realize signal extraction of the transimpedance amplifier chip, and a plastic packaging layer is further provided to cover the electrical connection component and the electrical chip; the silicon bridge chip is configured with a plurality of conductive through-holes that allow the multi-channel signals of the transimpedance amplifier chip to be output in parallel to the outside, and the height of the silicon bridge chip is greater than the height of the electrical chip so that the top of the silicon bridge chip is exposed and is electrically connected to the packaging substrate through wire bonding, so as to realize signal extraction of the transimpedance amplifier chip.

2. The three-dimensional packaging structure according to claim 1, wherein: The transimpedance amplifier chip is configured to process multi-channel signals. A functional surface of the transimpedance amplifier chip is provided with bonding pads having a bonding pad layout with a center-to-center spacing of no more than 85 μm.

3. The three-dimensional packaging structure according to claim 1, wherein: The bonding pads of the transimpedance amplifier chip directly contact the first main surface of the redistribution layer and are electrically interconnected with the photoelectric conversion element through metal lines and solder bumps in the redistribution layer, wherein the photoelectric conversion element includes a photodetector.

4. The three-dimensional packaging structure according to claim 1, wherein: The silicon bridge chip is further configured to supply power to the transimpedance amplifier chip.

5. The three-dimensional packaging structure according to claim 1, wherein: The optical chip includes a photosensitive area and an optical coupler. The photosensitive area is optically coupled to an optical fiber inserted from a side of the optical chip through the optical coupler.

6. A method for manufacturing a high-density optoelectronic integrated three-dimensional packaging structure, characterized in that: The following steps are involved: Providing a mold frame, wherein a sacrificial material layer is formed on the mold frame; Disposing an electrical chip and an electrical connection component at intervals and fixing them on the sacrificial material layer, wherein the functional surface of the electrical chip faces the sacrificial material layer, and the electrical chip includes a transimpedance amplifier chip; Covering the electric chip and the electric connection component to form a plastic packaging layer; Removing the sacrificial material layer, peeling off the mold frame to expose the functional surface of the electronic chip, and forming a redistribution layer on the side of the plastic encapsulation layer that exposes the functional surface of the electronic chip, wherein the redistribution layer includes a first main surface and a second main surface that are opposite to each other, a dielectric layer, and a metal circuit located within the dielectric layer, wherein the functional surface of the electronic chip is in direct contact with the first main surface of the redistribution layer; The electrical connection component includes a silicon bridge chip, and the manufacturing method further includes: electrically connecting the electrical chip to the silicon bridge chip through metal wiring in the redistribution layer by directly contacting a contact pad located at one end of the silicon bridge chip with the redistribution layer; Bonding an optical chip to the second main surface of the rewiring layer, the optical chip including a photoelectric conversion element, the optical chip being electrically interconnected with the electrical chip via metal wiring within the rewiring layer, so as to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal wiring within the rewiring layer; The optical chip is fixed on a packaging substrate and electrically interconnected with the packaging substrate. The electrical connection component is electrically connected to the packaging substrate by wire bonding to realize signal extraction of the transimpedance amplifier chip. The silicon bridge chip is configured with multiple conductive through-holes that allow the multi-channel signals of the transimpedance amplifier chip to be output in parallel to the outside. The height of the silicon bridge chip is greater than the height of the electrical chip so that the top of the silicon bridge chip is exposed and electrically connected to the packaging substrate by wire bonding to realize signal extraction of the transimpedance amplifier chip.

7. The production method according to claim 6, characterized in that: Also includes: Before forming the rewiring layer, a metallization pattern is formed on the side of the plastic encapsulation layer that exposes the functional surface of the electrical chip based on a graphic mask, wherein the transimpedance amplifier chip includes a solder pad located on its functional surface, and the rewiring layer is formed on the metallization pattern to connect the metal circuit in the rewiring layer.

8. The production method according to claim 6, characterized in that: The optical chip further includes a bonding pad on its functional surface. The manufacturing method further includes: electrically coupling the bonding pad of the optical chip to the packaging substrate by wire bonding to receive external signals.

9. An optical transceiver module, characterized in that: The optical transceiver module has a high-density optoelectronic integrated three-dimensional packaging structure as claimed in any one of claims 1 to 5.

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