Gate drive chip and control method thereof, storage medium and IPM

Abstract

The embodiment of the present application provides a gate driver chip and its control method, storage medium and IPM, which belongs to power semiconductor technology. The chip includes an input control module, and a first drive circuit and a second drive circuit respectively connected to the input control module; the input control module is used for PWM signals and current input switching signals, and when the current input switching signal is a large current signal, the second drive circuit is turned on, so that the second drive circuit and the first drive circuit form a parallel circuit structure, and drive the first target power element to be turned on or off based on the parallel circuit structure; or, drive the second target power element to be turned on or off based on the first drive circuit; wherein the rated value of the first target power element is greater than the rated value of the second target power element. The gate driver chip provided by the present application can realize the driving of various types of power elements, which can greatly shorten the development cycle of the gate driver chip and reduce the development cost.

Description

Technical Field

[0001] The embodiments of the present application relate to power semiconductor technology, and more specifically, to a gate drive chip and a control method thereof, a storage medium, and an IPM. Background Art

[0002] The gate driver chip (integrated circuit, IC) inside the IPM is a key circuit structure used to drive the power components on and off.

[0003] The best driving conditions for power components are usually achieved by optimizing the output current of the gate driver IC. Since the current gate driver IC has a certain output current specification, a single gate driver IC can only be used for one corresponding power component. In other words, manufacturers need to develop a corresponding gate driver IC for each power component, and as the number of IPM types with different ratings increases, the number of gate driver IC types will also increase proportionally. This will undoubtedly lead to a longer development time and higher development costs for gate driver chips. Summary of the invention

[0004] The embodiments of the present application provide a gate driver chip and a control method thereof, a storage medium and an IPM, which are used to at least solve the problem in the prior art that the gate driver chip can only be used for a single rated power component, resulting in a long development time or high cost.

[0005] According to a first aspect of an embodiment of the present application, a gate driver chip is provided, comprising an input control module, and a first driver circuit and a second driver circuit respectively connected to the input control module; wherein:

[0006] The input control module is used to receive a PWM signal and a current input switching signal, and when the current input switching signal is a large current signal, turn on the second drive circuit so that the second drive circuit and the first drive circuit form a parallel circuit structure, and transmit the PWM signal to the parallel circuit structure to drive the first target power element to be turned on or off based on the parallel circuit structure;

[0007] Alternatively, when the current input switching signal is a small current signal, the second drive circuit is turned off, and the PWM signal is transmitted to the first drive circuit to drive the second target power element to be turned on or off based on the first drive circuit; wherein the rated value of the first target power element is greater than the rated value of the second target power element.

[0008] In one embodiment, the gate driver chip further includes:

[0009] A pad, the pad is connected to the input control module, and can be connected to a power supply terminal VDD and / or a ground terminal VSS through a lead;

[0010] When the pad is connected to the power terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a large current signal, so that the input control module turns on the second drive circuit;

[0011] Alternatively, when the pad is not connected to the power terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a small current signal, so that the input control module turns off the second drive circuit.

[0012] In one embodiment, the input control module includes a switch combination module, and the switch combination module includes a plurality of switch elements;

[0013] The input end of the switch combination module is connected to the pad, and the output end thereof is connected to the second drive circuit, and is used to turn on the second drive circuit when the pad is connected to the power supply terminal VDD and / or the ground terminal VSS through a lead; or to turn off the second drive circuit when the pad is not connected to the power supply terminal VDD and / or the ground terminal VSS through a lead.

[0014] In one embodiment, the first driving circuit includes a first on circuit and a first off circuit;

[0015] The first conduction circuit includes a first NOT gate, a first PMOS transistor and a first resistor, wherein one end of the input terminal of the first NOT gate is connected to the input control module, the other end of the input terminal is connected to the ground terminal VSS, and the output end is connected to the gate of the first PMOS transistor; the source of the first PMOS transistor is connected to the power supply terminal VDD, and the drain of the first PMOS transistor is connected to the first resistor;

[0016] The first shutdown circuit includes a second NOT gate, a first NMOS tube and a second resistor, wherein one end of the input of the second NOT gate is connected to the input control module, the other end of the input is connected to the ground terminal VSS, and the output end is connected to the gate of the first NMOS tube; the source of the first NMOS tube is connected to the ground terminal VSS, and the drain is connected to the second resistor.

[0017] In one embodiment, the second driving circuit includes a second on-circuit and a second off-circuit;

[0018] The second conduction circuit includes a third NOT gate, a second PMOS tube and a third resistor, wherein one end of the input end of the third NOT gate is connected to the input control module, the other end of the input end is connected to the ground end VSS, and the output end is connected to the gate of the second PMOS tube; the source of the second PMOS tube is connected to the power supply end VDD, and the drain of the second PMOS tube is connected to the third resistor;

[0019] The second shutdown circuit includes a fourth NOT gate, a second NMOS transistor and a fourth resistor, wherein one end of the input end of the fourth NOT gate is connected to the input control module, the other end of the input end is connected to the ground terminal VSS, and the output end is connected to the gate of the second NMOS transistor; the source of the second NMOS transistor is connected to the ground terminal VSS, and the drain of the second NMOS transistor is connected to the fourth resistor;

[0020] Among them, when the current input switching signal is a large current signal, the input control module turns on the second conduction circuit, so that the second conduction circuit and the first conduction circuit form a parallel conduction circuit, so as to drive the conduction of the first target power element based on the parallel conduction circuit; or turns on the second shutdown circuit, so that the second shutdown circuit and the first shutdown circuit form a parallel shutdown circuit, so as to drive the shutdown of the first target power element based on the parallel shutdown circuit.

[0021] In one embodiment, the input control module includes a PWM signal transmission element, which is respectively connected to the second conduction circuit and the second shutdown circuit, for receiving the PWM signal and transmitting the PWM signal to the second conduction circuit or the second shutdown circuit when the second conduction circuit or the second shutdown circuit is turned on.

[0022] In one implementation, the pad is labeled as an Io_chg pad for current input switching.

[0023] According to a second aspect of an embodiment of the present application, a control method for a gate driver chip is provided, the method comprising:

[0024] The input control module receives a PWM signal and a current input switching signal, and when the current input switching signal is a large current signal, turns on the second drive circuit so that the second drive circuit and the first drive circuit form a parallel circuit structure, and transmits the PWM signal to the parallel circuit structure;

[0025] The parallel circuit structure drives the target power element to be turned on or off based on the PWM signal;

[0026] Alternatively, when the current input switching signal is a low current signal, the input control module turns off the second drive circuit and transmits the PWM signal to the first drive circuit;

[0027] The first drive circuit drives the target power element to be turned on or off based on the PWM signal.

[0028] According to a third aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the control method of the gate drive chip is implemented.

[0029] According to a fourth aspect of an embodiment of the present application, an intelligent power module IPM is provided, wherein the IPM includes the gate drive chip.

[0030] The gate drive chip and its control method, storage medium and IPM provided by the embodiments of the present application include an input control module, and a first drive circuit and a second drive circuit respectively connected to the input control module; wherein the input control module is used to receive a pulse width modulation PWM signal and a current input switching signal, and when the current input switching signal is a large current signal, turn on the second drive circuit so that the second drive circuit and the first drive circuit form a parallel circuit structure, and transmit the PWM signal to the parallel circuit structure to drive the first target power element to be turned on or off based on the parallel circuit structure; or, when the current input switching signal is a small current signal, turn off the second drive circuit, transmit the PWM signal to the first drive circuit, and drive the second target power element to be turned on or off based on the first drive circuit; wherein the rated value of the first target power element is greater than the rated value of the second target power element. In this process, the gate drive chip includes multiple groups of drive circuits. By utilizing the switching control of the input control module, the drive of large-rated power components and small-rated power components is realized when the multiple groups of drive circuits are combined into a parallel structure or not combined into a parallel structure, thereby realizing the optimal drive of multiple types of power components by using one type of gate drive chip, which can greatly shorten the development cycle of the gate drive chip and reduce the development cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the implementation methods in the embodiments of the present application or the related technologies, the following is a brief introduction to the drawings required for use in the embodiments or the related technology descriptions. Obviously, the drawings described below are some embodiments of the present application, and a person skilled in the art can also obtain other drawings based on these drawings.

[0032] Figure 1A possible circuit structure diagram of a gate drive chip provided in the related art;

[0033] Figure 2a One of the circuit structure diagrams of the gate drive chip provided in the embodiment of the present application;

[0034] Figure 2b The second circuit structure diagram of the gate drive chip provided in the embodiment of the present application;

[0035] Figure 3 The third circuit structure diagram of the gate drive chip provided in the embodiment of the present application;

[0036] Figure 4 The fourth circuit structure diagram of the gate drive chip provided in the embodiment of the present application;

[0037] Figure 5 A circuit timing diagram of a gate drive chip provided in an embodiment of the present application;

[0038] Figure 6 The fifth circuit structure diagram of the gate drive chip provided in the embodiment of the present application;

[0039] Figure 7 The sixth circuit structure diagram of the gate drive chip provided in the embodiment of the present application;

[0040] Figure 8 is a curve chart of the simulation results of the embodiment of the present application;

[0041] Fig. 9 A schematic diagram of the process flow of the gate drive chip provided in an embodiment of the present application;

[0042] Fig.10 A schematic diagram of the structure of the IPM provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, implementation mode and advantages of the present application clearer, the exemplary implementation mode of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0044] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0045] In addition, the terms "include" and "have" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such products or devices.

[0046] Intelligent Power Module (IPM) is commonly used in three-phase inverter circuits of household appliances (such as variable frequency air conditioners), industrial machines and automotive products. It is an advanced power switching device. IPM is usually composed of high-speed and low-power power components - Insulated Gate Bipolar Transistor (IGBT) and gate drive IC and other circuits.

[0047] The best driving condition of power components is usually achieved by optimizing the output current of gate driver IC. Therefore, different power components have different optimal output current of gate driver IC. Currently, gate driver IC has certain output current specification, and a single gate driver IC can only be applied to a corresponding power component. Figure 1 As shown, the gate drive IC is composed of NOT gate A1 and NOT gate A5, switch tube M3 & resistor R2 and switch tube M1 & resistor R3, wherein A1 receives PWM signal to drive M3 & R2, and drives IGBT to conduct by outputting high level signal corresponding to Io-, and A2 receives PWM signal to drive M1 & R3, and drives IGBT to turn off by outputting low level signal corresponding to Io+. It can be seen that this circuit structure can only be applied to the drive of the corresponding IGBT. If driving of IGBT with other rated values ​​is required, in order to ensure good driving effect, it is necessary to redevelop gate drive IC for IGBT with other rated values, for example, the size of the resistor needs to be changed, and each type of gate drive can only be applied to IGBT with one rated value, which leads to development time and high development cost.

[0048] Based on the above technical problems, the embodiments of the present application provide a gate driver chip and its control method, storage medium and IPM. On the basis of the prior art, in addition to the existing first driver circuit, an input control module and a second driver circuit are newly added to realize the technical solution that the gate driver chip can be applicable to a variety of power elements. Specifically, the input control module of the embodiment of the present application is used to receive a PWM signal and a current input switching signal, and when the current input switching signal is a large current signal, turn on the second driver circuit, so that the second driver circuit and the first driver circuit form a parallel circuit structure, and transmit the PWM signal to the parallel circuit structure to drive the first target power element to be turned on or off based on the parallel circuit structure; or, when the current input switching signal is a small current signal, turn off the second driver circuit, and transmit the PWM signal to the first driver circuit to drive the second target power element to be turned on or off based on the first driver circuit; wherein the rated value of the first target power element is greater than the rated value of the second target power element. In this process, by adding a new driving circuit inside the gate drive chip and utilizing the switching control of the input control module, the driving of the large-rated IGBT and the small-rated IGBT is realized when they are combined into a parallel structure or not. It can be seen that the present application uses one type of gate drive chip to realize the driving of multiple types of IGBTs, which can greatly shorten the development cycle of the gate drive chip and reduce the development cost.

[0049] The technical solution of the present application is described in detail below in conjunction with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0050] Please refer to Figure 2a , Figure 2a A circuit structure diagram of a gate drive chip 20 provided in an embodiment of the present application, the gate drive chip 20 includes an input control module 21, and a first drive circuit 22 and a second drive circuit 23 respectively connected to the input control module 21; wherein,

[0051] An input control module 21 is used to receive a PWM signal and a current input switching signal, and when the current input switching signal is a large current signal, turn on the second drive circuit 23 so that the second drive circuit 23 and the first drive circuit 22 form a parallel circuit structure, and transmit the PWM signal to the parallel circuit structure to drive the first target power element to be turned on or off based on the parallel circuit structure;

[0052] Alternatively, when the current input switching signal is a small current signal, the second drive circuit 23 is turned off and the PWM signal is transmitted to the first drive circuit 22 to drive the second target power element to be turned on or off based on the first drive circuit 22; wherein the rated value of the first target power element is greater than the rated value of the second target power element.

[0053] In this embodiment, the pulse width modulation wave (PWM) signal includes a three-phase signal, a U-phase signal, a V-phase signal and a W-phase signal. Combining the U-phase signal, the V-phase signal and the W-phase signal can realize the driving of each power element in the IPM.

[0054] In this embodiment, there may be one or more second drive circuits 23. Those skilled in the art may determine the number of second drive circuits in combination with actual applications, and specifically, may determine the number according to the rated value of the target power element. In this embodiment, the rated value is the rated current value.

[0055] In this embodiment, the current input switching signal can be an external chip signal or an internal chip signal. In order to meet the needs of IPM small packaging, there is no need to increase the external functional terminals of the IPM to transmit the current input switching signal. This embodiment uses an internal chip signal. Optionally, the internal chip signal is connected to the power supply terminal VDD and / or the ground terminal VSS by setting a pad on the gate drive chip and using the leads on the lead frame to serve as a trigger for the current input switching signal.

[0056] In this embodiment, the large current signal and the small current signal can be adaptively determined according to actual applications and existing technologies. For example, the large current signal or the small current signal can be determined according to the size of the optimal output current required by the target power element.

[0057] In one embodiment, in combination Figure 2b As shown, the gate driving chip 20 also includes:

[0058] A pad 24, which is connected to the input control module 21 and can be connected to a power supply terminal VDD and / or a ground terminal VSS through a lead;

[0059] When the pad 24 is connected to the power supply terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a large current signal, so that the input control module turns on the second drive circuit;

[0060] Alternatively, when the pad is not connected to the power terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a small current signal, so that the input control module turns off the second drive circuit.

[0061] Those skilled in the art can understand that a pad is a group of metal pins on a chip that can be used to connect other electronic components or printed circuit boards. In this embodiment, a pad is provided on the gate drive chip to be connected to a power supply terminal or a ground terminal through a lead wire, as an internal element for triggering a current input switching signal, without having to add a new transmission terminal to achieve the transmission of an external signal.

[0062] Optionally, in order to facilitate identification of the function of the pad structure, based on the various connection modes of the gate driving chip 20, the pad 24 in this embodiment is marked as an Io_chg pad for current input switching, hereinafter referred to as an Io_chg terminal.

[0063] In one embodiment, in combination Figure 3 and Figure 4 As shown, Figure 3 and Figure 4 Schematic diagrams of circuit structures when driving the first target power element and the second target power element respectively.

[0064] like Figure 3 and Figure 4 As shown, the first driving circuit 22 in this embodiment includes a first conduction circuit 221 and a first shutdown circuit 222; the first conduction circuit 221 includes a first NOT gate A1, a first PMOS tube M3 and a first resistor R2, one end of the input end of the first NOT gate A1 is connected to the input control module 21, the other end of the input end is connected to the ground terminal VSS, and the output end is connected to the gate of the first PMOS tube M3; the source of the first PMOS tube M3 is connected to the power supply terminal VDD, and the drain is connected to the first resistor R2; the first shutdown circuit 222 includes a second NOT gate A5, a first NMOS tube M1 and a second resistor R3, one end of the input end of the second NOT gate A5 is connected to the input control module 21, the other end of the input end is connected to the ground terminal VSS, and the output end is connected to the gate of the first NMOS tube M1; the source of the first NMOS tube M1 is connected to the ground terminal VSS, and the drain is connected to the second resistor R3.

[0065] In this embodiment, when the second driving circuit handles the shutdown situation, that is, when Io_chg is not connected to VDD and / or VSS through the lead, the first driving circuit is used to complete the Io transmission, which can be used to drive the power element X1 (second target power element) with a small rating. A1 and A2 output corresponding level signals to M3 and M1 respectively according to the PWM signal to realize the conduction of M3 or M1, and then realize the conduction or shutdown of the first target power element through M3&R2 or M1&R3.

[0066] Continue to refer to Figure 3 and Figure 4, the second driving circuit 23 includes a second conduction circuit 231 and a second shutdown circuit 232; the second conduction circuit 231 includes a third NOT gate A3, a second PMOS tube M4 and a third resistor R1, one end of the input end of the third NOT gate A3 is connected to the input control module 21, the other end of its input end is connected to the ground terminal VSS, and its output end is connected to the gate of the second PMOS tube M4; the source of the second PMOS tube M4 is connected to the power supply terminal VDD, and its drain is connected to the third resistor R1; the second shutdown circuit 232 includes a fourth NOT gate A4, a second NMOS tube M2 and a fourth resistor R4, one end of the input end of the fourth NOT gate A4 is connected to the input control module 21, the other end of its input end is connected to the ground terminal VSS, and its output end is connected to the gate of the second NMOS tube M2; the source of the second NMOS tube M2 is connected to the ground terminal VSS, and its drain is connected to the fourth resistor R4;

[0067] Among them, when the current input switching signal is a large current signal, the input control module 21 turns on the second conduction circuit 231, so that the second conduction circuit 231 and the first conduction circuit 221 form a parallel conduction circuit, so as to drive the first target power element X2 to be turned on based on the parallel conduction circuit; or turns on the second shutdown circuit 232, so that the second shutdown circuit 232 and the first conduction circuit 222 form a parallel shutdown circuit, so as to drive the first target power element X2 to be turned off based on the parallel shutdown circuit.

[0068] In this embodiment, the current input switching signal is determined by whether the Io_chg terminal is connected to VDD and / or VSS through a lead, wherein when the Io_chg terminal is in an open circuit state, that is, not connected to VDD and / or VSS through a lead, it corresponds to a small current signal, and the power element X1 is driven by the first drive circuit; when the Io_chg terminal is in a short circuit state, that is, connected to VDD and / or VSS through a lead, it corresponds to a large current signal, and the power element X2 is driven by the parallel structure between the first drive circuit and the second drive circuit.

[0069] In other words, based on the gate drive circuit having a combination of (M3+R2) and (M1+R3) and a combination of (M4+R1) and (M2+R4), in which impedance adjustment has been performed to drive the power element in the best manner, the terminal marked as Io_chg is in an open state or by connecting to Vss and / or Vdd, it is possible to drive the power element by switching two or more of the following: only using the circuit block of (M3+R2) and (M1+R3) to act, or combining (M4+R1) and (M2+R4) to work in parallel. Here, the Io_chg terminal can be realized by connecting to VDD or VSS through a lead on the internal lead frame of the IPM without increasing the external functional terminal of the IPM, and without increasing other hardware structures.

[0070] exist Figure 3 In order to keep the Io_Chg part in an open circuit state to drive the IGBT (X1) with a small rated current, only the driving circuit parts of M3+R2 and M1+R3 adjusted to the optimal gate current (horizontal arrow) work. Figure 4 When the IGBT is changed to a type (X2) with a rated current greater than X1 as shown in the figure, the optimum gate current also increases. In this case, by connecting the Io_Chg terminal to VDD and / or VSS as Figure 3 As shown, in addition to the M3+R2 and M1+R3 driving circuits, the M4+R1 and M2+R4 driving circuits also work simultaneously, which can increase the gate current so that X2 can be set at the optimal gate current. It should be noted that those skilled in the art can make an adaptive determination in the planning stage whether the Io_Chg part is connected to VDD or VSS or whether it is connected to VDD and VSS at the same time in combination with actual applications.

[0071] In the above process, combined with Figure 5 As shown in the circuit timing diagram, the first half of the dotted line in the timing diagram shows Figure 3 The working status of the dashed line is shown in the second half. Figure 4 When the Io_Chg terminal is open (not connected to VDD or VSS through a lead), the gate drive MOSFETs M4 and M2 are fixedly turned off for the A3 and A4 signals. Therefore, the current supplied to the IGBT gate is Io-(L) and Io+(L). On the other hand, by connecting Io_Chg to VDD or VSS, the PWM signal is transmitted to A3 and A4, and the gate drive MOSFETs M4 and M2 operate synchronously with this, indicating that the current supplied to the IGBT gate increases to Io-(H) and Io+(H).

[0072] Further, in order to improve the on and off efficiency of the second driving circuit, the input control module 21 in this embodiment includes a switch combination module, and the switch combination module includes a plurality of switch elements;

[0073] The input end of the switch combination module is connected to the pad, and the output end thereof is connected to the second drive circuit, and is used to turn on the second drive circuit when the pad is connected to the power supply terminal VDD and / or the ground terminal VSS through a lead; or to turn off the second drive circuit when the pad is not connected to the power supply terminal VDD and / or the ground terminal VSS through a lead.

[0074] Combination Figure 6 and Figure 7 As shown, Figure 6 and Figure 7Possible situations where the pad is connected to VDD and / or VSS through a lead and where it is not connected to VDD and / or VSS are shown respectively, taking the design that the pad is connected to the power supply VDD through a lead as an example. Figure 6 The c part in corresponds to the connection relationship between the switch combination module and A3 and A4. Figure 7 The d part in corresponds to the connection relationship between the switch combination and A10 and A11 (where A10 corresponds to A3 and A11 corresponds to A4). Figure 6 and Figure 7 The component numbers appearing in Figure 3 and Figure 4 Compare the component numbers in the table 1 as shown below:

[0075] Table 1

[0076]

[0077] Table 1 shows Figure 6 and Figure 7 The circuit corresponds to Figure 3 or Figure 4 The component name in . Figure 6 and Figure 7 In the embodiment, the first driving circuit 22 may be part e, and the structure of the input control module 21 and the second driving circuit 23 may include part c / d and M3, M4, R3, R4 (M13, M14, R11, R12).

[0078] like Figure 6 As shown, the Io_chg terminal is connected to the power supply terminal VDD, and the c part can work by connecting the Io_chg terminal to Vdd. The switch elements M5, M6, M7, M8, and M10 (i.e., the switch combination module) of the c part transmit the PWM signal to the M3 and M4 switch elements, and work synchronously with the M1 and M2 in the first drive circuit, as a parallel circuit, to provide the drive current to the gate part gate1 of the first target power element. Figure 7 As shown, when the Io_chg terminal is set to an open circuit, that is, when the power supply terminal VDD is in an open circuit state, the resistor R13 (corresponding to Figure 5 R5 in the d part) is fixed to VSS, and the switch elements M15, M16, M17, M18, M20 in the d part (corresponding to Figure 5 M5, M6, M7, M8, M10) in the circuit are closed, and the PWM signal is not transmitted to M13, M14 (corresponding to Figure 5 The switch elements M3, M4) in the embodiment of FIG. 1 are used, and only the first drive circuit works, and the drive current is only from M11, M12 (corresponding to Figure 5 M1, M2) in the circuit are supplied to the gate.

[0079] Furthermore, the input control module 21 includes a PWM signal transmission element, which is respectively connected to the second on-circuit and the second off-circuit, for receiving a PWM signal and transmitting the PWM signal to the second on-circuit or the second off-circuit when the second on-circuit or the second off-circuit is on.

[0080] In the related art, since there is only one set of drive circuits in the gate drive chip, the drive circuit can directly receive the PWM signal and use the PWM signal to drive the power element. In this embodiment, multiple sets of drive circuits are set inside the gate drive chip, and the composition of the parallel structure between the multiple sets of drive circuits is determined according to the corresponding power elements, and the PWM signal is transmitted to other drive circuits other than the existing drive circuit. The input control module 21 of this embodiment can be provided with a PWM signal transmission element so that the PWM signal can be transmitted to the second drive circuit.

[0081] Continue to combine Figure 6 and Figure 7 As shown, in order to verify the effect of the technical solution provided in the embodiment of the present application, a simulation verification is performed, and the simulation results are as follows Figure 8 As shown, it can be seen that the VDD short circuit Figure 6 The corresponding A state is provided to the load ( Figure 6 R18&C1 or Figure 7 The current control of R17 & C2 in the open circuit state Figure 7 The corresponding B states are different, so that the same gate driver IC can achieve optimal driving of IGBTs with various ratings. It can be understood that the current amount sets the impedances of M1-M4 and R1-R4 according to the conditions of the power components.

[0082] In summary, the technical solution provided by the embodiment of the present application can produce multiple rated IPMs through the same gate driver IC by equipping the gate driver IC with the output current switching function corresponding to each power element and selecting the output current of the gate driver IC when manufacturing the IPM. It can provide a universal IC for multiple IPMs without increasing the number of gate driver ICs developed (without increasing the development cycle and development resources) to reduce the risk of surplus or shortage during procurement. In addition, the technical solution of the present application is particularly applicable when the market requires multiple rated currents in the development lineup of products (such as IPMs) with the same package and pin arrangement.

[0083] Please refer to Fig. 9 , Fig. 9 A schematic diagram of a control method for a gate drive chip is provided in accordance with an embodiment of the present application. The method comprises the following steps:

[0084] Step S901: the input control module receives a PWM signal and a current input switching signal, and when the current input switching signal is a large current signal, turns on the second drive circuit so that the second drive circuit and the first drive circuit form a parallel circuit structure, and transmits the PWM signal to the parallel circuit structure;

[0085] Step S902: The parallel circuit structure drives the target power element to be turned on or off based on the PWM signal;

[0086] Alternatively, in step S903, when the current input switching signal is a low current signal, the input control module turns off the second drive circuit and transmits the PWM signal to the first drive circuit;

[0087] Step S904: The first driving circuit drives the target power element to be turned on or off based on the PWM signal.

[0088] Please refer to Fig.10 , Fig.10 An intelligent power module IPM100 is provided in an embodiment of the present application. IPM100 includes a gate drive chip. The gate drive chip can be a gate drive chip 20 of any implementation method provided in the above embodiments. The gate drive chip and the target power element 30 are used to drive the target power element 30. The target power element 30 includes a first target power element or a second target power element.

[0089] Optionally, the gate drive chip 20 includes a pad, which is connected to the input control module and can be connected to the power supply terminal VDD and / or the ground terminal VSS through a lead; when the pad is connected to the power supply terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a large current signal, so that the input control module turns on the second drive circuit; or, when the pad is not connected to the power supply terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a small current signal, so that the input control module turns off the second drive circuit.

[0090] In the above technical solution, the IPM that needs to be developed can be realized without increasing the number of external functional terminals.

[0091] The present application also provides a computer-readable storage medium, which may include: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes. Specifically, the computer-readable storage medium stores program instructions, and when the computer execution instructions are executed by the processor, the control method of the gate drive chip in the above embodiment is used.

[0092] The present application also provides a program product, which includes an execution instruction, which is stored in a readable storage medium. At least one control module of the display device can read the execution instruction from the readable storage medium, and at least one control module executes the execution instruction so that the display device implements the control method of the gate drive chip provided by the above various embodiments.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0094] For ease of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are intended to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A gate driver chip, characterized in that: It includes an input control module, and a first drive circuit and a second drive circuit respectively connected to the input control module; wherein, The input control module is used to receive a pulse width modulation (PWM) signal and a current input switching signal, and when the current input switching signal is a large current signal, turn on the second drive circuit so that the second drive circuit and the first drive circuit form a parallel circuit structure, and transmit the PWM signal to the parallel circuit structure to drive the first target power element to be turned on or off based on the parallel circuit structure; Alternatively, when the current input switching signal is a low current signal, the second drive circuit is turned off, and the PWM signal is transmitted to the first drive circuit, so as to drive the second target power element to be turned on or off based on the first drive circuit; wherein the rated value of the first target power element is greater than the rated value of the second target power element; A pad, the pad is connected to the input control module, and can be connected to a power supply terminal VDD and / or a ground terminal VSS through a lead; When the pad is connected to the power terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a large current signal, so that the input control module turns on the second drive circuit; Alternatively, when the pad is not connected to the power terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a small current signal, so that the input control module turns off the second drive circuit; The input control module includes a PWM signal transmission element, a switch combination module and a ninth PMOS tube, and the switch combination module includes a fifth NMOS tube, a sixth PMOS tube, a seventh NMOS tube, an eighth PMOS tube, and a tenth NMOS tube; The gate of the ninth PMOS tube is connected to the pad, the source of the ninth PMOS tube is connected to the power supply terminal VDD, and the drain of the ninth PMOS tube is connected to the second drive circuit; the gate of the fifth NMOS tube is connected to the pad, one of the source and the drain of the fifth NMOS tube is connected to the second drive circuit, and the other is connected to the output end of the first NOT gate, one end of the input end of the first NOT gate is connected to the PWM signal transmission element, and the other end of the input end is grounded; the gate of the sixth PMOS tube is connected to the output end of the third NOT gate, one of the source and the drain of the sixth PMOS tube is connected to the second drive circuit, and the other is connected to the output end of the first NOT gate, and the input end of the third NOT gate is connected to the PWM signal transmission element. one end of the input end is connected to the pad, and the other end of the input end is grounded; the gate of the seventh NMOS tube is connected to the pad, one of the source and the drain of the seventh NMOS tube is connected to the second drive circuit, and the other is connected to the output end of the first NOT gate; the gate of the eighth PMOS tube is connected to the output end of the fourth NOT gate, one end of the input end of the fourth NOT gate is connected to the pad, and the other end of the input end is grounded, one of the source and the drain of the eighth PMOS tube is connected to the second drive circuit, and the other is connected to the output end of the first NOT gate; the gate of the tenth NMOS tube is connected to the output end of the fourth NOT gate, the drain of the tenth NMOS tube is connected to the second drive circuit, and the source of the tenth NMOS tube is grounded; The first driving circuit includes a first on circuit and a first off circuit; The first conduction circuit includes the first NOT gate, the first PMOS tube and the first resistor, wherein one end of the input terminal of the first NOT gate is connected to the input control module, the other end of the input terminal is connected to the ground terminal VSS, and the output end is connected to the gate of the first PMOS tube; the source of the first PMOS tube is connected to the power supply terminal VDD, and the drain of the first PMOS tube is connected to the first resistor; The first shutdown circuit includes a second NOT gate, a first NMOS tube and a second resistor, wherein one end of the input of the second NOT gate is connected to the input control module, the other end of the input is connected to the ground terminal VSS, and the output end is connected to the gate of the first NMOS tube; the source of the first NMOS tube is connected to the ground terminal VSS, and the drain is connected to the second resistor.

2. The gate driver chip according to claim 1, characterized in that: The input end of the switch combination module is connected to the pad, and the output end thereof is connected to the second drive circuit, and is used to turn on the second drive circuit when the pad is connected to the power supply terminal VDD and / or the ground terminal VSS through a lead; or to turn off the second drive circuit when the pad is not connected to the power supply terminal VDD and / or the ground terminal VSS through a lead.

3. The gate driver chip according to claim 1, characterized in that: The second driving circuit includes a second on-circuit and a second off-circuit; The second conduction circuit includes a third NOT gate, a second PMOS tube and a third resistor, wherein one end of the input end of the third NOT gate is connected to the input control module, the other end of the input end is connected to the ground end VSS, and the output end is connected to the gate of the second PMOS tube; the source of the second PMOS tube is connected to the power supply end VDD, and the drain of the second PMOS tube is connected to the third resistor; The second shutdown circuit includes a fourth NOT gate, a second NMOS transistor and a fourth resistor, wherein one end of the input end of the fourth NOT gate is connected to the input control module, the other end of the input end is connected to the ground terminal VSS, and the output end is connected to the gate of the second NMOS transistor; the source of the second NMOS transistor is connected to the ground terminal VSS, and the drain of the second NMOS transistor is connected to the fourth resistor; Among them, when the current input switching signal is a large current signal, the input control module turns on the second conduction circuit, so that the second conduction circuit and the first conduction circuit form a parallel conduction circuit, so as to drive the conduction of the first target power element based on the parallel conduction circuit; or turns on the second shutdown circuit, so that the second shutdown circuit and the first shutdown circuit form a parallel shutdown circuit, so as to drive the shutdown of the first target power element based on the parallel shutdown circuit.

4. The gate driving chip according to claim 3, characterized in that: The PWM signal transmission element is respectively connected to the second conduction circuit and the second shutdown circuit for receiving the PWM signal and transmitting the PWM signal to the second conduction circuit or the second shutdown circuit when the second conduction circuit or the second shutdown circuit is turned on.

5. The gate driver chip according to claim 1, characterized in that: The pad is labeled as Io_chg pad for current input switching.

6. A control method for a gate drive chip, characterized in that: The method comprises: The input control module receives a PWM signal and a current input switching signal, and when the current input switching signal is a large current signal, turns on the second drive circuit so that the second drive circuit and the first drive circuit form a parallel circuit structure, and transmits the PWM signal to the parallel circuit structure; The parallel circuit structure drives the target power element to be turned on or off based on the PWM signal; Alternatively, when the current input switching signal is a low current signal, the input control module turns off the second drive circuit and transmits the PWM signal to the first drive circuit; The first driving circuit drives the target power element to be turned on or off based on the PWM signal; The pad is connected to a power supply terminal VDD and / or a ground terminal VSS through a lead. When the pad is connected to the power supply terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a large current signal, so that the input control module turns on the second drive circuit; Alternatively, when the pad is not connected to the power terminal VDD and / or the ground terminal VSS through a lead, the trigger current input switching signal is a small current signal, so that the input control module turns off the second drive circuit; The input control module includes a PWM signal transmission element, a switch combination module and a ninth PMOS tube, and the switch combination module includes a fifth NMOS tube, a sixth PMOS tube, a seventh NMOS tube, an eighth PMOS tube, and a tenth NMOS tube; The gate of the ninth PMOS tube is connected to the pad, the source of the ninth PMOS tube is connected to the power supply terminal VDD, and the drain of the ninth PMOS tube is connected to the second drive circuit; the gate of the fifth NMOS tube is connected to the pad, one of the source and the drain of the fifth NMOS tube is connected to the second drive circuit, and the other is connected to the output end of the first NOT gate, one end of the input end of the first NOT gate is connected to the PWM signal transmission element, and the other end of the input end is grounded; the gate of the sixth PMOS tube is connected to the output end of the third NOT gate, one of the source and the drain of the sixth PMOS tube is connected to the second drive circuit, and the other is connected to the output end of the first NOT gate, and the input end of the third NOT gate is connected to the PWM signal transmission element. one end of the input end is connected to the pad, and the other end of the input end is grounded; the gate of the seventh NMOS tube is connected to the pad, one of the source and the drain of the seventh NMOS tube is connected to the second drive circuit, and the other is connected to the output end of the first NOT gate; the gate of the eighth PMOS tube is connected to the output end of the fourth NOT gate, one end of the input end of the fourth NOT gate is connected to the pad, and the other end of the input end is grounded, one of the source and the drain of the eighth PMOS tube is connected to the second drive circuit, and the other is connected to the output end of the first NOT gate; the gate of the tenth NMOS tube is connected to the output end of the fourth NOT gate, the drain of the tenth NMOS tube is connected to the second drive circuit, and the source of the tenth NMOS tube is grounded; The first driving circuit includes a first on circuit and a first off circuit; The first conduction circuit includes the first NOT gate, the first PMOS tube and the first resistor, wherein one end of the input terminal of the first NOT gate is connected to the input control module, the other end of the input terminal is connected to the ground terminal VSS, and the output end is connected to the gate of the first PMOS tube; the source of the first PMOS tube is connected to the power supply terminal VDD, and the drain of the first PMOS tube is connected to the first resistor; The first shutdown circuit includes a second NOT gate, a first NMOS tube and a second resistor, wherein one end of the input of the second NOT gate is connected to the input control module, the other end of the input is connected to the ground terminal VSS, and the output end is connected to the gate of the first NMOS tube; the source of the first NMOS tube is connected to the ground terminal VSS, and the drain is connected to the second resistor.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by the processor, the gate drive chip control method of claim 6 is implemented.

8. An intelligent power module IPM, characterized in that: The IPM includes the gate driving chip as described in any one of claims 1-5.

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