Efficient rank switching in multi-rank memory controller

Abstract

A data processor includes a hierarchical buffer, a command queue, a picker, and an arbiter. The hierarchical buffer receives and stores a first memory access request. The command queue stores second memory access requests, each second memory access request indicating one of a plurality of memory ranks of a memory system. The picker selects among the first memory access requests in the hierarchical buffer and provides the selected first memory access request among the first memory access requests to the command queue. The arbiter selects among the second memory access requests from the command queue based at least on a preference for access to a current memory rank of the memory system. The picker selects access to the current memory rank among the first memory access requests in the hierarchical buffer and provides the selected first memory access request among the first memory access requests to the command queue.

Description

Background Art

[0001] Computer systems typically use inexpensive and high-density dynamic random access memory (DRAM) chips as main memory. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards published by the Joint Electron Device Engineering Council (JEDEC). DDR DRAM offers both high performance and low power operation, and DRAM manufacturers have offered DDR DRAM that operates at increasingly faster clock speeds.

[0002] Modern DDR memory controllers maintain queues to store pending memory access requests, allowing these memory controllers to pick up pending memory access requests out of order to improve efficiency. For example, a memory controller can retrieve multiple memory access requests for the same row in a given rank of memory from a queue out of order and issue the multiple memory access requests to the memory system continuously to avoid the overhead of precharging the current row and activating another row.

[0003] Higher performance DDR memory systems provide multiple memory ranks connected to a single memory channel and share most of the address, data and control signals. These memory systems generate complex timing constraints and can reduce memory bus efficiency if the memory controller frequently switches between memory ranks. However, the number of memory ranks in high performance computing systems continues to grow. For example, a DDR memory organized into one or more load reduced dual in-line memory modules (LRDIMMs) may have four physical chip selects / physical memory ranks, and each chip select / physical memory rank may have eight logical memory ranks in a three-dimensional stacked (3DS) package. In addition, over time, DDR memories have been specified to run using faster and faster memory clock signals. However, with these faster memory clock signals, certain timing parameters (e.g., minimum write to read timing) have increased proportionally, which reduces the efficiency of the memory controller using known memory controllers. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An accelerated processing unit (APU) and a memory system known in the prior art are shown in block diagram form;

[0005] FIG2 shows in block diagram form a memory controller known in the prior art;

[0006] Figure 3 A block diagram is shown that can be used according to some embodiments Figure 1 The memory controller in the APU;

[0007] Figure 4shows a timing diagram of components illustrating write to read turnaround time; and

[0008] FIG5 illustrates a set of timelines for memory accesses that may be selected by a memory controller known in the prior art;

[0009] Figure 6 According to some embodiments, Figure 3 A block diagram of a portion of a memory controller;

[0010] Figure 7 According to some embodiments, Figure 6 A timeline of memory accesses selected by an arbiter; and

[0011] Figure 8 is a flow diagram of a technique for selecting accesses from a multi-storage column system according to some embodiments.

[0012] In the following description, the same reference numerals are used in different drawings to indicate similar or identical items. Unless otherwise specified, the word "couple" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also means an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0013] A data processor includes a hierarchical buffer, a command queue, a picker, and an arbiter. The hierarchical buffer receives and stores a first memory access request. The command queue stores second memory access requests, each second memory access request indicating one of a plurality of memory ranks of a memory system. The picker selects among the first memory access requests in the hierarchical buffer and provides the selected first memory access request among the first memory access requests to the command queue. The arbiter selects among the second memory access requests from the command queue based at least on a preference for access to a current memory rank of the memory system. The picker selects access to the current memory rank among the first memory access requests in the hierarchical buffer and provides the selected first memory access request among the first memory access requests to the command queue.

[0014] The data processor includes a command queue and an arbiter. The command queue receives and stores decoded memory commands, wherein each decoded memory command includes information indicating a type and a memory rank, wherein the type indicates one of a read and a write. The arbiter is coupled to the command queue and is configured to select among the decoded memory commands from the command queue based on a plurality of criteria to provide to the memory channel. The arbiter is operable to determine whether the arbiter is nearing the end of a write access burst, and if so, to continue the write access burst to the current memory rank for a predetermined number of times before starting a read burst.

[0015] A method for a memory controller to select memory access requests to be provided to a memory channel having a plurality of memory ranks includes initiating a write access burst. Performing a write access to a current memory rank. Determining whether the memory controller is near the end of the write access burst. If the memory controller is not near the end of the write access burst, selectively switching the current memory rank, and repeatedly performing the write access to the current memory rank and determining whether the memory controller is near the end of the write access burst. If the memory controller is near the end of the write access burst, continuing the write access burst to the current memory rank for a predetermined number of times, waiting for a write-to-read turnaround time, and starting a read burst when any read access meets a timing condition.

[0016] Figure 1 An accelerated processing unit (APU) 100 and a memory system 130, known in the art, are shown in block diagram form. The APU 100 is an integrated circuit data processor suitable for use as a host processor in a data processing system and generally includes a central processing unit (CPU) core complex 110, a graphics core 120, a set of display engines 122, a memory management hub 124, a data structure 125, a set of peripheral controllers 160, a set of peripheral bus controllers 170, and a system management unit (SMU) 180.

[0017] The CPU core complex 110 includes a CPU core 112 and a CPU core 114. In this example, the CPU core complex 110 includes two CPU cores, but in other embodiments, the CPU core complex 110 may include any number of CPU cores. Each of the CPU cores 112 and 114 is bidirectionally connected to a system management network (SMN) (which forms a control structure) and a data structure 125, and can provide memory access requests to the data structure 125. Each of the CPU cores 112 and 114 can be a unitary core, or can also be a core complex with two or more unitary cores that share certain resources such as cache.

[0018] The graphics core 120 is a high-performance graphics processing unit (GPU) that can perform graphics operations such as vertex processing, fragment processing, shading, texture blending, etc. in a highly integrated and parallel manner. The graphics core 120 is bidirectionally connected to the SMN and the data structure 125, and can provide memory access requests to the data structure 125. In this regard, the APU 100 may support a unified memory architecture in which the CPU core complex 110 and the graphics core 120 share the same memory space, or a memory architecture in which the CPU core complex 110 and the graphics core 120 share a portion of the memory space while the graphics core 120 also uses a private graphics memory that the CPU core complex 110 cannot access.

[0019] The display engine 122 renders and rasterizes objects generated by the graphics core 120 for display on the monitor. The graphics core 120 and the display engine 122 are bidirectionally connected to a common memory management hub 124 for unified translation to the appropriate addresses in the memory system 130, and the memory management hub 124 is bidirectionally connected to a data structure 125 for generating such memory accesses and receiving read data returned from the memory system.

[0020] The data structure 125 includes a crossbar switch for routing memory access requests and memory responses between any memory accessing agents and the memory controller 140. The data structure also includes a system memory map defined by the basic input / output system (BIOS) for determining the destination of memory accesses based on the system configuration, and a buffer for each virtual connection.

[0021] Peripheral controllers 160 include a Universal Serial Bus (USB) controller 162 and a Serial Advanced Technology Attachment (SATA) interface controller 164, each of which is bidirectionally connected to a system hub 166 and the SMN bus. These two controllers are merely examples of peripheral controllers that may be used with APU 100.

[0022] The peripheral bus controller 170 includes a system controller or "South Bridge" (SB) 172 and a peripheral component interconnect express (PCIe) controller 174, each of which is bidirectionally connected to an input / output (I / O) hub 176 and the SMN bus. The I / O hub 176 is also bidirectionally connected to the system hub 166 and the data structure 125. Thus, for example, the CPU core can program registers in the USB controller 162, the SATA interface controller 164, the SB 172, or the PCIe controller 174 through accesses routed through the I / O hub 176 via the data structure 125. The software and firmware of the APU 100 are stored in a system data drive or system BIOS memory (not shown), which can be any of a variety of non-volatile memory types, such as read-only memory (ROM), flash electrically erasable programmable ROM (EEPROM), etc. Typically, the BIOS memory is accessed through the PCIe bus, and the system data drive is through the SATA interface.

[0023] The SMU 180 is a local controller that controls the operation of resources on the APU 100 and synchronizes communications between these resources. The SMU 180 manages the power-up sequencing of the various processors on the APU 100 and controls a number of off-chip devices via reset, enable, and other signals. The SMU 180 includes one or more clock sources (not shown), such as a phase-locked loop (PLL), to provide clock signals to each component of the APU 100. The SMU 180 also manages the power of the various processors and other functional blocks, and may receive measured power consumption values ​​from the CPU cores 112 and 114 and the graphics core 120 to determine the appropriate power state.

[0024] In this embodiment, the memory controller 140 and its associated physical interfaces (PHYs) 151 and 152 are integrated with the APU 100. The memory controller 140 includes memory channels 141 and 142 and a power engine 149. The memory channel 141 includes a host interface 145, a memory channel controller 143, and a physical interface 147. The host interface 145 connects the memory channel controller 143 bidirectionally to the data structure 125 via a serial presence detection link (SDP). The physical interface 147 connects the memory channel controller 143 bidirectionally to the PHY 151 and complies with the DDR PHY interface (DFI) specification. The memory channel 142 includes a host interface 146, a memory channel controller 144, and a physical interface 148. The host interface 146 connects the memory channel controller 144 bidirectionally to the data structure 125 via another SDP. The physical interface 148 connects the memory channel controller 144 bidirectionally to the PHY 152 and complies with the DFI specification. Power engine 149 is bidirectionally connected to SMU 180 via the SMN bus, to PHY 151 and PHY 152 via APB, and also bidirectionally connected to memory channel controllers 143 and 144. PHY 151 has a bidirectional connection to memory channel 131. PHY 152 has a bidirectional connection to memory channel 133.

[0025] Memory controller 140 is an instantiation of a memory controller having two memory channel controllers, and uses a shared power engine 149 to control the operation of both memory channel controller 143 and memory channel controller 144 in a manner that will be further described below. Each of memory channels 141 and 142 can be connected to prior art DDR memories, such as fifth generation DDR (DDR5), fourth generation DDR (DDR4), low power DDR4 (LPDDR4), fifth generation graphics DDR (GDDR5), and high bandwidth memory (HBM), and can be adapted to future memory technologies. These memories provide high bus bandwidth and high-speed operation. At the same time, they also provide low power modes to save power for battery-powered applications such as laptops, and also provide built-in thermal monitoring.

[0026] Memory system 130 includes memory channel 131 and memory channel 133. Memory channel 131 includes a set of dual inline memory modules (DIMMs) connected to DDRx bus 132, including representative DIMMs 134, 136, and 138, which correspond to separate memory ranks in this example. Similarly, memory channel 133 includes a set of DIMMs connected to DDRx bus 129, including representative DIMMs 135, 137, and 139.

[0027] The APU 100 operates as the central processing unit (CPU) of the host data processing system and provides various buses and interfaces available in modern computer systems. These interfaces include two double data rate (DDRx) memory channels, a PCIe root complex for connecting to a PCIe link, a USB controller for connecting to a USB network, and an interface to a SATA mass storage device.

[0028] APU 100 also implements various system monitoring and power saving functions. Specifically, one system monitoring function is thermal monitoring. For example, if APU 100 becomes hot, SMU 180 may reduce the frequency and voltage of CPU cores 112 and 114 and / or graphics core 120. If APU 100 becomes overheated, it may be shut down completely. SMU 180 may also receive thermal events from external sensors via the SMN bus, and in response, SMU 180 may reduce the clock frequency and / or the power supply voltage.

[0029] 2 shows a memory controller 200 known in the art in block diagram form. The memory controller 200 includes a memory channel controller 210 and a power controller 250. The memory channel controller 210 includes an interface 212, a memory interface queue 214, a command queue 220, an address generator 222, a content addressable memory (CAM) 224, a replay queue 230, a refresh logic block 232, a timing block 234, a page table 236, an arbiter 238, an error correction code (ECC) check block 242, an ECC generation block 244, and a data buffer (DB) 246.

[0030] The interface 212 has a first bidirectional connection to the data structure 125 through an external bus and has an output. In the memory controller 200, the external bus is compatible with the Advanced eXtensible Interface version four (referred to as AXI4) specified by ARM Holdings, PLC of Cambridge, England, but may be other types of interfaces in other embodiments. The interface 212 converts memory access requests from a first clock domain referred to as the FCLK (or MEMCLK) domain to a second clock domain referred to as the UCLK domain internal to the memory controller 200. Similarly, the memory interface queue 214 provides memory access from the UCLK domain to the DFICLK domain associated with the DFI interface.

[0031] The address generator 222 decodes the address of the memory access request received from the data structure 125 via the AXI4 bus. The memory access request includes an access address represented by a normalized address in the physical address space. The address generator 222 converts the normalized address into a format that can be used to address the actual memory device in the memory system 130 and efficiently schedule the related access. The format includes a region identifier that associates the memory access request with a specific storage column, row address, column address, storage body address, and storage body group. At startup, the system BIOS queries the memory devices in the memory system 130 to determine their size and configuration, and programs a set of configuration registers associated with the address generator 222. The address generator 222 uses the configuration stored in the configuration register to convert the normalized address into the appropriate format. The command queue 220 is a queue of memory access requests received from memory access agents in the APU 100, such as the CPU cores 112 and 114 and the graphics core 120. Command queue 220 stores address fields decoded by address generator 222 and other address information, including access type and quality of service (QoS) identification, that allows arbiter 238 to efficiently select memory accesses. CAM 224 includes information to implement ordering rules such as write-after-write (WAW) and read-after-write (RAW) ordering rules.

[0032] The replay queue 230 is a temporary queue for storing memory accesses selected by the arbiter 238 that are waiting for responses, such as address and command parity responses, write cyclic redundancy check (CRC) responses for DDR4 DRAM, or write and read CRC responses for GDDR5 DRAM. The replay queue 230 accesses the ECC check block 242 to determine whether the returned ECC is correct or indicates an error. The replay queue 230 allows the access to be replayed in the event of a parity or CRC error in one of these cycles.

[0033] The refresh logic 232 includes state machines for various power-down, refresh, and terminal resistance (ZQ) calibration cycles that are generated separately from normal read and write memory access requests received from the memory access agent. For example, if a memory storage column is in a pre-charge power-down, the memory storage column must be periodically awakened to run a refresh cycle. The refresh logic 232 periodically generates automatic refresh commands to prevent data errors caused by charge leakage from the storage capacitors of the memory cells in the DRAM chip. In addition, the refresh logic 232 periodically calibrates the ZQ to prevent mismatches in the terminal resistance on the die due to thermal changes in the system. The refresh logic 232 also decides when to place the DRAM devices in different power-down modes.

[0034] The arbiter 238 is bidirectionally connected to the command queue 220 and is the core of the memory channel controller 210. The arbiter improves efficiency by intelligently scheduling accesses to improve the utilization of the memory bus. The arbiter 238 uses the timing block 234 to enforce the correct timing relationship by determining whether certain accesses in the command queue 220 are eligible to be issued based on the DRAM timing parameters. For example, each DRAM has a minimum specified time between activation commands to the same memory bank, called "t RC ". The timing block 234 maintains a set of counters that determine eligibility based on the timing parameters and other timing parameters specified in the JEDEC specification, and the timing block is bidirectionally connected to the replay queue 230. The page table 236 maintains status information about the active pages in each memory bank and memory column of the memory channel of the arbiter 238, and is bidirectionally connected to the replay queue 230.

[0035] In response to receiving a write memory access request from the interface 212, the ECC generation block 244 calculates the ECC based on the write data. The DB 246 stores the write data and ECC of the received memory access request. When the arbiter 238 selects the corresponding write access for scheduling to the memory channel, the data buffer outputs the combined write data / ECC to the memory interface queue 214.

[0036] The power controller 250 includes an interface 252 to an Advanced eXtensible Interface Version 1 (AXI), an APB interface 254, and a power engine 260. The interface 252 has a first bidirectional connection to the SMN, the first bidirectional connection including an input for receiving an event signal labeled "EVENT_n" shown separately in FIG. 2, and an output. The APB interface 254 has an input connected to the output of the interface 252, and an output for connecting to the PHY through the APB. The power engine 260 has an input connected to the output of the interface 252, and an output connected to the input of the memory interface queue 214. The power engine 260 includes a set of configuration registers 262, a microcontroller (μC) 264, a self-refresh controller (SLFREF / PE) 266, and a reliable read / write training engine (RRW / TE) 268. The configuration registers 262 are programmed through the AXI bus and store configuration information to control the operation of various blocks in the memory controller 200. Therefore, configuration register 262 has outputs connected to these blocks, which are not shown in detail in Figure 2. Self-refresh controller 266 is an engine that allows refreshes to be manually generated in addition to the refreshes automatically generated by refresh logic 232. Reliable read / write training engine 268 provides a continuous memory access stream to the memory or I / O device for purposes such as DDR interface read latency training and loopback testing.

[0037] The memory channel controller 210 includes a circuit system that allows it to select memory accesses for scheduling to the associated memory channel. In order to make the desired arbitration decision, the address generator 222 decodes the address information into pre-decoding information, which includes the storage column, row address, column address, memory bank address and memory bank group in the memory system, and the command queue 220 stores the pre-decoding information. The configuration register 262 stores the configuration information to determine the manner in which the address generator 222 decodes the received address information. The arbitrator 238 uses the decoded address information, the timing condition information indicated by the timing block 234, and the active page information indicated by the page table 236 to efficiently schedule memory accesses while complying with other criteria such as QoS requirements. For example, the arbitrator 238 implements priority for accessing open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides the overhead access to one memory bank by interleaving the overhead access to one memory bank with the read and write access to another memory bank. In particular, during normal operation, arbiter 238 may decide to keep pages open in different banks until those pages need to be precharged, and then select a different page.

[0038] Figure 3 A block diagram is shown that can be used according to some embodiments Figure 1 2. The memory controller 300 includes a number of elements having reference numerals corresponding to those in FIG2. Since these elements function in the same or similar manner, these elements will not be described again.

[0039] However, the memory controller 300 operates more efficiently in a multi-rank system than the memory controller 200 of FIG. 2 , and the differences between the memory controller 300 and the memory controller 200 will now be described. In addition to the command queue 320, which operates similarly to the command queue 220 of FIG. 2 , the memory controller 300 also includes a staging buffer 326 and a picker 328. The staging buffer 326 has an input connected to the output of the address generator 322 and an output. The picker 328 has an input connected to the staging buffer 326, a control input connected to the second output of the page table 336, and an output connected to the input of the command queue 320. The page table 336 is similar to the page table 236 of FIG. 2 , but has been modified to provide additional information about the currently selected rank and, in some embodiments, additional rank information, as will now be described.

[0040] In operation, the memory controller 300 operates more efficiently in a multi-rank memory system than the memory controller 200 of Figure 2. Conversely, the memory controller 300 requires a smaller circuit area than the memory controller 200 of Figure 2 to operate at a particular rank switching efficiency in a multi-rank system.

[0041] The memory controller 300 adds a hierarchical buffer 326 and a picker 328 to provide a higher storage column hit rate for a given size of the command queue 320. In addition, as will be further described below, the memory controller 300 also facilitates efficient write-to-read switching in a multi-storage column memory system. The address generator 322 decodes the memory access into at least one storage column. In a specific embodiment, the address generator 322 decodes the access into storage columns, storage bodies, rows, and columns. The hierarchical buffer 326 receives and stores the memory access request decoded by the address generator 322. The hierarchical buffer 326 is only used to select in the access based on the storage column rather than based on other arbitration criteria, and requires fewer fields in each entry. Therefore, each entry in the hierarchical buffer 326 requires less circuit area than the corresponding entry in the command queue 320.

[0042] The picker 328 picks from the memory access requests stored in the staging buffer 326 and provides the selected accesses to the input of the command queue 320. In one embodiment, the picker 328 picks accesses to the current memory rank and to the second memory rank, but not to any other memory rank. In this case, the page table 336 stores the current memory rank and the second memory rank (or an indication thereof) and provides the current memory rank and the second memory rank to the picker 328. In this case, the page table 336 receives the current memory rank and the second memory rank from the arbiter 338 and stores the current memory rank and the second memory rank in addition to the current page of each memory bank and memory rank, and provides the current memory rank to the input of the picker 328. The picker 328 picks accesses from the staging buffer 326 from the current memory rank and the second memory rank, but not to any other memory rank. The picker 328 attempts to pick approximately the same number of accesses from the two memory ranks in a round-robin manner to hide the single memory rank four access window (t FAW ) and activation to activation (t RRD) timing constraints. If there are no remaining accesses to the current storage column and / or the second storage column in the staging buffer 326, the picker 328 may pick accesses from the staging buffer 326 in various ways. According to one embodiment, the arbitrator 338 implements a scoreboard of the number of accesses per storage column in the staging buffer 326. The scoreboard tracks the number of accesses for each storage column stored in the staging buffer 326. When the picker 328 completes picking a request in one storage column, the arbitrator 338 will pick the next storage column as the storage column that qualifies due to having the most requests among the candidate storage columns. That is, when the staging buffer 326 no longer stores accesses to the current storage column and / or the second storage column, the arbitrator 338 is operable to cause the picker 328 to pick accesses from a third storage column, wherein the number of accesses to the third storage column is greater than or equal to the number of accesses to any other storage column in the staging buffer 326. By using this scoreboard technique, the arbitrator 338 can achieve fewer overall storage column switches.

[0043] In another embodiment, the picker 328 picks accesses to the current memory rank selected by the arbiter 338, but not to any other memory rank. In this case, the page table 336 receives the current memory rank (or an indication of the current memory rank) from the arbiter 338 and stores the current memory rank in addition to the current page for each memory bank and memory rank, and provides the current memory rank to the input of the picker 328. If there are no remaining accesses to the current memory rank in the staging buffer 326, the picker 328 picks the accesses from the staging buffer 326 in the order received.

[0044] By including the staging buffer 326 and the picker 328, the memory controller 300 increases the average number of same rank accesses that can be picked from the command queue 320 before a rank switch is required. This is achieved by increasing the memory access command window size according to both the depth of the command queue 320 and the depth of the staging buffer 326. This mechanism reduces the number of rank switches during an access sequence. In addition, each entry in the staging buffer 326 is significantly smaller than the corresponding entry in the command queue 320, and therefore the memory controller 300 makes a better trade-off between additional circuit area and improved rank switching efficiency.

[0045] In a multi-storage rank system with a large number of storage ranks, the hierarchical buffer 326 provides a significant increase in storage rank switching efficiency compared to the memory controller 200 of Figure 2. For example, the command queue 320 can have a total of 64 entries in a 32-storage rank memory system. If the access is evenly distributed across multiple storage ranks, on average, the command queue 320 will store two accesses from each storage rank. Compared to a system with a much smaller number of storage ranks, performing a storage rank turnover for every two memory access requests will produce significantly lower efficiency. The memory controller 300 adds a hierarchical buffer 326 to increase the access window visible to the arbiter 338, so that more accesses to the current storage rank and the second storage rank can be placed in the command queue 320. At the same time, this does not increase the size of the command queue 320 or the complexity of the arbiter 338.

[0046] Entries in command queue 320 include more fields than entries in staging buffer 326. Picker 328 picks entries of staging buffer 326 based solely on memory rank to provide to command queue 320. Thus, picker 328 can be implemented as a relatively simple circuit. In addition, due to the smaller size of each of its entries, staging buffer 326 can include more entries than command queue 320. This feature is important in multi-memory rank systems with a large number of expected memory memory ranks.

[0047] Additional efficiency issues arise in multi-rank systems due to same bank write-to-read turnaround. The mechanism and an improved arbitration system for handling this issue will now be described.

[0048] Figure 4 A timing diagram 400 illustrating components of a write to read turnaround time is shown. Figure 4 4, the horizontal axis represents time in picoseconds (ps) and the vertical axis represents the amplitude of various signals of interest in volts. Timing diagram 400 includes waveform 410 of a memory command clock signal labeled "CK" and its complement labeled "CK#", waveform 420 of a command signal labeled "COMMAND", waveform 430 of an address signal labeled "ADDRESS", waveform 440 of a real data strobe signal labeled "DQS" and its complement labeled "DQS#", and waveform 450 of a data signal labeled "DQ" representing a complex number (e.g., eight bits) of data signal.

[0049] The CK and CK# signals form a differential clock signal that the DDR memory chip uses to record commands and time the input and output of data. Timing diagram 400 shows specific transitions labeled "T0" through "T9" and transitions labeled "Tn" that occur an amount of time after T7 determined by the memory and clock speed.

[0050] COMMAND is recorded on the low-to-high transition of the CK signal and the high-to-low transition of the CK# signal. Shown in timing diagram 400 is a write command occurring at T0, followed by a read command occurring at Tn, separated by a no operation (NOP) encoding of the COMMAND signal. The COMMAND signal comprises a set of individual signals used by the memory controller 300 to encode specific types of commands. These signals and their encoding are specified by the corresponding DDR standard, and because these signals and their encoding are well known, they will not be described further.

[0051] As shown in timing diagram 400, the WRITE cycle at time T0 is directed to a specific bank and column in a given memory column labeled "Bank, Column n", and the READ cycle is directed to a different bank and column of the same memory column at Tn labeled "Bank, Column b". The minimum amount of time between T0 and Tn is called the turnaround time, and in this case is the same memory column write to read turnaround time. The same memory column write to read turnaround time is determined by three separate timing components, which will now be described with reference to the specific WRITE command shown in timing diagram 400.

[0052] The amount of time from when a WRITE command is issued until the write data is provided to the memory chip is called the column write latency or t CWL As shown in Figure 5, t CWL is the time from T0 to T5, or five clock cycles in this example.

[0053] The write cycle initiated by the WRITE command to T0 causes the writing of data to begin at time T5. Prior to T5, the memory controller provides a preamble period in the DQS and DQS# signals. Timing diagram 400 is a timing diagram for a DDR4 SDRAM, and the preamble includes DQS going high for half a clock cycle at T4, then going low for half a clock cycle, and then going high again at T5 to cause the first data element to be written to the memory. As shown in timing diagram 400, the write cycle is a burst of 4, where data is transmitted over four half cycles defined by four consecutive transitions of the DQS and DQS# signals. For the write cycle, the memory controller drives both the data select signals DQS and DQS# and the data signal DQ. The transitions in the DQS and DQS# signals occur in the middle of the valid time of each data value at the memory chip, shown as the value "D IN n", "D IN n+1", "D IN n+2" and "D INn+3", where the "IN" designator represents data output by the memory controller and input to the memory. The length of the 4 bursts is labeled t(BL / 2), where BL equals the number of cycles in a write burst. Therefore, in timing diagram 400, t(BL / 2) equals two clock cycles. After the memory controller transmits the last data element, the memory controller provides a post-sync code in the DQS / DQS# signal, where DQS goes low for half a clock cycle and DQS# goes high for the same half clock cycle.

[0054] The amount of time from the end of the DQS postamble until a subsequent READ command can be accepted is the write-to-read time or t WTR This is shown in timing diagram 400 as occurring between T7 and Tn and is the minimum number of clock cycles determined by the clock speed and DDR version.

[0055] The total same-storage-column write-to-read turnaround time is given by Equation 1:

[0056] Same storage column turnover time = t CWL +t (BL / 2) +t WTR_S / L [1]

[0057] Among them, t WTR_S is the same memory column write-to-read turnaround time for accesses to different memory bank groups, and t WTR_L is the same memory column write to read turnaround time for accesses to the same memory bank group. Timing diagram 400 shows an example of DDR4 memory. In this example, the clock speed is 1866 megahertz (MHz). t CWL =5, t(BL / 2)=2 and t WTR_L = 14, a total of 21 clocks. In a DDR5 memory with a clock speed of 6400 MHz, the same memory column turnaround time can exceed 70 clock cycles.

[0058] FIG. 5 shows a set of timelines 500 of memory accesses that can be selected by a memory controller known in the prior art. In the timeline 500, time advances from left to right. The timeline 500 includes a first timeline 510 and a second timeline 520. The first timeline 510 shows a write access burst 511 and a subsequent read access burst 512 separated by an overhead period 513. As used in FIG. 5 and elsewhere, a "burst" of write or read access means a series or sequence of individual memory access commands, each memory access command containing multiple data transfers. Although a group of individual data transfers is also commonly referred to as a "burst", the present disclosure relates to bursts of memory access commands rather than individual data transfers. However, the appropriate meaning of "burst" will be apparent from its context.

[0059] In the write access burst 511, the write accesses labeled "W0" are write accesses to memory rank 0, while the write accesses labeled "W1" are write accesses to memory rank 1. When the memory controller performs memory rank switching within a burst, a relatively small overhead loss or "foam" is incurred. Due to the relatively long write-to-read turnaround time, the memory controller prefers to switch memory ranks to continue the write burst rather than switching between write and read access types. Therefore, in the example shown in the first timeline 510, the memory controller selects two write accesses to memory rank 0, followed by two write accesses to memory rank 1, followed by one write access to memory rank 0 before performing a write-to-read turnaround.

[0060] In the read access burst 512, the read access labeled "R0" is a read access to memory rank 0, and the read access labeled "R1" is a read access to memory rank 1. All accesses, including the read access selected by the memory controller, must meet all timing condition specifications, including the same memory rank write to read turnaround time given by equation [1] above. In the example shown in the first timeline 510, read access to memory rank 1 is not available until the write to read turnaround time for memory rank 1 is met, so the memory controller starts the read burst with an access to memory rank 1. In the very next cycle, a read access to memory rank 0 becomes available to issue, and by then the write to read turnaround time for memory rank 0 has been met, so the memory controller selects the read of memory rank 0 as the next access.

[0061] The overhead period 513 represents a time period during which the memory controller cannot pick up any memory access because the memory access has the same memory rank write-to-read turnaround time and has not yet become eligible for timing. This time period is relatively long and significantly reduces the efficiency of the system.

[0062] The second timeline 520 shows a burst of write accesses 521 and a subsequent burst of read accesses 522 separated by an overhead period 523. The second timeline 520 is similar to the first timeline 510, except that there are no available read accesses when the same bank write to read turnaround time expires after the last access to bank 1. Therefore, the memory controller waits for the entire same bank write to read turnaround time after the last access to bank 0. Subsequently, a read access to memory rank 1 becomes available before the first read access, and the memory controller picks that read access in the read burst after the access to memory rank 0.

[0063] The inventors have discovered that rank switching near the end of a write burst (e.g., write access burst 511 or 521) increases inefficiency due to long same bank write to read turnaround times. However, according to various embodiments disclosed herein, data processors and methods avoid rank switching near the end of a write burst and reduce the foam to a much smaller amount, thereby increasing memory controller efficiency.

[0064] To address this efficiency issue, the inventors have discovered that there is an opportunity to reduce the inefficiencies typically caused by write-to-read turnaround in multi-rank systems and have developed a data processor and memory controller with an arbiter 338 that exploits this opportunity to improve efficiency and memory bus utilization.

[0065] Figure 6 According to some embodiments, Figure 3 6 is a block diagram of a portion 600 of the memory controller 300. The portion 600 includes the arbiter 338 and a set of control circuits 660 associated with the operation of the arbiter 338.

[0066] The arbiter 338 includes a group of sub-arbiters 605 and a final arbiter 650. The sub-arbiter 605 includes a sub-arbiter 610, a sub-arbiter 620, and a sub-arbiter 630. The sub-arbiter 610 includes a page hit arbiter 612 labeled "PH ARB" and an output register 614. The page hit arbiter 612 has a first input terminal, a second input terminal, and an output terminal connected to the command queue 320. The register 614 has a data input terminal connected to the output terminal of the page hit arbiter 612, a clock input terminal for receiving a UCLK signal, and an output terminal. The sub-arbiter 620 includes a page conflict arbiter 622 labeled "PC ARB" and an output register 624. The page conflict arbiter 622 has a first input terminal, a second input terminal, and an output terminal connected to the command queue 320. The register 624 has a data input terminal connected to the output terminal of the page conflict arbiter 622, a clock input terminal for receiving a UCLK signal, and an output terminal. The sub-arbiter 630 includes a page miss arbiter 632 labeled "PM ARB" and an output register 634. The page miss arbiter 632 has a first input connected to the command queue 320, a second input, and an output. The register 634 has a data input connected to the output of the page miss arbiter 632, a clock input for receiving a UCLK signal, and an output. The final arbiter 650 has a first input connected to the output of the refresh logic 332, a second input from the page close predictor 662, a third input connected to the output of the output register 614, a fourth input connected to the output of the output register 624, a fifth input connected to the output of the output register 634, and an output for providing an arbitration winner labeled "CMD" to the memory interface queue 314. In some embodiments, the final arbiter 650 is capable of picking two sub-arbitration winners per memory controller clock cycle.

[0067] The control circuit 660 includes a timing block 334 and a page table 336 corresponding to the timing block 234 and the page table 236 previously described with respect to FIG. 2 , as well as a page closing predictor 662, a current mode register 602, and a cross mode enable logic unit 604. The timing block 334 has an output connected to the cross mode enable logic unit 604, an input connected to the page hit arbiter 612, a page conflict arbiter 622, and an output connected to the page miss arbiter 632. The page table 336 has an input connected to the output of the replay queue 230, an output connected to the input of the replay queue 330, an output connected to the input of the command queue 320, an output connected to the input of the timing block 334, and an output connected to the input of the page closing predictor 662. The page closing predictor 662 has an input connected to one output of the page table 336, an input connected to the output of the output register 614, and an output connected to a second input of the final arbiter 650. The cross mode enabling logic component 604 has an input terminal connected to the current mode register 602 and an input terminal connected to the command queue 220 , an input terminal and an output terminal connected to the final arbiter 650 , and an input terminal and an output terminal connected to the sub-arbiter 610 , the sub-arbiter 620 , and the sub-arbiter 630 .

[0068] In operation, the arbiter 338 selects memory access commands from the command queue 320 and the refresh logic unit 332 by considering the current mode (indicating whether read tailing or write tailing is in progress), the page status of each entry, the priority of each memory access request, and the correlation between these requests. The priority is related to the quality of service or QoS of the request received from the AXI4 bus and stored in the command queue 320, but can be changed based on the type of memory access and the dynamic operation of the arbiter 338. The arbiter 338 includes three sub-arbiters that operate in parallel to address the mismatch between the processing and transmission limitations of existing integrated circuit technologies. The winners of the corresponding sub-arbitrations are presented to the final arbiter 650. The final arbiter 650 selects between the three sub-arbitration winners and selects the refresh operation from the refresh logic unit 332, and can further modify the read or write command to a read or write with an automatic precharge command as determined by the page close predictor 662.

[0069] The cross mode enable logic 604 operates to cause and manage tailing of read commands and tailing of write commands on the memory channel. During the current tailing of either type of command, the cross mode enable logic 604 monitors the indication of the data bus efficiency of the memory channel. In response to the indication of the data bus efficiency indicating that the data bus efficiency is below a specified threshold, the cross mode enable logic 604 stops the current tailing, starts another type of tailing, and changes the current mode in the current mode register 602.

[0070] Each of the page hit arbiter 612, the page conflict arbiter 622 and the page miss arbiter 632 has an output connected to the timing block 334 to determine the input of the command queue 320 that falls into these corresponding categories and meets the timing condition. The timing block 334 includes an array of binary counters, which counts the duration associated with the specific operation of each storage body in each storage column. The number of timers required to determine the state depends on the timing parameters, the number of storage bodies of a given memory type, and the number of storage columns supported by the system on a given memory channel. The number of timing parameters implemented depends on the type of memory implemented in the system. For example, compared with other DDRx memory types, GDDR5 memory requires more timers to comply with more timing parameters. By including an array of general timers implemented as binary counters, the timing block 334 can be scaled and reused for different memory types. The input from the cross mode enable logic unit 604 signals the sub-arbiter to provide which type of command (read or write) as a candidate for the final arbiter 650.

[0071] A page hit is a read or write cycle to an open page. The page hit arbiter 612 arbitrates between accesses in the command queue 320 to open a page. Timing condition parameters tracked by the timer in the timing block 334 and checked by the page hit arbiter 612 include, for example, the row address strobe (RAS) to column address strobe (CAS) delay time (t RCD ) and CAS latency (t CL ). For example, t RCD The minimum amount of time that must pass before read or write access to a page after the page has been opened in the RAS cycle is specified. The page hit arbitrator 612 selects the sub-arbitration winner based on the assigned access priority. In one embodiment, the priority is a 4-bit, unique hot value, thus indicating the priority among four values, however, it should be apparent that this four-level priority scheme is only an example. If the page hit arbitrator 612 detects two or more requests of the same priority level, the oldest entry wins.

[0072] A page conflict is an access to a row in a bank when another row in the bank is currently active. The page conflict arbitrator 622 arbitrates between accesses to pages in the command queue 320 that conflict with pages currently open in the corresponding bank and rank. The page conflict arbitrator 622 selects the sub-arbitration winner that results in the issuance of a precharge command. Timing condition parameters tracked by the timer in the timing block 334 and checked by the page conflict arbitrator 622 include, for example, the active to precharge command period (t RAS). The page conflict arbitrator 622 selects a sub-arbitration winner based on the assigned access priority. If the page conflict arbitrator 622 detects two or more requests of the same priority level, the oldest entry wins.

[0073] A page miss is an access to a memory bank that is in a precharged state. The page miss arbiter 632 arbitrates between accesses to precharged memory banks in the command queue 320. Timing-eligible parameters tracked by the timer in the timing block 334 and checked by the page miss arbiter 632 include, for example, the precharge command period (t RP ). If there are two or more requests that are page misses at the same priority level, the oldest entry wins.

[0074] Each sub-arbitrator outputs a priority value for their respective sub-arbitration winner. The final arbitrator 650 compares the priority values ​​of the sub-arbitration winners from each of the page hit arbitrator 612, the page conflict arbitrator 622, and the page miss arbitrator 632. The final arbitrator 650 determines the relative priority between the sub-arbitration winners by performing a set of relative priority comparisons that consider two sub-arbitration winners at a time. The sub-arbitrators may include a set of logic for arbitrating commands for read and write for each mode so that when the current mode changes, a set of available candidate commands are quickly available as sub-arbitration winners.

[0075] After determining the relative priorities between the three sub-arbitration winners, the final arbitrator 650 then determines whether these sub-arbitration winners conflict (i.e., whether they point to the same memory bank and memory column). When there is no such conflict, the final arbitrator 650 selects at most two sub-arbitration winners with the highest priority. When there is a conflict, the final arbitrator 650 follows the following rules. When the priority value of the sub-arbitration winner of the page hit arbitrator 612 is higher than the priority value of the sub-arbitration winner of the page conflict arbitrator 622 and both point to the same memory bank and memory column, the final arbitrator 650 selects the access indicated by the page hit arbitrator 612. When the priority value of the sub-arbitration winner of the page conflict arbitrator 622 is higher than the priority value of the sub-arbitration winner of the page hit arbitrator 612 and both point to the same memory bank and memory column, the final arbitrator 650 selects the winner based on several additional factors. In some cases, the page close predictor 662 causes the page to be closed at the end of the access indicated by the page hit arbitrator 612 by setting the automatic precharge attribute.

[0076] Within the page hit arbiter 612, the priority is initially set by the request priority from the memory access agent, but is dynamically adjusted based on the access type (read or write) and the access sequence. In general, the page hit arbiter 612 assigns a higher implicit priority to reads, but implements a priority boosting mechanism to ensure that writes make progress toward completion.

[0077] Whenever the page hit arbiter 612 selects a read or write command, the page close predictor 662 determines whether to send a command with an automatic precharge (AP) attribute. The automatic precharge attribute is set with a predefined address bit during the read or write cycle, and the automatic precharge attribute causes the DDR device to close the page after the read or write cycle is completed, which avoids the need for the memory controller to send a separate precharge command for the memory bank later. The page close predictor 662 considers other requests that already exist in the command queue 320 to access the same memory bank as the selected command accesses. If the page close predictor 662 converts the memory access into an AP command, the next access to the page will be a page miss.

[0078] The crossbar mode enabling logic 604 reduces the inefficiency caused by the same rank write to read turnaround time by controlling the sub-arbiter 605 to avoid rank switching near the end of a write burst. To completely hide the same rank write to read overhead, the number of write requests L of the same rank that would need to be available at the end of a write burst would be:

[0079] L=(t CWL +t (BL / 2) +t WTR_S / L ) / t CCD [2]

[0080] Among them, t CCD is the column address strobe (CAS) to CAS delay.

[0081] In one example, the cross mode enabling logic 604 may determine that the cross mode enabling logic is near the "end" of a write burst by determining that the total number of writes in the command queue 320 is less than a fixed threshold. In another example, the cross mode enabling logic 604 may determine that the cross mode enabling logic is near the "end" of a write burst by determining that the number of writes in the command queue 320 to a storage rank different from the current storage rank is less than L. In either case, when the cross mode enabling logic 604 detects the "near end" condition, the cross mode enabling logic does not allow the write burst to switch to another storage rank. When switching to a read burst, these constraints may keep some writes out of the burst.

[0082] Figure 7 According to some embodiments, Figure 6 FIG. 7 is a timeline 700 of memory accesses selected by the arbiter 338 of FIG. 700 . In the timeline 700 , time progresses from left to right. The timeline 700 shows a write access burst 710 and a subsequent read access burst 720 separated by an overhead period 730 . The write access burst 710 includes a write access to memory rank 1 followed by four write accesses to memory rank 0 . The read access burst 720 includes four read accesses to memory rank 1 followed by a read access to memory rank 0 . As shown in the timeline 700 , the timing condition is met including the same memory bank write to read turnaround time of the first read access to memory rank 1 satisfied from the end of the write access to memory rank 1 to the beginning of the read access burst 720 . Similarly, there is the same memory bank write to read turnaround time of the read access to memory rank 0 satisfied from the end of the last write access to memory rank 0 to the beginning of the read access to memory rank 0 in the read access burst 720 .

[0083] In addition, there is a WRRD "The write-to-read turnaround latency of different memory ranks is different, during which the memory controller cannot use the memory bus, resulting in inefficiency. WRRD Significantly shorter than t WTR_S / L In addition, as the memory clock speed increases, t WRRD T WTR_S / L For example, for high-speed DDR5 SDRAM running at 6400MHz, t CWL is 54 memory clock cycles, and t WTR is 30 memory clock cycles, and t WRRD Between 10 and 20 memory clock cycles, depending on the board design, resulting in a difference between same rank and different rank turnarounds of more than about 70 memory clock cycles.

[0084] The staging buffer 326 can enhance the ability to avoid same-rank write-to-read turnaround time losses, which can be aided by the use of the staging buffer 326. If the command queue 320 can see requests from many ranks, the command queue will naturally do rank switching more frequently. To avoid the command queue 320 seeing requests from too many ranks, the picker 328 can temporarily leave unwanted requests in the staging buffer 326. In this way, the staging buffer 326 and picker 328 can reshape multi-rank traffic into two-rank traffic by picking requests from only two active ranks.

[0085] For example, a sequence of requests evenly distributed across five ranks and equally divided between reads and writes can be picked from the staging buffer 326 so that the command queue 320 focuses on only two ranks at a time. This technique ensures that most command requests come from only two ranks rather than multiple ranks and prevents too much rank switching time between CAS commands. The picker 328 will pick requests from the two preferred ranks until the requests from the staging buffer are exhausted, and will then move to another rank (if the first rank is exhausted before the second rank) or to two other ranks (if the first rank and the second rank are exhausted at the same time).

[0086] Figure 8 800 is a flow chart of a technique for selecting access from a multi-storage rank system according to some embodiments. In action block 810, the memory controller 300 initiates a write burst. In action block 820, the memory controller 300 performs a write access to the current storage rank. Then, in decision block 830, the memory controller 300 determines whether it is near the end of the write burst, for example, by the cross mode enable logic component 604. For example, the cross mode enable logic component 604 can determine whether the total number of write accesses in the command queue 320 is less than a predetermined number. In another example, the cross mode enable logic component 604 can determine whether the number of write accesses to the current storage rank in the command queue 320 is sufficient to hide the overhead of the same memory bank write to read turnaround time. If the memory controller 300 is not near the end of the write burst, then in action block 831, the memory controller 300 determines whether to selectively switch the current storage rank to another storage rank. The switch can be based on other conventional memory controller selection criteria. After selectively switching the current storage rank, the process returns to action block 820. However, if the memory controller 300 is nearing the end of a write burst, then in action block 840, the memory controller continues to write bursts to the current memory rank for a predetermined number of times. The predetermined number is selected to hide the same memory rank write to read turnaround time. In action block 850, wait for a much shorter memory rank write to read turnaround time t WRRD Then, when any read access meets the timing condition, the memory controller 300 starts a read burst, as shown in decision block 860, where the memory controller 300 determines whether any read access meets the timing condition based on all timing criteria. If no read access meets the timing condition, the method continues to test whether the read access meets the timing condition. When the read access meets the timing condition, the flow proceeds to action block 870, where the memory controller 300 starts a read burst.

[0087] The disclosed technique improves the efficiency of memory access by avoiding the same bank write-to-read turnaround time, and instead only waits for the overhead of a different bank write-to-read turnaround time, assuming that some read access to a different bank is available. Furthermore, this relies on the existing timing-qualified check to allow the arbiter to naturally select any timing-qualified read access after the end of a write burst based on normal timing-qualified criteria.

[0088] The data processor 100 or any part thereof (e.g., the memory controller 300) may be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture an integrated circuit. For example, the data structure may be a behavioral level description or a register transfer level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool, which may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represent the functionality of the hardware comprising the integrated circuit. The netlist may then be placed and routed to produce a data set describing the geometry to be applied to the mask. The mask may then be used in various semiconductor manufacturing steps to produce an integrated circuit. Alternatively, the database on a computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set (as required) or a graphic data system (GDS) II data.

[0089] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, various techniques for determining when a memory controller is near the end of a write burst are possible. In addition, the write-to-read turnaround technique may be used independently of or in conjunction with a hierarchical buffer and a picker, wherein the hierarchical buffer and the picker are well suited for extending the window for selecting desired accesses to be placed in a command queue in a multi-storage column system. Although examples of selecting a current storage column and a second storage column from a hierarchical buffer to provide to a command queue are described, different numbers of additional storage columns may be selected. In addition, in other embodiments, the circuit structure of the arbiter may be different.

[0090] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A method for a memory controller to select a memory access request to be provided to a memory channel having a plurality of memory ranks, comprising: Initiate a write access burst; Perform write access to the current storage column; determining whether the memory controller is nearing the end of the write access burst; In response to the memory controller not approaching the end of the write access burst: selectively switching the current storage rank; and repeating the performing and the determining; In response to the memory controller approaching the end of the write access burst: Continue to perform the write access burst on the current storage column for a predetermined number of times; Waiting for write-to-read turnaround time; and When any read access meets the timing condition, a read burst begins.

2. The method according to claim 1, wherein: The determining whether the memory controller is nearing the end of the write access burst comprises: A determination is made as to whether a total number of write accesses in a command queue of the memory controller is less than a predetermined number.

3. The method according to claim 1, wherein: The determining whether the memory controller is nearing the end of the write access burst comprises: A determination is made as to whether the number of write accesses to the current memory rank in the command queue of the memory controller is sufficient to hide the overhead of the same bank write to read turnaround time.

4. The method according to claim 1, wherein: The waiting for the write-to-read turnaround time includes: Wait based on column address strobe (CAS) write latency, burst length, and write-to-read turnaround time for different memory columns.

5. The method according to claim 1, further comprising: storing memory accesses in a staging buffer; as well as picking a write memory access from the staging buffer and storing the write memory access in a command queue of the memory controller based on whether the write memory access is from the current memory rank or from another memory rank, The performing of the write access to the current storage rank includes performing the write access to one of the current storage rank and the another storage rank.

6. A data processor comprising: a command queue for receiving and storing decoded memory commands, wherein each of the decoded memory commands includes information indicating a type and a memory rank, wherein the type indicates one of read and write; and an arbiter coupled to the command queue for selecting among the decoded memory commands from the command queue to provide to a memory channel based on a plurality of criteria, wherein the arbiter is operable to determine whether the arbiter is nearing the end of a write access burst, and if the arbiter is nearing the end of the write access burst, to continue the write access burst to a current memory rank a predetermined number of times before commencing a read burst.

7. A data processor according to claim 6, wherein: The arbiter determines that the arbiter is approaching the end of the burst of write accesses based on whether a total number of write accesses in the command queue is less than a predetermined number.

8. The data processor according to claim 6, wherein: The arbiter determines that the arbiter is approaching the end of the write access burst based on whether a number of write accesses to the current memory rank in the command queue is sufficient to hide an overhead of a same bank write to read turnaround time.

9. The data processor according to claim 6, further comprising: a memory controller, the memory controller comprising the command queue and the arbiter; and A plurality of memory access agents are coupled to the memory controller for generating memory access requests.

10. The data processor according to claim 9, further comprising: A physical interface circuit is coupled to the memory controller and is operable to access a plurality of memory ranks of a double data rate (DDR) dynamic random access memory channel.

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