Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises a driving circuit, the driving circuit comprises a first node control circuit, a second node control circuit and an output circuit; the first node control circuit controls the potential of the first node respectively; the second node control circuit controls the potential of the second node and the potential of the third node; the output circuit controls the communication between the driving signal end and the second voltage line under the control of the potential of the first node, and controls the communication between the driving signal output end and the first voltage line under the control of the potential of the second node; the transistor included in the output circuit is arranged on the side of the second voltage line away from the display area, and the transistor included in the first node control circuit and the transistor included in the second node control circuit are arranged on the side of the transistor included in the output circuit away from the second voltage line. The present disclosure optimizes the layout space.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] In the relevant technology, there is no driving circuit that has strong driving capability, simple circuitry, and can meet the requirements of full oxide pixel driving, nor is there a display substrate that includes the driving circuit and optimizes the layout space. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a display substrate, including a driving circuit disposed on a substrate, the driving circuit including a first node control circuit, a second node control circuit, and an output circuit;

[0004] The first node control circuit is electrically connected to the first node, the input terminal, the first clock signal line, the second clock signal line, the third node, and the first voltage line, respectively. It is used to control the potential of the first node according to the input signal provided by the input terminal and the first voltage signal provided by the first voltage line under the control of the first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, and the potential of the third node.

[0005] The second node control circuit is electrically connected to the second node and the third node respectively, and is used to control the potential of the second node and the potential of the third node;

[0006] The output circuit is electrically connected to the first node, the second node, the drive signal output terminal, the first voltage line, and the second voltage line, respectively, and is used to control the connection between the drive signal terminal and the second voltage line under the control of the potential of the first node, and to control the connection between the drive signal output terminal and the first voltage line under the control of the potential of the second node.

[0007] The transistors included in the output circuit are disposed on the side of the second voltage line away from the display area; the transistors included in the first node control circuit and the second node control circuit are disposed on the side of the transistors included in the output circuit away from the second voltage line; the first voltage line, the first clock signal line, and the second clock signal line are disposed on the side of the transistors included in the first node control circuit away from the second voltage line.

[0008] Optionally, the transistors included in the second node control circuit are disposed between the transistors included in the first node control circuit and the transistors included in the output circuit.

[0009] Optionally, the first node control circuit includes a first transistor, a second transistor, and a third transistor;

[0010] The first gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0011] The first gate of the second transistor is electrically connected to the second clock signal line, the first electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the first node;

[0012] The first gate of the third transistor is electrically connected to the third node, and the first electrode of the third transistor is electrically connected to the first voltage line.

[0013] Optionally, the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line all extend along a first direction;

[0014] The first transistor, the second transistor, and the third transistor are arranged sequentially along a first direction.

[0015] Optionally, the second node control circuit includes a third node control sub-circuit, a fourth node control sub-circuit, and a second node control sub-circuit.

[0016] The third node control sub-circuit is electrically connected to the third node, the second voltage line, the first clock signal terminal, and the first node, respectively, and is used to control the connection between the third node and the second voltage line under the control of the first clock signal, and to control the connection between the third node and the first clock signal line under the control of the potential of the first node.

[0017] The fourth node control sub-circuit is electrically connected to the third node, the second clock signal line and the fourth node respectively, and is used to control the connection between the fourth node and the second clock signal line under the control of the potential of the third node, and to control the potential of the fourth node according to the potential of the third node.

[0018] The second node control sub-circuit is electrically connected to the second clock signal line, the fourth node, the second node, the first node, and the first voltage line, respectively. It is used to control the connection between the second node and the fourth node under the control of the second clock signal, and to control the connection between the second node and the first voltage line under the control of the potential of the first node, and to maintain the potential of the second node.

[0019] Optionally, the third node control sub-circuit includes a fourth transistor and a fifth transistor;

[0020] The first gate of the fourth transistor is electrically connected to the first clock signal line, the first electrode of the fourth transistor is electrically connected to the second voltage line, and the second electrode of the fourth transistor is electrically connected to the third node.

[0021] The first gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first clock signal line, and the second electrode of the fifth transistor is electrically connected to the third node.

[0022] The fourth node control sub-circuit includes a sixth transistor and a first capacitor;

[0023] The first gate of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second clock signal line, and the second electrode of the sixth transistor is electrically connected to the fourth node;

[0024] The first plate of the first capacitor is electrically connected to the third node, and the second plate of the first capacitor is electrically connected to the fourth node;

[0025] The second node control sub-circuit includes a seventh transistor, an eighth transistor, and a second capacitor;

[0026] The first gate of the seventh transistor is electrically connected to the second clock signal line, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second node;

[0027] The first gate of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the first voltage line, and the second electrode of the eighth transistor is electrically connected to the second node;

[0028] The first plate of the second capacitor is electrically connected to the second node, and the second plate of the second capacitor is electrically connected to the first voltage line.

[0029] The output circuit includes a ninth transistor and a tenth transistor;

[0030] The first gate of the ninth transistor is electrically connected to the fourth node, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the drive signal output terminal.

[0031] The first gate of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the second voltage line, and the second electrode of the tenth transistor is electrically connected to the drive signal output terminal.

[0032] Optionally, the display substrate includes a semiconductor layer, a first gate metal layer, and a source / drain metal layer sequentially stacked along a direction away from the substrate.

[0033] The first gate of the first transistor and the first conductive connection portion are integral structures, and the first conductive connection portion is coupled to the first clock signal line;

[0034] The first electrode of the first transistor is coupled to the second conductive connection portion, and the second conductive connection portion is coupled to the input terminal; the second electrode of the first transistor is coupled to the third conductive connection portion, and the third conductive connection portion is coupled to the second electrode of the second transistor.

[0035] The first electrode of the third transistor is coupled to the fourth conductive connection portion, and the fourth conductive connection portion and the first voltage line are an integral structure.

[0036] The active layer of the first transistor includes a first electrode and a second electrode, the active layer of the second transistor includes a first electrode and a second electrode, and the active layer of the third transistor includes a first electrode and a second electrode.

[0037] The active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor are contained in the semiconductor layer; the first gate of the first transistor, the first gate of the second transistor, and the first gate of the third transistor are contained in the first gate metal layer; the input terminal and the first conductive connection portion are contained in the first gate metal layer; and the second conductive connection portion, the third conductive connection portion, and the fourth conductive connection portion are all contained in the source-drain metal layer.

[0038] Optionally, the display substrate includes a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source / drain metal layer sequentially stacked along a direction away from the substrate.

[0039] The first gate, first conductive connection portion, and fifth conductive connection portion of the fourth transistor are integral structures. The first conductive connection portion is coupled to the first clock signal line; the fifth conductive connection portion is coupled to the sixth conductive connection portion; and the sixth conductive connection portion is coupled to the first electrode of the fifth transistor.

[0040] The first gate of the second transistor, the first gate of the seventh transistor, the seventh conductive connection portion, and the eighth conductive connection portion are integral structures. The seventh conductive connection portion is coupled to the second clock signal line; the eighth conductive connection portion is coupled to the ninth conductive connection portion; the ninth conductive connection portion is coupled to the first electrode of the sixth transistor; the second electrode of the sixth transistor is coupled to the tenth conductive connection portion, and the tenth conductive connection portion is coupled to the second plate of the first capacitor.

[0041] The first gate of the third transistor, the first gate of the sixth transistor, the first plate of the first capacitor, and the eleventh conductive connection are integral structures, and the eleventh conductive connection is coupled to the twelfth conductive connection; the twelfth conductive connection is coupled to the second electrode of the fourth transistor and the second electrode of the fifth transistor, respectively.

[0042] The first gate of the fifth transistor, the first gate of the eighth transistor, the first gate of the tenth transistor, and the thirteenth conductive connection portion are an integral structure; the thirteenth conductive connection portion is coupled to the third conductive connection portion.

[0043] The first electrode of the fourth transistor is coupled to the fourteenth conductive connection, and the fourteenth conductive connection and the second voltage line are an integral structure;

[0044] The first electrode of the seventh transistor is adjacent to and continuous with the second electrode of the sixth transistor; the first gate of the ninth transistor and the fifteenth conductive connection portion are integral structures.

[0045] The second electrode of the seventh transistor is coupled to the sixteenth conductive connection portion, and the sixteenth conductive connection portion is coupled to the second electrode of the eighth transistor and the fifteenth conductive connection portion, respectively;

[0046] The first electrode of the eighth transistor is coupled to the first electrode of the ninth transistor;

[0047] The first gate of the ninth transistor and the first plate of the second capacitor are integrally formed; the second plate of the second capacitor is coupled to the seventeenth conductive connection, and the seventeenth conductive connection is integrally formed with the first voltage line.

[0048] The active layer of the fourth transistor includes a first electrode and a second electrode; the active layer of the fifth transistor includes a first electrode and a second electrode; the active layer of the sixth transistor includes a first electrode and a second electrode; the active layer of the seventh transistor includes a first electrode and a second electrode; and the active layer of the eighth transistor includes a first electrode and a second electrode.

[0049] The active layers of the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all contained within the semiconductor layer; the first gates of the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all contained within the first gate metal layer; the first plates of the first capacitor and the second capacitor are contained within the first gate metal layer; and the second plates of the first capacitor and the second capacitor are contained within the second gate metal layer.

[0050] The first clock signal line, the second clock signal line, the first voltage line, and the second voltage line are all contained in the source-drain metal layer; the fifth conductive connection, the seventh conductive connection, the eighth conductive connection, the eleventh conductive connection, the thirteenth conductive connection, and the fifteenth conductive connection are contained in the first gate metal layer; and the sixth conductive connection, the ninth conductive connection, the tenth conductive connection, the twelfth conductive connection, the fourteenth conductive connection, the sixteenth conductive connection, and the seventeenth conductive connection are all contained in the source-drain metal layer.

[0051] Optionally, the tenth transistor and the ninth transistor are arranged along a first direction; the active layer of the ninth transistor and the active layer of the tenth transistor are continuous with each other;

[0052] The first electrode of the tenth transistor, the second electrode of the tenth transistor, the first electrode of the ninth transistor, and the second electrode of the ninth transistor are all contained in the source / drain metal layer;

[0053] The first gate of the tenth transistor and the first gate of the ninth transistor are both contained in the first gate metal layer;

[0054] The first electrode of the tenth transistor, the fourteenth conductive connection portion, and the second voltage line are an integral structure;

[0055] The second electrode of the tenth transistor and the second electrode of the ninth transistor are integral structures; the second electrode of the ninth transistor is coupled to the drive signal output terminal, which is contained in the first gate metal layer;

[0056] The first electrode of the ninth transistor and the first voltage line are an integral structure.

[0057] Optionally, the first transistor, the second transistor, and the third transistor are all dual-gate transistors;

[0058] The second gate of the first transistor is electrically connected to the first voltage line, the second gate of the second transistor is electrically connected to the first voltage line, and the second gate of the third transistor is electrically connected to the first voltage line;

[0059] The display substrate further includes a light-shielding layer disposed between the substrate and the semiconductor layer, wherein the second gate of the first transistor, the second gate of the second transistor, and the second gate of the third transistor are all contained in the light-shielding layer.

[0060] Optionally, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all dual-gate transistors;

[0061] The second gate of the fourth transistor is electrically connected to the first voltage line, and the second gate of the fifth transistor is electrically connected to the second gate of the tenth transistor; the second gate of the tenth transistor is electrically connected to the second electrode of the tenth transistor.

[0062] The second gate of the sixth transistor is electrically connected to the first voltage line, and the second gate of the seventh transistor is electrically connected to the first gate of the ninth transistor; the second gate of the eighth transistor and the second gate of the ninth transistor are electrically connected, and the second gate of the ninth transistor is electrically connected to the first voltage line.

[0063] The second gates of the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all contained within the light-shielding layer.

[0064] Optionally, the driving circuit further includes a third capacitor;

[0065] The first plate of the third capacitor is electrically connected to the first node, and the second plate of the third capacitor is electrically connected to the second clock signal line.

[0066] Optionally, the driving circuit further includes a potential control circuit;

[0067] The potential control circuit is electrically connected to the first node and is used to control the potential of the first node to be less than the control voltage threshold.

[0068] Optionally, the potential control circuit includes an eleventh transistor;

[0069] The gate of the eleventh transistor and the first electrode of the eleventh transistor are both electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the second voltage line.

[0070] Optionally, all transistors included in the driving circuit are n-type transistors.

[0071] In a second aspect, embodiments of this disclosure also provide a display device including the display substrate described above. Attached Figure Description

[0072] Figure 1 This is a structural diagram of at least one embodiment of the driving circuit included in the display substrate described in this disclosure.

[0073] Figure 2 This is a structural diagram of at least one embodiment of the driving circuit included in the display substrate described in this disclosure.

[0074] Figure 3 This is a circuit diagram of at least one embodiment of the driving circuit included in the display substrate described in this disclosure.

[0075] Figure 4 yes Figure 3 The timing diagram of at least one embodiment of the driving circuit shown;

[0076] Figure 5 This is a circuit diagram of at least one embodiment of the driving circuit included in the display substrate described in this disclosure.

[0077] Figure 6 yes Figure 5 The timing diagram of at least one embodiment of the driving circuit shown;

[0078] Figure 7 This is a circuit diagram of at least one embodiment of the driving circuit included in the display substrate described in this disclosure.

[0079] Figure 8 yes Figure 7 The timing diagram of at least one embodiment of the driving circuit shown;

[0080] Figure 9 This is a circuit diagram of at least one embodiment of the driving circuit included in the display substrate described in this disclosure.

[0081] Figure 10 This is a circuit diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure, which shows the electrodes of each transistor and the plates of each capacitor.

[0082] Figure 11 yes Figure 10A layout diagram of at least one embodiment of the driving circuit shown;

[0083] Figure 12 yes Figure 11 Layout diagram of the semiconductor layer in the diagram;

[0084] Figure 13 yes Figure 11 Layout diagram of the first gate metal layer in the middle;

[0085] Figure 14 yes Figure 11 Layout diagram of the second gate metal layer;

[0086] Figure 15 yes Figure 11 Layout diagram of the first source / drain metal layer in the image;

[0087] Figure 16 This is a circuit diagram of at least one embodiment of the driving circuit included in the display substrate described in this disclosure.

[0088] Figure 17 Is Figure 11 The layout diagram shows at least one embodiment of the driving circuit with an added light-blocking layer.

[0089] Figure 18 yes Figure 17 Layout diagram of the light-blocking layer in the image;

[0090] Figure 19 Is Figure 11 A schematic diagram showing at least one embodiment of the display substrate with an added eleventh transistor;

[0091] Figure 20 yes Figure 19 A structural diagram of the semiconductor layer in the image;

[0092] Figure 21 yes Figure 19 A structural diagram of the first gate metal layer in the middle;

[0093] Figure 22 yes Figure 19 The structural diagram of the source and drain metal layers in the image. Detailed Implementation

[0094] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0095] In all embodiments of this disclosure, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first electrode, and the other terminal as the second electrode.

[0096] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0097] The display substrate described in this embodiment includes a driving circuit disposed on a substrate, such as... Figure 1 As shown, the driving circuit includes a first node control circuit 11, a second node control circuit 12, and an output circuit 13;

[0098] The first node control circuit 11 is electrically connected to the first node N1, the input terminal STV, the first clock signal line CK, the second clock signal line CB, the third node N3, and the first voltage line V1, respectively. It is used to control the potential of the first node N1 according to the input signal provided by the input terminal STV and the first voltage signal provided by the first voltage line V1 under the control of the first clock signal provided by the first clock signal line CK, the second clock signal provided by the second clock signal line CB, and the potential of the third node N3.

[0099] The second node control circuit 12 is electrically connected to the second node N2 and the third node N3 respectively, and is used to control the potential of the second node N2 and the potential of the third node N3;

[0100] The output circuit 13 is electrically connected to the first node N1, the second node N2, the drive signal output terminal E1, the first voltage line V1, and the second voltage line V2, respectively. It is used to control the connection between the drive signal terminal E1 and the second voltage line V2 under the control of the potential of the first node N1, and to control the connection between the drive signal output terminal E1 and the first voltage line V1 under the control of the potential of the second node N2.

[0101] The transistors included in the output circuit 13 are disposed on the side of the second voltage line V2 away from the display area. The transistors included in the first node control circuit 11 and the second node control circuit 12 are disposed on the side of the transistors included in the output circuit 13 away from the second voltage line V2. The first voltage line V1, the first clock signal line CK, and the second clock signal line CB are disposed on the side of the transistors included in the first node control circuit 11 away from the second voltage line V2.

[0102] In at least one embodiment of this disclosure, the first voltage line may be a low voltage line and the second voltage line may be a high voltage line, but this is not a limitation.

[0103] In a specific implementation, both the first voltage line and the second voltage line can be DC power signal lines;

[0104] The first voltage line is used to provide a first voltage signal, and the second voltage line is used to provide a second voltage signal. The voltage value of the first voltage signal may be less than the voltage value of the second voltage signal, but is not limited thereto.

[0105] Optionally, the line width of the first voltage line can be greater than the line width of the second voltage line;

[0106] The line width of the first clock signal line can be greater than the line width of the second voltage line, and the line width of the second clock signal line can be greater than the line width of the second voltage line.

[0107] However, this is not the limit.

[0108] In at least one embodiment of this disclosure, the driving signal output by the driving signal output terminal E1 can be a light emission control signal, but is not limited thereto.

[0109] In at least one embodiment of this disclosure, the driving circuit includes transistors that are all n-type transistors. The driving circuit has strong driving capability, simple circuit, can meet the requirements of full oxide pixel driving, and reduces one capacitor in the circuit structure, thus optimizing the layout space.

[0110] In at least one embodiment of this disclosure, the n-type transistor is turned on when the gate-source voltage of the n-type transistor is greater than the threshold voltage of the n-type transistor; and the n-type transistor is turned off when the gate-source voltage of the n-type transistor is less than the threshold voltage of the n-type transistor.

[0111] Optionally, the n-type transistor can be an oxide transistor or an n-type doped LTPS (low-temperature polysilicon) transistor; but it is not limited thereto.

[0112] In this public disclosure Figure 1 In at least one embodiment of the driving circuit shown, a capacitor electrically connected to the first node N1 is not provided. When used in an all-oxide driving circuit, this capacitor would cause a step in the output waveform, which is detrimental to the output. At least one embodiment of this disclosure reduces the use of this capacitor in the circuit structure of the driving circuit, optimizing the layout space.

[0113] In at least one embodiment of this disclosure, the transistors included in the output circuit 13 are disposed on the side of the second voltage line V2 away from the display area, and the transistors included in the first node control circuit 11 and the second node control circuit 12 are disposed on the side of the transistors included in the output circuit 13 away from the second voltage line V2; the first voltage line V1, the first clock signal line CK, and the second clock signal line CB are disposed on the side of the transistors included in the first node control circuit 11 away from the second voltage line V2, that is, the transistors included in the first node control circuit 11, the second node control circuit 12, and the output circuit 13 can be disposed between the first voltage line V1 and the second voltage line V2 for convenient layout.

[0114] In at least one embodiment of this disclosure, the transistor included in the second node control circuit is disposed between the transistor included in the first node control circuit and the transistor included in the output circuit.

[0115] In a specific implementation, the transistors included in the second node control circuit can be disposed between the transistors included in the first node control circuit and the transistors included in the output circuit, and the transistors included in the first node control circuit can be arranged sequentially along the first direction, thus saving horizontal space and facilitating the realization of a narrow bezel.

[0116] In at least one embodiment of this disclosure, the first direction may be a vertical direction, but is not limited thereto.

[0117] Optionally, the first node control circuit includes a first transistor, a second transistor, and a third transistor;

[0118] The first gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0119] The first gate of the second transistor is electrically connected to the second clock signal line, the first electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the first node;

[0120] The first gate of the third transistor is electrically connected to the third node, and the first electrode of the third transistor is electrically connected to the first voltage line.

[0121] In a specific implementation, the first node control circuit may include a first transistor, a second transistor, and a third transistor. The first transistor is used to control the connection between the input terminal and the first node under the control of a first clock signal. The second transistor is used to control the connection between the second electrode of the third transistor and the first node under the control of a second clock signal. The third transistor is used to control the connection between the first voltage line and the second electrode of the third transistor under the control of the potential of the third node, thereby controlling the potential of the first node.

[0122] Optionally, the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line all extend along a first direction;

[0123] The first transistor, the second transistor, and the third transistor are arranged sequentially along a first direction to save lateral space and facilitate the achievement of a narrow bezel.

[0124] In at least one embodiment of this disclosure, the first direction may be a vertical direction, but is not limited thereto.

[0125] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the second node control circuit may include a third node control sub-circuit 21, a fourth node control sub-circuit 22, and a second node control sub-circuit 23.

[0126] The third node control sub-circuit 21 is electrically connected to the third node N3, the second voltage line V2, the first clock signal terminal CK, and the first node N1, respectively. It is used to control the connection between the third node N3 and the second voltage line V2 under the control of the first clock signal, and to control the connection between the third node N3 and the first clock signal line CK under the control of the potential of the first node N1.

[0127] The fourth node control sub-circuit 22 is electrically connected to the third node N3, the second clock signal line CB and the fourth node N4 respectively, and is used to control the connection between the fourth node N4 and the second clock signal line CB under the control of the potential of the third node N3, and to control the potential of the fourth node N4 according to the potential of the third node N3.

[0128] The second node control sub-circuit 23 is electrically connected to the second clock signal line CB, the fourth node N4, the second node N2, the first node N1 and the first voltage line V1, respectively. It is used to control the connection between the second node N2 and the fourth node N4 under the control of the second clock signal, and to control the connection between the second node N2 and the first voltage line V1 under the control of the potential of the first node N1, and to maintain the potential of the second node N2.

[0129] This disclosure is as follows Figure 2 In at least one embodiment of the driving circuit shown, during operation, the third node control sub-circuit 21 controls the potential of the third node N3 under the control of the first clock signal and the potential of the first node N1; the fourth node control sub-circuit 22 controls the potential of the fourth node N4 under the control of the potential of the third node N3; and the second node control sub-circuit 23 controls the potential of the second node N2 under the control of the second clock signal and the potential of the first node N1.

[0130] Optionally, the third node control sub-circuit includes a fourth transistor and a fifth transistor;

[0131] The first gate of the fourth transistor is electrically connected to the first clock signal line, the first electrode of the fourth transistor is electrically connected to the second voltage line, and the second electrode of the fourth transistor is electrically connected to the third node.

[0132] The first gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first clock signal line, and the second electrode of the fifth transistor is electrically connected to the third node.

[0133] The fourth node control sub-circuit includes a sixth transistor and a first capacitor;

[0134] The first gate of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second clock signal line, and the second electrode of the sixth transistor is electrically connected to the fourth node;

[0135] The first plate of the first capacitor is electrically connected to the third node, and the second plate of the first capacitor is electrically connected to the fourth node;

[0136] The second node control sub-circuit includes a seventh transistor, an eighth transistor, and a second capacitor;

[0137] The first gate of the seventh transistor is electrically connected to the second clock signal line, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second node;

[0138] The first gate of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the first voltage line, and the second electrode of the eighth transistor is electrically connected to the second node;

[0139] The first plate of the second capacitor is electrically connected to the second node, and the second plate of the second capacitor is electrically connected to the first voltage line.

[0140] The output circuit includes a ninth transistor and a tenth transistor;

[0141] The first gate of the ninth transistor is electrically connected to the fourth node, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the drive signal output terminal.

[0142] The first gate of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the second voltage line, and the second electrode of the tenth transistor is electrically connected to the drive signal output terminal.

[0143] Optionally, the driving circuit further includes a third capacitor;

[0144] The first plate of the third capacitor is electrically connected to the first node, and the second plate of the third capacitor is electrically connected to the second clock signal line.

[0145] In at least one embodiment of this disclosure, the driving circuit further includes a potential control circuit;

[0146] The potential control circuit is electrically connected to the first node and is used to control the potential of the first node to be less than the control voltage threshold, so as to reduce the bias voltage of the transistor whose gate is electrically connected to the first node and prevent the threshold voltage of the transistor from drifting.

[0147] Optionally, the potential control circuit includes an eleventh transistor;

[0148] The gate of the eleventh transistor and the first electrode of the eleventh transistor are both electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the second voltage line.

[0149] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown,

[0150] The first node control circuit 11 includes a first transistor T1, a second transistor T2, and a third transistor T3;

[0151] The first gate of the first transistor T1 is electrically connected to the first clock signal line CK, the source of the first transistor T1 is electrically connected to the input terminal STV, and the drain of the first transistor T1 is electrically connected to the first node N1.

[0152] The first gate of the second transistor T2 is electrically connected to the second clock signal line CB, the source of the second transistor T2 is electrically connected to the drain of the third transistor T3, and the drain of the second transistor T2 is electrically connected to the first node N1.

[0153] The first gate of the third transistor T3 is electrically connected to the third node N3, and the source of the third transistor T3 is electrically connected to the first low voltage line VGL.

[0154] The third node control sub-circuit 21 includes a fourth transistor T4 and a fifth transistor T5;

[0155] The first gate of the fourth transistor T4 is electrically connected to the first clock signal line CK, the source of the fourth transistor T4 is electrically connected to the high voltage line VGH, and the drain of the fourth transistor T4 is electrically connected to the third node N3.

[0156] The first gate of the fifth transistor T5 is electrically connected to the first node N1, the source of the fifth transistor T5 is electrically connected to the first clock signal line CK, and the drain of the fifth transistor T5 is electrically connected to the third node N3.

[0157] The fourth node control sub-circuit 22 includes a sixth transistor T6 and a first capacitor C1;

[0158] The first gate of the sixth transistor T6 is electrically connected to the third node N3, the source of the sixth transistor T6 is electrically connected to the second clock signal line CB, and the drain of the sixth transistor T6 is electrically connected to the fourth node N4.

[0159] The first plate of the first capacitor C1 is electrically connected to the third node N3, and the second plate of the first capacitor C1 is electrically connected to the fourth node N4;

[0160] The second node control sub-circuit 23 includes a seventh transistor T7, an eighth transistor T8, and a second capacitor C2;

[0161] The first gate of the seventh transistor T7 is electrically connected to the second clock signal line CB, the source of the seventh transistor T7 is electrically connected to the fourth node N4, and the drain of the seventh transistor T7 is electrically connected to the second node N2.

[0162] The first gate of the eighth transistor T8 is electrically connected to the first node N1, the source of the eighth transistor T8 is electrically connected to the low voltage line VGL, and the drain of the eighth transistor T8 is electrically connected to the second node N2.

[0163] The first plate of the second capacitor C2 is electrically connected to the second node N2, and the second plate of the second capacitor C2 is electrically connected to the low voltage line VGL.

[0164] The output circuit 13 includes a ninth transistor T9 and a tenth transistor T10;

[0165] The first gate of the ninth transistor T9 is electrically connected to the fourth node N4, the source of the ninth transistor T9 is electrically connected to the low voltage line VGL, and the drain of the ninth transistor T9 is electrically connected to the drive signal output terminal E1.

[0166] The first gate of the tenth transistor T10 is electrically connected to the first node N1, the source of the tenth transistor T10 is electrically connected to the high voltage line VGH, and the drain of the tenth transistor T10 is electrically connected to the drive signal output terminal E1.

[0167] exist Figure 3 In at least one embodiment of the driving circuit, the first voltage line can be a low voltage line VGL, and the second voltage line can be a high voltage line VGH, but is not limited thereto.

[0168] In specific implementation, the low voltage line VGL is used to provide a low voltage signal, and the high voltage line VGH is used to provide a high voltage signal. The voltage value of the low voltage signal provided by the low voltage line VGL can be less than the voltage value of the high voltage signal provided by the high voltage line VGH, but is not limited thereto.

[0169] exist Figure 3 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors; for example, all transistors can be IGZO (indium gallium zinc oxide) transistors, but are not limited thereto; in actual operation, all transistors can also be n-type doped LTPS transistors.

[0170] exist Figure 3 In the diagram, node N5 is the fifth node.

[0171] Figure 4 yes Figure 3 The timing diagram shows the operation of at least one embodiment of the driving circuit.

[0172] like Figure 4 As shown, this disclosure is as follows Figure 3When at least one embodiment of the driving circuit shown is in operation, the display cycle may include a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7, and an eighth stage t8 set sequentially.

[0173] In the first stage t1, STV provides a low voltage signal, CK provides a high voltage signal, CB provides a low voltage signal, T4 is turned on, N3 has a high voltage potential, T1 is turned on, N1 has a low voltage potential, T6 is turned on, N4 has a low voltage potential; T3 is turned on, N5 has a low voltage potential; T7 and T8 are both turned off, N2 maintains a low voltage potential; T9 is turned off, T10 is turned on, and E1 outputs a high voltage signal.

[0174] In the second stage t2, STV provides a low voltage signal, CK provides a low voltage signal, CB provides a high voltage signal, T1 and T4 are turned off, the potential of N3 is maintained at a high voltage, T2 and T3 are both turned on so that the potential of N1 is a low voltage, T6 and T7 are turned on so that the potentials of N2 and N4 are both high voltage, the potential of N5 is a low voltage, T9 is turned on, T10 is turned off, and E1 outputs a low voltage signal.

[0175] In the third stage t3, STV provides a low voltage signal, CK provides a high voltage signal, CB provides a low voltage signal, T1 and T4 are both on, N3 is at a high voltage, T3 is on, T2 is off, N5 is at a low voltage, N1 is at a low voltage, T6 is on, T7 is off, T8 is off, N2 is maintained at a high voltage, T9 is on, T10 is off, and E1 outputs a low voltage signal.

[0176] In the fourth stage t4, STV provides a low voltage signal, CK provides a low voltage signal, CB provides a high voltage signal, T1 and T4 are turned off, N3 is at a high voltage, T2 and T3 are turned on, N1 is at a low voltage, T6 and T7 are turned on, N2 is at a high voltage, N5 is at a low voltage, T9 is turned on, T10 is turned off, and E1 outputs a low voltage signal.

[0177] In the fifth stage t5, STV provides a low voltage signal, CK provides a high voltage signal, CB provides a low voltage signal, T1 and T4 are both on, N3 is at a high voltage, T3 is on, T2 is off, N5 is at a low voltage, N1 is at a low voltage, T6 is on, T7 is off, T8 is off, N2 is maintained at a high voltage, T9 is on, T10 is off, and E1 outputs a low voltage signal.

[0178] In the sixth stage t6, STV provides a low voltage signal, CK provides a low voltage signal, CB provides a high voltage signal, T1 and T4 are off, N3 is at a high voltage, T2 and T3 are on, N1 is at a low voltage, T6 and T7 are on, N2 is at a high voltage, N5 is at a low voltage, T9 is on, T10 is off, and E1 outputs a low voltage signal.

[0179] In stage 7 t7, STV provides a high voltage signal, CK provides a high voltage signal, CB provides a low voltage signal, T1 and T4 are turned on, N1 has a high voltage potential, N3 has a high voltage potential, T5 is turned on, T2 is turned off, T3 is turned on, N5 has a low voltage potential, T7 is turned off, T8 is turned on, N2 has a low voltage potential, T9 is turned off, T10 is turned on, and E1 outputs a high voltage signal.

[0180] In stage 8 t8, STV provides a low voltage signal, CK provides a low voltage signal, CB provides a high voltage signal, T1 and T4 are off, N1 is at a high voltage, T5 is on, N3 is at a low voltage, T6 is off, T7 is on, T8 is on, N2 is at a low voltage, T9 is off, T10 is on, and E1 outputs a high voltage signal.

[0181] exist Figure 4 In the diagram, the potential of N1 is labeled Vn1, the potential of N2 is labeled Vn2, the potential of N3 is labeled Vn3, the potential of N4 is labeled Vn4, and the potential of N5 is labeled Vn5.

[0182] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the at least one embodiment of the driving circuit may further include a third capacitor C3;

[0183] The first plate of the third capacitor C3 is electrically connected to the first node N1, and the second plate of the third capacitor C3 is electrically connected to the second clock signal line CB.

[0184] Figure 6 yes Figure 5 The timing diagram shows the operation of at least one embodiment of the driving circuit.

[0185] exist Figure 6 In the diagram, the potential of N1 is labeled Vn1, the potential of N2 is labeled Vn2, the potential of N3 is labeled Vn3, the potential of N4 is labeled Vn4, and the potential of N5 is labeled Vn5.

[0186] like Figure 7 As shown, in Figure 3Based on at least one embodiment of the driving circuit shown, the at least one embodiment of the driving circuit may further include a potential control circuit 60.

[0187] The potential control circuit 60 is electrically connected to the first node N1 and is used to control the potential of the first node N1 to be less than the control voltage threshold.

[0188] The potential control circuit 60 includes an eleventh transistor T11;

[0189] The gate and source of the eleventh transistor T11 are both electrically connected to the first node N1, and the drain of the eleventh transistor T11 is electrically connected to the high voltage line VGH.

[0190] Figure 8 yes Figure 7 The timing diagram shows the operation of at least one embodiment of the driving circuit.

[0191] like Figure 7 In at least one embodiment of the driving circuit shown, when the potential of the first node N1 is greater than Vh + Vth11, T11 is turned on to control the connection between the first node N1 and the high-voltage line VGH, thereby controlling the pull-down of the potential of the first node N1 to reduce the bias voltage of T10, prevent the threshold voltage of T10 from drifting, and improve the driving effect. Here, Vth11 is the threshold voltage of T11.

[0192] like Figure 7 In at least one embodiment of the driving circuit shown, when in operation, by increasing T11, the potential of the first node N1 can be reduced from 16V to 10V when the potential of the first node N1 is high.

[0193] like Figure 9 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, T1, T2, T3, T4, T5, T6, T7, T8, T9 and T10 can all be dual-gate transistors;

[0194] The second gate of the first transistor T1 is electrically connected to the low voltage line VGL, the second gate of the second transistor T2 is electrically connected to the low voltage line VGL, and the second gate of the third transistor T3 is electrically connected to the low voltage line VGL.

[0195] The second gate of the fourth transistor T4 is electrically connected to the low voltage line VGL; the second gate of the fifth transistor T5 is electrically connected to the second gate of the tenth transistor T10; the second gate of the tenth transistor T10 is electrically connected to the drain of the tenth transistor T10.

[0196] The second gate of the sixth transistor T6 is electrically connected to the low voltage line VGL, the second gate of the seventh transistor T7 is electrically connected to the first gate of the ninth transistor T9, the second gate of the eighth transistor T8 and the second gate of the ninth transistor T9 are electrically connected, and the second gate of the ninth transistor T9 is electrically connected to the low voltage line VGL.

[0197] Figure 10 This is a circuit diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure, showing the electrodes of each transistor and the plates of each capacitor.

[0198] like Figure 10 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown,

[0199] The first node control circuit includes a first transistor T1, a second transistor T2, and a third transistor T3;

[0200] The first gate G11 of the first transistor T1 is electrically connected to the first clock signal line CK, the first electrode S1 of the first transistor T1 is electrically connected to the input terminal STV, and the second electrode D1 of the first transistor T1 is electrically connected to the second electrode D2 of the second transistor T2.

[0201] The first gate G21 of the second transistor T2 is electrically connected to the second clock signal line CB, the first electrode S2 of the second transistor T2 is electrically connected to the second electrode D3 of the third transistor T3, and the second electrode D2 of the second transistor T2 is electrically connected to the first node N1.

[0202] The first gate G31 of the third transistor T3 is electrically connected to the second electrode D2 of the second transistor T2, and the first electrode S3 of the third transistor T3 is electrically connected to the first low voltage line VGL.

[0203] The third node control sub-circuit includes a fourth transistor T4 and a fifth transistor T5;

[0204] The first gate G41 of the fourth transistor T4 is electrically connected to the first clock signal line CK, the first electrode S4 of the fourth transistor T4 is electrically connected to the high voltage line VGH, and the second electrode D4 of the fourth transistor T4 is electrically connected to the second electrode D5 of the fifth transistor T5.

[0205] The first gate G51 of the fifth transistor T5 is electrically connected to the first node N1, the first electrode S5 of the fifth transistor T5 is electrically connected to the first clock signal line CK, and the second electrode D5 of the fifth transistor T5 is electrically connected to the third node N3.

[0206] The fourth node control sub-circuit includes a sixth transistor T6 and a first capacitor C1;

[0207] The first gate G61 of the sixth transistor T6 is electrically connected to the third node N3, the source S6 of the sixth transistor T6 is electrically connected to the second clock signal line CB, and the drain D6 of the sixth transistor T6 is electrically connected to the fourth node N4.

[0208] The first plate C1a of the first capacitor C1 is electrically connected to the third node N3, and the second plate C1b of the first capacitor C1 is electrically connected to the fourth node N4.

[0209] The second node control sub-circuit includes a seventh transistor T7, an eighth transistor T8, and a second capacitor C2;

[0210] The first gate G71 of the seventh transistor T7 is electrically connected to the second clock signal line CB, the first electrode S7 of the seventh transistor T7 is electrically connected to the fourth node N4, and the second electrode D7 of the seventh transistor T7 is electrically connected to the second node N2.

[0211] The first gate G81 of the eighth transistor T8 is electrically connected to the first node N1, the first electrode S8 of the eighth transistor T8 is electrically connected to the low voltage line VGL, and the second electrode D8 of the eighth transistor T8 is electrically connected to the second node N2.

[0212] The first plate C2a of the second capacitor C2 is electrically connected to the second node N2, and the second plate C2b of the second capacitor C2 is electrically connected to the low voltage line VGL.

[0213] The output circuit 13 includes a ninth transistor T9 and a tenth transistor T10;

[0214] The first gate G91 of the ninth transistor T9 is electrically connected to the fourth node N4, the first electrode S9 of the ninth transistor T9 is electrically connected to the low voltage line VGL, and the second electrode D9 of the ninth transistor T9 is electrically connected to the drive signal output terminal E1.

[0215] The first gate G101 of the tenth transistor T10 is electrically connected to the first node N1, the first electrode S10 of the tenth transistor T10 is electrically connected to the high voltage line VGH, and the second electrode D10 of the tenth transistor T10 is electrically connected to the drive signal output terminal E1.

[0216] exist Figure 10In at least one embodiment shown, the first voltage line is a low voltage line VGL, and the second voltage line is a high voltage line VGH.

[0217] In at least one embodiment of this disclosure, the display substrate includes a semiconductor layer, a first gate metal layer, and a source / drain metal layer sequentially stacked along a direction away from the substrate.

[0218] The first gate of the first transistor and the first conductive connection portion are integral structures, and the first conductive connection portion is coupled to the first clock signal line;

[0219] The first electrode of the first transistor is coupled to the second conductive connection portion, and the second conductive connection portion is coupled to the input terminal; the second electrode of the first transistor is coupled to the third conductive connection portion, and the third conductive connection portion is coupled to the second electrode of the second transistor.

[0220] The first electrode of the third transistor is coupled to the fourth conductive connection portion, and the fourth conductive connection portion and the first voltage line are an integral structure.

[0221] The active layer of the first transistor includes a first electrode and a second electrode, the active layer of the second transistor includes a first electrode and a second electrode, and the active layer of the third transistor includes a first electrode and a second electrode.

[0222] The active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor are contained in the semiconductor layer; the first gate of the first transistor, the first gate of the second transistor, and the first gate of the third transistor are contained in the first gate metal layer; the input terminal and the first conductive connection portion are contained in the first gate metal layer; and the second conductive connection portion, the third conductive connection portion, and the fourth conductive connection portion are all contained in the source-drain metal layer.

[0223] Figure 11 yes Figure 10 The layout diagram of at least one embodiment of the driving circuit shown is as follows. Figure 12 yes Figure 11 Layout diagram of the semiconductor layer in the middle. Figure 13 yes Figure 11 Layout diagram of the first gate metal layer in the middle. Figure 14 yes Figure 11 The layout diagram of the second gate metal layer in the middle, Figure 15 yes Figure 11 The layout diagram of the first source / drain metal layer in the image.

[0224] like Figures 11-15 As shown, the first gate G11 of the first transistor T1 and the first conductive connection L1 are integral structures, and the first conductive connection L1 is coupled to the first clock signal line CK.

[0225] The first electrode S1 of the first transistor T1 is coupled to the second conductive connection L2, and the second conductive connection L2 is coupled to the input terminal STV; the second electrode D1 of the first transistor T1 is coupled to the third conductive connection L3, and the third conductive connection L3 is coupled to the second electrode D2 of the second transistor T2.

[0226] The first electrode S3 of the third transistor T3 is coupled to the fourth conductive connection L4, and the fourth conductive connection and the low voltage line VGL are an integral structure.

[0227] The active layer of the first transistor T1 includes the first electrode S1 of T1, the channel region of T1 and the second electrode D1 of T1; the active layer of the second transistor T2 includes the first electrode S2 of T2, the channel region of T2 and the second electrode D2 of T2; and the active layer of the third transistor T3 includes the first electrode S3 of T3, the channel region of T3 and the second electrode D3 of T3.

[0228] The channel area of ​​T1 is located between S1 and D1, the channel area of ​​T2 is located between S2 and D2, and the channel area of ​​T3 is located between S3 and D3.

[0229] like Figure 12 As shown, the active layer of the first transistor T1, the active layer of the second transistor T2, and the active layer of the third transistor T3 are contained within the semiconductor layer; as Figure 12 As shown, the first gate G11 of the first transistor T1, the first gate G21 of the second transistor T2, and the first gate G31 of the third transistor T3 are contained in the first gate metal layer, and the input terminal STV and the first conductive connection L1 are contained in the first gate metal layer; Figure 14 As shown, the second conductive connection portion L2, the third conductive connection portion L3, and the fourth conductive connection portion L4 are all included in the source / drain metal layer.

[0230] In at least one embodiment of this disclosure, the display substrate includes a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source / drain metal layer sequentially stacked along a direction away from the substrate.

[0231] like Figures 11-15 As shown, the first gate G41, the first conductive connection L1, and the fifth conductive connection L5 of the fourth transistor T4 are an integral structure. The first conductive connection L1 is coupled to the first clock signal line CK; the fifth conductive connection L5 is coupled to the sixth conductive connection L6; and the sixth conductive connection L6 is coupled to the first electrode S5 of the fifth transistor T5.

[0232] The first gate G21 of the second transistor T2, the first gate G71 of the seventh transistor T7, the seventh conductive connection L7, and the eighth conductive connection L8 are integral structures. The seventh conductive connection L7 is coupled to the second clock signal line CB; the eighth conductive connection L8 is coupled to the ninth conductive connection L9; the ninth conductive connection L9 is coupled to the first electrode S6 of the sixth transistor T6; the second electrode D6 of the sixth transistor T6 is coupled to the tenth conductive connection L10, and the tenth conductive connection L10 is coupled to the second plate C1b of the first capacitor C1.

[0233] The first gate G31 of the third transistor T3, the first gate G61 of the sixth transistor T6, the first plate C1b of the first capacitor C1, and the eleventh conductive connection L11 are integral structures. The eleventh conductive connection L11 is coupled to the twelfth conductive connection L12. The twelfth conductive connection L12 is coupled to the second electrode D4 of the fourth transistor T4 and the second electrode D5 of the fifth transistor T5, respectively.

[0234] The first gate G51 of the fifth transistor T5, the first gate G81 of the eighth transistor T8, the first gate of the tenth transistor T10, and the thirteenth conductive connection L13 are an integral structure; the thirteenth conductive connection L13 is coupled to the third conductive connection L3.

[0235] The first gate of the tenth transistor T10 includes a first gate pattern G111, a second gate pattern G112, a third gate pattern G113, a fourth gate pattern G114, a fifth gate pattern G115, a sixth gate pattern G116, a seventh gate pattern G117, an eighth gate pattern G118, a ninth gate pattern G119, and a tenth gate pattern G1110 that are electrically connected to each other.

[0236] The first electrode S4 of the fourth transistor T4 is coupled to the fourteenth conductive connection L14, and the fourteenth conductive connection L14 and the high voltage line VGH are an integral structure.

[0237] The first electrode S7 of the seventh transistor T7 is adjacent to and continuous with the second electrode D6 of the sixth transistor T6; the first gate of the ninth transistor T9 and the fifteenth conductive connection L15 are an integral structure.

[0238] The first gate of the ninth transistor T9 includes an eleventh gate pattern G1111, a twelfth gate pattern G1112, a thirteenth gate pattern G1113, a fourteenth gate pattern G1114, a fifteenth gate pattern G1115, a sixteenth gate pattern G1116, a seventeenth gate pattern G1117, an eighteenth gate pattern G1118, a nineteenth gate pattern G1119, and a twentieth gate pattern G1120 that are electrically connected to each other.

[0239] The second electrode D7 of the seventh transistor T7 is coupled to the sixteenth conductive connection L16, and the sixteenth conductive connection L16 is coupled to the second electrode D8 of the eighth transistor T8 and the fifteenth conductive connection L15, respectively.

[0240] The first electrode S8 of the eighth transistor T8 is coupled to the first electrode S9 of the ninth transistor T9;

[0241] The first gate of the ninth transistor T9 and the first plate C2a of the second capacitor C2 are integral structures; the second plate C2b of the second capacitor C2 is coupled to the seventeenth conductive connection L17, and the seventeenth conductive connection L17 is integral with the low voltage line VGL.

[0242] The active layer of the fourth transistor T4 includes the first electrode S4 and the second electrode D4 of T4; the active layer of the fifth transistor T5 includes the first electrode S5 and the second electrode D5 of T5; the active layer of the sixth transistor T6 includes the first electrode S6 and the second electrode D6 of T6; the active layer of the seventh transistor T7 includes the first electrode S7 and the second electrode D7 of T7; and the active layer of the eighth transistor T8 includes the first electrode S8 and the second electrode D8 of T8.

[0243] The active layers of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all contained within the semiconductor layer; the first gate G41 of the fourth transistor T4, the first gate G51 of the fifth transistor T5, the first gate G61 of the sixth transistor T6, the first gate T71 of the seventh transistor T7, and the first gate G81 of the eighth transistor T8 are all contained within the first gate metal layer; the first electrode C1a of the first capacitor C1 and the first electrode C2a of the second capacitor C2 are contained within the first gate metal layer; and the second electrode C1b of the first capacitor C1 and the second electrode C2b of the second capacitor C2 are contained within the second gate metal layer.

[0244] The first clock signal line CK, the second clock signal line CB, the low voltage line VGL, and the high voltage line VGH are all contained in the source-drain metal layer; the fifth conductive connection L5, the seventh conductive connection L7, the eighth conductive connection L8, the eleventh conductive connection L11, the thirteenth conductive connection L13, and the fifteenth conductive connection L15 are contained in the first gate metal layer; the sixth conductive connection L6, the ninth conductive connection L9, the tenth conductive connection L10, the twelfth conductive connection L12, the fourteenth conductive connection L14, the sixteenth conductive connection L16, and the seventeenth conductive connection L17 are all contained in the source-drain metal layer.

[0245] like Figure 15 As shown, the line width K1 of the low voltage line VGL is greater than the line width K2 of the high voltage line VGH;

[0246] The line width K3 of the first clock signal line CK is greater than the line width K2 of the high voltage line VGH;

[0247] The line width K4 of the second clock signal line CB is greater than the line width K2 of the high voltage line VGH;

[0248] The line width K0 of the starting signal line E0 is less than the line width K1 of the low voltage line VGL, and the line width K0 of the starting signal line E0 is less than the line width K3 of the first clock signal line CK, and the line width K0 of the starting signal line E0 is less than the line width K4 of the second clock signal line CB.

[0249] However, this is not the limit.

[0250] In at least one embodiment of this disclosure, the tenth transistor and the ninth transistor are arranged along a first direction; the active layer of the ninth transistor and the active layer of the tenth transistor are continuous with each other;

[0251] The first electrode of the tenth transistor, the second electrode of the tenth transistor, the first electrode of the ninth transistor, and the second electrode of the ninth transistor are all contained in the source / drain metal layer;

[0252] The first gate of the tenth transistor and the first gate of the ninth transistor are both contained in the first gate metal layer;

[0253] The first electrode of the tenth transistor, the fourteenth conductive connection portion, and the second voltage line are an integral structure;

[0254] The second electrode of the tenth transistor and the second electrode of the ninth transistor are integral structures; the second electrode of the ninth transistor is coupled to the drive signal output terminal, which is contained in the first gate metal layer;

[0255] The first electrode of the ninth transistor and the first voltage line are an integral structure.

[0256] like Figures 11-15 As shown, the active layer of the ninth transistor T9 includes a first active portion A1 and a second active portion A2, and the active layer of the tenth transistor T10 includes a third active portion A3 and a fourth active portion A4; the first active portion A1 and the third active portion A3 are continuous with each other, and the second active portion A2 and the fourth active portion A4 are continuous with each other.

[0257] The first electrode S10 of the tenth transistor T10, the second electrode D10 of the tenth transistor T10, the first electrode S9 of the ninth transistor T9, and the second electrode D9 of the ninth transistor T9 are all contained in the source and drain metal layer;

[0258] The first gate of the tenth transistor T10 and the first gate of the ninth transistor T9 are both contained in the first gate metal layer;

[0259] The first electrode S10 of the tenth transistor T10, the fourteenth conductive connection L14 and the high voltage line VGH are an integral structure;

[0260] The second electrode D10 of the tenth transistor T10 and the second electrode D9 of the ninth transistor T9 are integral structures; the second electrode D9 of the ninth transistor T9 is coupled to the drive signal output terminal E1, and the drive signal output terminal E1 is contained in the first gate metal layer.

[0261] The first electrode S9 of the ninth transistor T9 and the low voltage line VGL are integrally structured.

[0262] like Figures 11-15 As shown, the active layers of the ninth transistor T9 and the tenth transistor T10 are composed of two active portions. One active portion includes a first active portion A1 and a third active portion A3 that are continuously connected, and the other active portion includes a second active portion A2 and a fourth active portion A4 that are continuously connected. In actual operation, to prevent heat dissipation and other problems caused by an excessively large active portion, the active layers of the ninth transistor T9 and the tenth transistor T10 can be configured to consist of at least two active portions.

[0263] exist Figure 11 and Figure 15 In the diagram, the line labeled E0 is the start signal line.

[0264] In at least one embodiment of this disclosure, the first transistor, the second transistor, and the third transistor may all be dual-gate transistors;

[0265] The second gate of the first transistor is electrically connected to the first voltage line, the second gate of the second transistor is electrically connected to the first voltage line, and the second gate of the third transistor is electrically connected to the first voltage line;

[0266] The display substrate further includes a light-shielding layer disposed between the substrate and the semiconductor layer, wherein the second gate of the first transistor, the second gate of the second transistor, and the second gate of the third transistor are all contained in the light-shielding layer.

[0267] In a specific implementation, the light-blocking layer is also used to block light; the first gate is a top gate, and the second gate is a bottom gate.

[0268] like Figure 16 and Figure 18 As shown, the first transistor T1, the second transistor T2, and the third transistor T3 are all dual-gate transistors;

[0269] The second gate G12 of the first transistor T1 is electrically connected to the low voltage line VGL, the second gate G22 of the second transistor T2 is electrically connected to the low voltage line VGL, and the second gate G32 of the third transistor T3 is electrically connected to the low voltage line VGL.

[0270] like Figure 18 As shown, the display substrate may further include a light-shielding layer disposed between the substrate and the semiconductor layer, wherein the second gate G12 of the first transistor T1, the second gate G22 of the second transistor T2 and the second gate G32 of the third transistor T3 are all contained in the light-shielding layer.

[0271] Figure 17 Is Figure 11 The layout diagram shows at least one embodiment of the driving circuit with an added light-blocking layer. Figure 18 yes Figure 17 The layout diagram of the light-blocking layer in the image. Figure 17 In the diagram, the line labeled E0 is the start signal line.

[0272] Optionally, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all dual-gate transistors;

[0273] The second gate of the fourth transistor is electrically connected to the first voltage line, and the second gate of the fifth transistor is electrically connected to the second gate of the tenth transistor; the second gate of the tenth transistor is electrically connected to the second electrode of the tenth transistor.

[0274] The second gate of the sixth transistor is electrically connected to the first voltage line, and the second gate of the seventh transistor is electrically connected to the first gate of the ninth transistor; the second gate of the eighth transistor and the second gate of the ninth transistor are electrically connected, and the second gate of the ninth transistor is electrically connected to the first voltage line.

[0275] The second gates of the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all contained within the light-shielding layer.

[0276] like Figure 16 and Figure 18 As shown, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all dual-gate transistors;

[0277] The second gate G42 of the fourth transistor T4 is electrically connected to the low voltage line VGL, the second gate G52 of the fifth transistor T5 is electrically connected to the second gate G102 of the tenth transistor T10, and the second gate G102 of the tenth transistor T10 is electrically connected to the second electrode D10 of the tenth transistor T10.

[0278] The second gate G62 of the sixth transistor T6 is electrically connected to the low voltage line VGL; the second gate G72 of the seventh transistor T7 is electrically connected to the first gate G91 of the ninth transistor T9; the second gate G82 of the eighth transistor T8 and the second gate G92 of the ninth transistor T9 are electrically connected; and the second gate G92 of the ninth transistor T9 is electrically connected to the low voltage line VGL.

[0279] like Figure 18 As shown, the second gate G42 of the fourth transistor T4, the second gate G52 of the fifth transistor T5, the second gate G62 of the sixth transistor T6, the second gate G72 of the seventh transistor T7, the second gate G82 of the eighth transistor T8, the second gate of the ninth transistor T9, and the second gate of the tenth transistor T10 are all included in the light-shielding layer.

[0280] like Figure 18As shown, the second gate of the tenth transistor T10 includes a twenty-first gate pattern G1121, a twenty-second gate pattern G1122, a twenty-third gate pattern G1123, a twenty-fourth gate pattern G1124, a twenty-fifth gate pattern G1125, a twenty-sixth gate pattern G1126, a twenty-seventh gate pattern G1127, a twenty-eighth gate pattern G1128, a twenty-ninth gate pattern G1129, and a thirtieth gate pattern G1130 that are electrically connected to each other.

[0281] The second gate of the ninth transistor T9 includes three gate patterns that are electrically connected to each other: the thirty-first gate pattern G1131, the thirty-second gate pattern G1132, the thirty-third gate pattern G1133, the thirty-fourth gate pattern G1134, the thirty-fifth gate pattern G1135, the thirty-sixth gate pattern G1136, the thirty-seventh gate pattern G1137, the thirty-eighth gate pattern G1138, the thirty-ninth gate pattern G1139, and the fortieth gate pattern G1140.

[0282] Figure 19 Is Figure 11 A schematic diagram showing at least one embodiment of the display substrate with an added eleventh transistor.

[0283] Figure 20 yes Figure 19 The structure diagram of the semiconductor layer in the diagram is shown. Figure 20 In the diagram, S11 is the source of the eleventh transistor T11, and D11 is the drain of the eleventh transistor T11. The drain of T11, D11, is electrically connected to the high-voltage line VGH through a via.

[0284] Figure 21 yes Figure 19 The structural diagram of the first gate metal layer in the image. Figure 21 In the diagram, G11 is the gate of the eleventh transistor T11; the gate G11 of T11 is electrically connected to the first gate of T10.

[0285] Figure 22 yes Figure 19 The structural diagram of the source / drain metal layers. Figure 22 In the diagram, L18 is the eighteenth conductive connection part; L18 is electrically connected to the source S11 of T11 and the first gate of T10 through vias.

[0286] The display device described in this disclosure includes the display substrate described above.

[0287] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0288] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display substrate, characterized in that, The device includes a driving circuit disposed on a substrate, the driving circuit comprising a first node control circuit, a second node control circuit, and an output circuit. The first node control circuit is electrically connected to the first node, the input terminal, the first clock signal line, the second clock signal line, the third node, and the first voltage line, respectively. It is used to control the potential of the first node according to the input signal provided by the input terminal and the first voltage signal provided by the first voltage line under the control of the first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, and the potential of the third node. The second node control circuit is electrically connected to the second node and the third node respectively, and is used to control the potential of the second node and the potential of the third node; The output circuit is electrically connected to the first node, the second node, the drive signal output terminal, the first voltage line, and the second voltage line, respectively, and is used to control the connection between the drive signal output terminal and the second voltage line under the control of the potential of the first node, and to control the connection between the drive signal output terminal and the first voltage line under the control of the potential of the second node. The transistors included in the output circuit are disposed on the side of the second voltage line away from the display area; the transistors included in the first node control circuit and the second node control circuit are disposed on the side of the transistors included in the output circuit away from the second voltage line; the first voltage line, the first clock signal line, and the second clock signal line are disposed on the side of the transistors included in the first node control circuit away from the second voltage line.

2. The display substrate as described in claim 1, characterized in that, The transistors included in the second node control circuit are disposed between the transistors included in the first node control circuit and the transistors included in the output circuit.

3. The display substrate as described in claim 1, characterized in that, The first node control circuit includes a first transistor, a second transistor, and a third transistor; The first gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the first node. The first gate of the second transistor is electrically connected to the second clock signal line, the first electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the first node; The first gate of the third transistor is electrically connected to the third node, and the first electrode of the third transistor is electrically connected to the first voltage line.

4. The display substrate as described in claim 3, characterized in that, The first voltage line, the second voltage line, the first clock signal line, and the second clock signal line all extend along a first direction; The first transistor, the second transistor, and the third transistor are arranged sequentially along a first direction.

5. The display substrate as described in claim 3, characterized in that, The second node control circuit includes a third node control sub-circuit, a fourth node control sub-circuit, and a second node control sub-circuit. The third node control sub-circuit is electrically connected to the third node, the second voltage line, the first clock signal terminal, and the first node, respectively, and is used to control the connection between the third node and the second voltage line under the control of the first clock signal, and to control the connection between the third node and the first clock signal line under the control of the potential of the first node. The fourth node control sub-circuit is electrically connected to the third node, the second clock signal line and the fourth node respectively, and is used to control the connection between the fourth node and the second clock signal line under the control of the potential of the third node, and to control the potential of the fourth node according to the potential of the third node. The second node control sub-circuit is electrically connected to the second clock signal line, the fourth node, the second node, the first node, and the first voltage line, respectively. It is used to control the connection between the second node and the fourth node under the control of the second clock signal, and to control the connection between the second node and the first voltage line under the control of the potential of the first node, and to maintain the potential of the second node.

6. The display substrate as described in claim 5, characterized in that, The third node control sub-circuit includes a fourth transistor and a fifth transistor; The first gate of the fourth transistor is electrically connected to the first clock signal line, the first electrode of the fourth transistor is electrically connected to the second voltage line, and the second electrode of the fourth transistor is electrically connected to the third node. The first gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first clock signal line, and the second electrode of the fifth transistor is electrically connected to the third node. The fourth node control sub-circuit includes a sixth transistor and a first capacitor; The first gate of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second clock signal line, and the second electrode of the sixth transistor is electrically connected to the fourth node; The first plate of the first capacitor is electrically connected to the third node, and the second plate of the first capacitor is electrically connected to the fourth node; The second node control sub-circuit includes a seventh transistor, an eighth transistor, and a second capacitor; The first gate of the seventh transistor is electrically connected to the second clock signal line, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second node; The first gate of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the first voltage line, and the second electrode of the eighth transistor is electrically connected to the second node; The first plate of the second capacitor is electrically connected to the second node, and the second plate of the second capacitor is electrically connected to the first voltage line. The output circuit includes a ninth transistor and a tenth transistor; The first gate of the ninth transistor is electrically connected to the fourth node, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the drive signal output terminal. The first gate of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the second voltage line, and the second electrode of the tenth transistor is electrically connected to the drive signal output terminal.

7. The display substrate as described in claim 3, characterized in that, The display substrate includes a semiconductor layer, a first gate metal layer, and a source / drain metal layer sequentially stacked along a direction away from the substrate. The first gate of the first transistor and the first conductive connection portion are integral structures, and the first conductive connection portion is coupled to the first clock signal line; The first electrode of the first transistor is coupled to the second conductive connection portion, and the second conductive connection portion is coupled to the input terminal; the second electrode of the first transistor is coupled to the third conductive connection portion, and the third conductive connection portion is coupled to the second electrode of the second transistor. The first electrode of the third transistor is coupled to the fourth conductive connection portion, and the fourth conductive connection portion and the first voltage line are an integral structure. The active layer of the first transistor includes a first electrode and a second electrode, the active layer of the second transistor includes a first electrode and a second electrode, and the active layer of the third transistor includes a first electrode and a second electrode. The active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor are contained in the semiconductor layer; the first gate of the first transistor, the first gate of the second transistor, and the first gate of the third transistor are contained in the first gate metal layer; the input terminal and the first conductive connection portion are contained in the first gate metal layer; and the second conductive connection portion, the third conductive connection portion, and the fourth conductive connection portion are all contained in the source-drain metal layer.

8. The display substrate as described in claim 6, characterized in that, The display substrate includes a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source / drain metal layer sequentially stacked along a direction away from the substrate. The first gate, first conductive connection portion, and fifth conductive connection portion of the fourth transistor are integral structures. The first conductive connection portion is coupled to the first clock signal line; the fifth conductive connection portion is coupled to the sixth conductive connection portion; and the sixth conductive connection portion is coupled to the first electrode of the fifth transistor. The first gate of the second transistor, the first gate of the seventh transistor, the seventh conductive connection portion, and the eighth conductive connection portion are integral structures. The seventh conductive connection portion is coupled to the second clock signal line; the eighth conductive connection portion is coupled to the ninth conductive connection portion; the ninth conductive connection portion is coupled to the first electrode of the sixth transistor; the second electrode of the sixth transistor is coupled to the tenth conductive connection portion, and the tenth conductive connection portion is coupled to the second plate of the first capacitor. The first gate of the third transistor, the first gate of the sixth transistor, the first plate of the first capacitor, and the eleventh conductive connection are integral structures, and the eleventh conductive connection is coupled to the twelfth conductive connection; the twelfth conductive connection is coupled to the second electrode of the fourth transistor and the second electrode of the fifth transistor, respectively. The first gate of the fifth transistor, the first gate of the eighth transistor, the first gate of the tenth transistor, and the thirteenth conductive connection portion are an integral structure; the thirteenth conductive connection portion is coupled to the third conductive connection portion. The first electrode of the fourth transistor is coupled to the fourteenth conductive connection, and the fourteenth conductive connection and the second voltage line are an integral structure; The first electrode of the seventh transistor is adjacent to and continuous with the second electrode of the sixth transistor; the first gate of the ninth transistor and the fifteenth conductive connection portion are integral structures. The second electrode of the seventh transistor is coupled to the sixteenth conductive connection portion, and the sixteenth conductive connection portion is coupled to the second electrode of the eighth transistor and the fifteenth conductive connection portion, respectively; The first electrode of the eighth transistor is coupled to the first electrode of the ninth transistor; The first gate of the ninth transistor and the first plate of the second capacitor are integrally formed; the second plate of the second capacitor is coupled to the seventeenth conductive connection, and the seventeenth conductive connection is integrally formed with the first voltage line. The active layer of the fourth transistor includes a first electrode and a second electrode; the active layer of the fifth transistor includes a first electrode and a second electrode; the active layer of the sixth transistor includes a first electrode and a second electrode; the active layer of the seventh transistor includes a first electrode and a second electrode; and the active layer of the eighth transistor includes a first electrode and a second electrode. The active layers of the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all contained within the semiconductor layer; the first gates of the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all contained within the first gate metal layer; the first plates of the first capacitor and the second capacitor are contained within the first gate metal layer; and the second plates of the first capacitor and the second capacitor are contained within the second gate metal layer. The first clock signal line, the second clock signal line, the first voltage line, and the second voltage line are all contained in the source-drain metal layer; the fifth conductive connection, the seventh conductive connection, the eighth conductive connection, the eleventh conductive connection, the thirteenth conductive connection, and the fifteenth conductive connection are contained in the first gate metal layer; and the sixth conductive connection, the ninth conductive connection, the tenth conductive connection, the twelfth conductive connection, the fourteenth conductive connection, the sixteenth conductive connection, and the seventeenth conductive connection are all contained in the source-drain metal layer.

9. The display substrate as described in claim 8, characterized in that, The tenth transistor and the ninth transistor are arranged along a first direction; the active layer of the ninth transistor and the active layer of the tenth transistor are continuous with each other; The first electrode of the tenth transistor, the second electrode of the tenth transistor, the first electrode of the ninth transistor, and the second electrode of the ninth transistor are all contained in the source / drain metal layer; The first gate of the tenth transistor and the first gate of the ninth transistor are both contained in the first gate metal layer; The first electrode of the tenth transistor, the fourteenth conductive connection portion, and the second voltage line are an integral structure; The second electrode of the tenth transistor and the second electrode of the ninth transistor are integral structures; the second electrode of the ninth transistor is coupled to the drive signal output terminal, which is contained in the first gate metal layer; The first electrode of the ninth transistor and the first voltage line are an integral structure.

10. The display substrate as claimed in claim 8, characterized in that, The first transistor, the second transistor, and the third transistor are all dual-gate transistors; The second gate of the first transistor is electrically connected to the first voltage line, the second gate of the second transistor is electrically connected to the first voltage line, and the second gate of the third transistor is electrically connected to the first voltage line; The display substrate further includes a light-shielding layer disposed between the substrate and the semiconductor layer, wherein the second gate of the first transistor, the second gate of the second transistor, and the second gate of the third transistor are all contained in the light-shielding layer.

11. The display substrate as claimed in claim 10, characterized in that, The fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all dual-gate transistors; The second gate of the fourth transistor is electrically connected to the first voltage line, and the second gate of the fifth transistor is electrically connected to the second gate of the tenth transistor; the second gate of the tenth transistor is electrically connected to the second electrode of the tenth transistor. The second gate of the sixth transistor is electrically connected to the first voltage line, and the second gate of the seventh transistor is electrically connected to the first gate of the ninth transistor; the second gate of the eighth transistor and the second gate of the ninth transistor are electrically connected, and the second gate of the ninth transistor is electrically connected to the first voltage line. The second gates of the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all contained within the light-shielding layer.

12. The display substrate as claimed in claim 1, characterized in that, The driving circuit also includes a third capacitor; The first plate of the third capacitor is electrically connected to the first node, and the second plate of the third capacitor is electrically connected to the second clock signal line.

13. The display substrate as claimed in claim 1, characterized in that, The driving circuit also includes a potential control circuit; The potential control circuit is electrically connected to the first node and is used to control the potential of the first node to be less than the control voltage threshold.

14. The display substrate as claimed in claim 13, characterized in that, The potential control circuit includes an eleventh transistor; The gate of the eleventh transistor and the first electrode of the eleventh transistor are both electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the second voltage line.

15. The display substrate according to any one of claims 1 to 14, characterized in that, All transistors in the driving circuit are n-type transistors.

16. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 15.

Images