Calibration chip and calibration chip set
By designing a calibration chip suitable for test fixtures, the problem of needing to de-embed test results in existing technologies is solved, enabling direct calibration without de-embedding, improving test accuracy and simplifying the test process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANTONG MILEWEI MICROELECTRONICS TECH CO LTD
- Filing Date
- 2022-12-09
- Publication Date
- 2026-05-29
AI Technical Summary
In existing technologies, when testing chips using a vector network analyzer, the test results need to be de-embedded to remove errors introduced by the test fixture. This results in test results that are not intuitive and whose accuracy is unpredictable. Furthermore, existing de-embedded methods cannot effectively remove errors introduced by the test slot and the interposer layer.
Design calibration chips suitable for test fixtures, including short-circuit, open-circuit, matched-load, and through-calibration chips. By transferring the calibration reference surface to the connection point of the test fixture, de-embedding is avoided. The calibration chip is the same size as the chip under test and has a specific metal and dielectric layer structure to achieve accurate calibration.
The actual performance of the chip under test can be obtained directly without de-embedding, simplifying the testing process and improving testing accuracy, and directly calibrating the RF performance of the chip.
Smart Images
Figure CN117518056B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip testing, and more particularly to a short-circuit calibration chip, an open-circuit calibration chip, a matched load calibration chip, a through-circuit calibration chip, and a calibration chip set including the short-circuit calibration chip, the open-circuit calibration chip, the matched load calibration chip, and the through-circuit calibration chip. Background Technology
[0002] Network analyzers are the most commonly used instruments for circuit testing. Modern vector network analyzers (VNAs) can test almost all the major parameters of a circuit.
[0003] Before using vector network detectors (VND) for testing, calibration is required. The calibration kits used are usually provided by the VND manufacturer and include short, open, load, and through components. These kits work in conjunction with the VND's built-in calibration software to complete the calibration of the entire testing system.
[0004] During vector network calibration, both ends of the calibration piece are connected to the test cable of the vector network analyzer. After calibration, the device under test is then connected to the test cable for radio frequency parameter (S-parameter) testing.
[0005] When a chip under test (DUT) is tested, it is typically mounted in a test fixture. The test fixture includes an evaluation circuit board, interposer, test slots, and a cover plate. Therefore, the scope of the DUT tested by a vector network analyzer usually encompasses both the DUT and the test fixture. This results in the RF parameters measured by the vector network analyzer including errors introduced by the test fixture. Therefore, existing technologies require the removal of these errors when obtaining the RF parameters of the DUT; this process is called "de-embedding."
[0006] A common de-embedding method is the through-line frequency response calibration method. The length of the through-line is the length of the test board minus the length of the chip under test (DUT). De-embedding the DUT involves subtracting the insertion loss of the through-line from the test results along with the test fixture; this is a scalar de-embedding method. This method only de-embeddings the evaluation circuit board portion of the test fixture and does not consider the errors introduced by the test slot and interposer, nor does it consider the effects of reflected power and phase changes generated by the test slot and interposer. It is only suitable for testing devices with low test frequencies and low accuracy requirements.
[0007] Another common de-embedding method is the TRL (Thru, Reflect, Line) calibration method. This method uses three calibrators (a reflection calibrator, a direct calibrator, and a transmission line calibrator) to perform four calibration tests to obtain the embedding network parameters of the test fixture. This de-embedding method is a vector de-embedding method, and its embedding network parameters include both amplitude and phase information. However, similarly, this method only de-embeddings the PCB board portion of the test fixture.
[0008] The above-described de-embedding method is called the indirect calibration method. The indirect calibration method has several limitations:
[0009] (1) The test results cannot be reflected intuitively and in real time on the test curve. The test curve needs to be "de-embedded" to obtain the true device specifications.
[0010] (2) The accuracy of the actual device performance test depends on the accuracy of the de-embedding test, and its error value is often unpredictable. Summary of the Invention
[0011] Purpose of the invention: To address the problems of the aforementioned indirect calibration methods, this invention designs a calibration chip suitable for test fixtures. This chip can transfer the calibration reference surface to the connection point between the test fixture and the pin of the chip under test, thereby fundamentally avoiding the calculation errors caused by the de-embedding process.
[0012] Technical solution: A short-circuit calibration chip for calibrating the radio frequency performance of a chip under test. The short-circuit calibration chip has the same size as the chip under test, and the test pins of the short-circuit calibration chip are short-circuited to its ground metal layer.
[0013] Furthermore, the short-circuit calibration chip includes a dielectric substrate, the bottom surface of which is fully metallized to serve as the ground metal layer, and the test pins of the short-circuit calibration chip are metal at any position on the bottom surface.
[0014] An open-circuit calibration chip is provided for calibrating the radio frequency performance of a chip under test. The open-circuit calibration chip has the same size as the chip under test, and the test pins of the open-circuit calibration chip are open-circuited with their ground metal layer.
[0015] Furthermore, the open-circuit calibration chip includes a dielectric substrate, the bottom surface of which is arranged with a grounding area and a plurality of pin areas. The grounding area is covered with a metal layer as the grounding metal layer, and the plurality of pin areas are covered with a metal layer as the plurality of test pins. Any two of the grounding metal layer and the plurality of test pins are insulated from each other through the dielectric substrate.
[0016] Furthermore, the bottom surface of the dielectric substrate is metallized to form the grounding metal layer and the plurality of test pins.
[0017] Furthermore, the dimensions of the printed circuit are calculated by optimizing the external dimensions and pin dimensions of the chip under test. The optimization objective is that the open-circuit calibration chip satisfies the S-parameter < 0.3dB within the operating frequency band of the chip under test.
[0018] A matching load calibration chip is provided for calibrating the radio frequency performance of a chip under test (DUT). The matching load calibration chip has the same size as the DUT, and the test pins of the matching load calibration chip are connected to its ground metal layer through a load resistor.
[0019] Furthermore, the matching load calibration chip includes a dielectric substrate, the bottom surface of which is arranged with a ground area and a plurality of pin areas. The ground area is covered with a metal layer as the ground metal layer, and the plurality of pin areas are covered with a metal layer as the test pins. The ground metal layer and the test pins are insulated from each other by the dielectric substrate. The load resistor of any test pin is set on the insulated area between the test pin and the ground metal layer and is connected across the test pin and the ground metal layer.
[0020] Furthermore, the load resistor is a thin-film process sheet resistance; and / or the load resistor of any test pin is two thin-film process sheet resistances connected in parallel, the two thin-film process sheet resistances being respectively disposed on both sides of the test pin.
[0021] Furthermore, the dimensions of the printed circuit are calculated by optimizing the outline dimensions and pin dimensions of the chip under test. The optimization objective is that the matched load calibration chip satisfies the S-parameter S11>-20dB within the operating frequency band of the chip under test.
[0022] A through-through calibration chip is provided for calibrating the radio frequency performance of a chip under test (DUT). The through-through calibration chip has the same size as the DUT, and any two test pins of the through-through calibration chip that have a through-through relationship are electrically connected.
[0023] Furthermore, the through calibration chip includes a first metal layer, a first dielectric layer, and a second metal layer. The first metal layer and the second metal layer respectively cover two opposite surfaces of the first dielectric layer. The first metal layer includes a ground metal area and multiple test pins. The ground metal area and any two of the multiple test pins are insulated from each other through the first dielectric layer. The multiple test pins include N through groups with through relationships, where N≥1. Each through group includes two test pins. The second metal layer includes N through microstrip lines corresponding one-to-one with the N through groups. At least 2N metal vias are provided on the first dielectric layer. Each test pin in a through group corresponds to at least one metal via. Two test pins in any through group pass through the corresponding metal vias and are connected to the two ends of the through microstrip line corresponding to the through group through the first dielectric layer.
[0024] Furthermore, the through calibration chip also includes a second dielectric layer and a third metal layer. The first metal layer, the first dielectric layer, the second metal layer, the second dielectric layer, and the third metal layer are stacked sequentially. The first dielectric layer and the second dielectric layer are also provided with N+1 corresponding metal channels. The metal channels are insulated from the metal vias. The grounding metal area is electrically connected to the third metal layer through the metal channels. The N+1 metal channels are spaced apart from the N through microstrip lines to isolate each through microstrip line individually.
[0025] Furthermore, the dimensions of the printed circuit of the through calibration chip are calculated by optimizing the external dimensions and pin dimensions of the chip under test. The optimization objective is that the through calibration chip satisfies the S-parameters S11<-20dB and S22<-20dB within the operating frequency band of the chip under test.
[0026] A calibration chipset is disclosed for calibrating the radio frequency performance of a chip under test (DUT). The calibration chipset includes a short-circuit calibration chip, an open-circuit calibration chip, a matched-load calibration chip, and a through-circuit calibration chip. The size of any one of the calibration chips in the chipset is the same as that of the DUT.
[0027] The test pin of the short-circuit calibration chip is short-circuited to its own ground metal layer;
[0028] The test pin of the open-circuit calibration chip is open-circuited with its own ground metal layer;
[0029] The test pins of the matching load calibration chip are connected to its own grounded metal layer through a load resistor;
[0030] The through calibration chip is electrically connected between any two test pins that have a through relationship.
[0031] Furthermore, the short-circuit calibration chip includes a dielectric substrate, the bottom surface of which is fully metallized to serve as the ground metal layer of the short-circuit calibration chip, and the test pins of the short-circuit calibration chip are metal at any position on the bottom surface.
[0032] Furthermore, the open-circuit calibration chip includes a dielectric substrate, on the bottom surface of which a grounding area and a plurality of pin areas are arranged. The grounding area is covered with a metal layer as the grounding metal layer of the open-circuit calibration chip, and the plurality of pin areas are covered with a metal layer as a plurality of test pins of the open-circuit calibration chip. Any two of the grounding metal layer and the plurality of test pins of the open-circuit calibration chip are insulated from each other by the dielectric substrate.
[0033] Furthermore, the matching load calibration chip includes a dielectric substrate. The bottom surface of the dielectric substrate has a grounding area and a plurality of pin areas. The grounding area is covered with a metal layer as the grounding metal layer of the matching load calibration chip. The plurality of pin areas are covered with a metal layer as the test pins of the matching load calibration chip. The grounding metal layer and the test pins are insulated from each other by the dielectric substrate. The load resistor of any test pin is set on the insulated area between the test pin and the grounding metal layer and is connected across the test pin and the grounding metal layer.
[0034] Furthermore, the load resistance is the sheet resistance of a thin-film process; and / or
[0035] The load resistor of any test pin is two thin-film process sheet resistors connected in parallel, and the two thin-film process sheet resistors are respectively set on both sides of the test pin.
[0036] Furthermore, the through calibration chip includes a first metal layer, a first dielectric layer, and a second metal layer. The first metal layer and the second metal layer respectively cover two opposite surfaces of the first dielectric layer. The first metal layer includes a ground metal area and multiple test pins. The ground metal area and any two of the multiple test pins are insulated from each other through the first dielectric layer. The multiple test pins include N through groups with through relationships, where N≥1. Each through group includes two test pins. The second metal layer includes N through microstrip lines corresponding one-to-one with the N through groups. The first dielectric layer is provided with at least 2N metal vias. Each test pin in a through group corresponds to at least one metal via. Two test pins in any through group pass through the corresponding metal vias and are connected to the two ends of the through microstrip line corresponding to the through group through the first dielectric layer.
[0037] Furthermore, the through calibration chip also includes a second dielectric layer and a third metal layer. The first metal layer, the first dielectric layer, the second metal layer, the second dielectric layer, and the third metal layer are stacked sequentially. The first dielectric layer and the second dielectric layer are also provided with N+1 corresponding metal channels. The metal channels are insulated from the metal vias. The grounding metal area is electrically connected to the third metal layer through the metal channels. The N+1 metal channels are spaced apart from the N through microstrip lines to isolate each through microstrip line individually.
[0038] Furthermore, the printed circuit dimensions on the open-circuit calibration chip, the matched load calibration chip, and the through-circuit calibration chip are obtained by optimizing the external dimensions and pin dimensions of the chip under test. The optimization objectives are as follows: the open-circuit calibration chip satisfies S-parameter < 0.3dB in the operating frequency band of the chip under test; the matched load calibration chip satisfies S-parameter S11 > -20dB in the operating frequency band of the chip under test; and the through-circuit calibration chip satisfies S-parameters S11 < -20dB and S22 < -20dB in the operating frequency band of the chip under test.
[0039] Beneficial effects: The calibration chip and its chipset provided by this invention transfer the calibration surface from the test cable port of the vector network analyzer in the prior art to the test end face in the test fixture during the calibration process. Therefore, no de-embedding process is required, and the actual performance of the chip under test can be obtained directly, which greatly simplifies the testing process and data processing process, and improves the testing accuracy. Attached Figure Description
[0040] Figure 1 (a)~1(c) are schematic diagrams of the external shape of the chip under test in an embodiment of the present invention;
[0041] Figure 2 (a)~2(c) are the three views of the short-circuit calibration chip described in Embodiment 1 of the present invention;
[0042] Figure 3 (a)~3(c) are the three views of the open-circuit calibration chip described in Embodiment 2 of the present invention;
[0043] Figure 4 (a)~4(c) are the three views of the matching load calibration chip described in Embodiment 3 of the present invention;
[0044] Figure 5 (a)~5(d) are the three-view drawings and side sectional views of the through calibration chip described in Embodiment 4 of the present invention;
[0045] Figure 6 (a)~6(e) are the three-view drawing, side sectional view and layer sectional view of the through calibration chip described in Embodiment 5 of the present invention;
[0046] Figure 7 This is an exploded view of the chip testing equipment to which the calibration chip described in this invention is applicable. Detailed Implementation
[0047] The technical solution of the present invention will be further described below with reference to the accompanying drawings.
[0048] Figure 1 This is the package outline of the standard QFN4x4-24L chip, with a side length of 4mm. Its chip structure, pin arrangement, and numbering are as follows: Figure 1 As shown in (a)~1(c).
[0049] The following is based on Figure 1 The calibration chip for this type of chip is illustrated using the packaged chip shown as an example. It can be understood that the calibration chip is designed for the target test chip, and therefore has the same size and similar pin arrangement as the target test chip.
[0050] Example 1:
[0051] against Figure 1 The top and bottom surfaces and one side of the short-circuit calibration chip designed for the packaged chip shown are as follows: Figure 2 As shown in (a) to 2(c), the RF performance of the chip under test is calibrated, and the size of the short-circuit calibration chip is the same as that of the chip under test. Figure 2 The dimensions of the short-circuit calibration chip shown are similar to Figure 1 The target test chip shown is the same (i.e., 4*4mm), and the test pin of the short-circuit calibration chip is short-circuited to its ground metal layer.
[0052] More specifically, the short-circuit calibration chip includes a dielectric substrate N1, the bottom surface of which is completely metallized, and the resulting metal layer is the ground metal layer M1 of the short-circuit calibration chip. The test pins of the short-circuit calibration chip are any metal at any position of this metal layer, that is, the ground metal layer M1 can also be regarded as a test pin.
[0053] Example 2:
[0054] against Figure 1 The top and bottom surfaces and one side of the open-circuit calibration chip designed for the packaged chip shown are as follows: Figure 3 As shown in (a)~3(c), the open-circuit calibration chip is used to calibrate the radio frequency performance of the chip under test. The size of the open-circuit calibration chip is the same as that of the chip under test (i.e., 4*4mm), and the test pin of the open-circuit calibration chip is open-circuited with its ground metal layer.
[0055] More specifically, the open-circuit calibration chip includes a dielectric substrate N2, on the bottom surface of which a grounding area and several pin areas are arranged. The grounding area is covered with a metal layer as a grounding metal layer M2, and the several pin areas are covered with a metal layer as several test pins (Pin). Figure 3 In one specific embodiment shown, six pins (Pin1~Pin6) are provided. Any two of the grounding metal layer and several test pins are insulated from each other by a dielectric substrate (i.e., Figure 3 The grounding metal layer M2 and any one of Pin1 to Pin6 are separated by a spacer N21.
[0056] Furthermore, the bottom surface of the dielectric substrate N2 is metallized to form a grounding metal layer M2 and several test pins, with the portion not covered by metal forming the spacer area N21. Preferably, as follows... Figure 3 As shown in (c), the interval region N21 is shaped like a "π".
[0057] It is understandable that the number of test pins on the open-circuit calibration chip can be planned according to the pin layout of the general-purpose chip corresponding to the chip under test, and it must at least cover the input and output pins of the chip under test. Preferably, the test pins on the open-circuit calibration chip can also cover the input and output pins of the general-purpose chip corresponding to the chip under test.
[0058] Furthermore, the shape, size, and distance between the test pins and the ground metal layer M2 of the open-circuit calibration chip can be optimized and calculated based on the external dimensions and pin dimensions of the chip under test. That is, the dimensions of the printed circuit on the open-circuit calibration chip can be optimized and calculated based on the external dimensions and pin dimensions of the chip under test. The optimization goal is for the open-circuit calibration chip to meet the S-parameter < 0.3dB within the operating frequency band of the chip under test.
[0059] exist Figure 3 The example shown is for Figure 1 In the embodiment of the open-circuit calibration chip designed for the chip under test, in order to meet the above S parameters, the vertical side A1 of the test pins Pin1 to Pin6 is 0.72mm, the horizontal side D2 is 1.20mm, and the short vertical side A2 of the spacing area N21 around any test pin is 2.28mm, the long vertical side A3 is 2.58mm, the short horizontal side D1 is 1.11mm, and the long horizontal side D3 is 1.80mm.
[0060] More preferably, the test pins of the open-circuit calibration chip can be arranged non-centrally and symmetrically according to the pin arrangement of the chip under test, so as to achieve calibration of all pins on the chip under test with the fewest possible test pins. Figure 1 Taking the QFN4x4-24L packaged chip shown as an example, the test pins of the open-circuit calibration chip are as follows: Figure 3(c) Arrangement, then if the open-circuit calibration chip is arranged according to Figure 3 The placement position is calibrated, and pins 1 through 6 can be calibrated individually. Figure 1 The pins of the packaged chip shown are 1, 3, 5, 14, 16, and 18; if this open-circuit calibration chip is... Figure 3 Rotate 90° clockwise and place; pins 1 through 6 can then be calibrated individually. Figure 1 The pins of the packaged chip shown are 19, 21, 23, 8, 10, and 12; if this open-circuit calibration chip is... Figure 3 Rotate 180° clockwise and place; pins 1 through 6 can be calibrated individually. Figure 1 The pins of the packaged chip shown are 13, 15, 17, 2, 4, and 6; if this open-circuit calibration chip is... Figure 3 Rotate 270° clockwise and place; pins 1 through 6 can be calibrated individually. Figure 1 The pins of the packaged chip shown are 7, 9, 11, 20, 22, and 24; obviously, although Figure 3 The open-circuit calibration chip shown only has 6 test pins, but it achieves [the following is a separate, unrelated sentence:] Figure 1 The open-circuit calibration of all pins of the chip under test is shown.
[0061] Example 3:
[0062] against Figure 1 The top and bottom surfaces and one side of the matching load calibration chip designed for the packaged chip shown are as follows: Figure 4 As shown in (a) to 4(c), the matching load calibration chip is used to calibrate the radio frequency performance of the chip under test. The size of the matching load calibration chip is the same as that of the chip under test (i.e., 4*4mm), and the test pin of the matching load calibration chip is electrically connected to its ground metal layer through a load resistor.
[0063] Furthermore, such as Figure 4 As shown, the matching load calibration chip includes a dielectric substrate N3. The bottom surface of dielectric substrate N3 has a grounding area and several pin areas. The grounding area is covered with metal to serve as a grounding metal layer M3, and the pin areas are covered with metal to serve as test pins Pin1 to Pin6. The grounding metal layer M3 and any two of the test pins (between the grounding metal layer M3 and any one of Pin1 to Pin6, or between any two pins) are insulated by dielectric substrate N3. The load resistor for any test pin is set on the insulating area N31 between the test pin and the grounding metal layer and is connected across the test pin and the grounding metal layer M3.
[0064] Preferably, the load resistor has a resistance of 50Ω.
[0065] Even more preferably, the load resistance is the sheet resistance of the thin-film process.
[0066] Even better, the load resistance of any test pin is two sheet resistances of thin-film process connected in parallel.
[0067] by Figure 4 Taking the enlarged schematic diagram of test pin Pin3 in the specific embodiment shown as an example, the two thin-film process sheet resistors K31 and K32 of test pin Pin3 are respectively disposed on both sides of test pin Pin3, and the two sides of thin-film process sheet resistors K31 or K32 are respectively connected to the ground metal layer M3 and Pin3. Preferably, the resistance value of thin-film process sheet resistors K31 and K32 is 100 Ω, then the parallel resistance value of K31 and K32 is 50 Ω.
[0068] Further optimized, the ground metal layer M3, test pins Pin1~Pin6, and / or thin-film sheet resistors K31 and K32 on the matching load calibration chip are printed circuits. The dimensions of this printed circuit are calculated by optimizing the outline dimensions and pin dimensions of the chip under test. The optimization objective is that the matching load calibration chip satisfies the S-parameter S11>-20dB within the operating frequency band of the chip under test.
[0069] exist Figure 4 The example shown is for Figure 1 In the embodiment of the matching load calibration chip designed for the chip under test, in order to meet the above S parameters, the vertical side B1 of the test pin is 0.72mm, the horizontal side E2 is 1.20mm, and the short vertical side B2 of the spacing area N31 around any test pin is 2.28mm, the long vertical side B3 is 2.58mm, the short horizontal side E1 is 1.11mm, and the long horizontal side E3 is 1.80mm.
[0070] More preferably, the test pins of the matching load calibration chip can be arranged non-centrally and symmetrically according to the pin layout of the chip under test, so as to achieve calibration of all pins on the chip under test with the fewest possible test pins. Figure 1 Taking the QFN4x4-24L packaged chip shown as an example, the test pins of the matching load calibration chip are as follows: Figure 4 (c) Arrangement, then if the matched load calibration chip is arranged according to Figure 4 The placement position is calibrated, and pins 1 through 6 can be calibrated individually. Figure 1 The pins of the packaged chip shown are 1, 3, 5, 14, 16, and 18; if the matching load calibration chip is... Figure 4 Rotate 90° clockwise, and pins 1-6 can be used to calibrate ports 19, 21, 23, 8, 10, and 12 respectively; if the matching load calibration chip is used... Figure 4 Rotate 180° clockwise and place. Pins 1-6 can be used to calibrate pins 13, 15, 17, 2, 4, and 6 of the packaged chip, respectively. If the matching load calibrates the chip... Figure 4Rotate 270° clockwise and place; pins 1-6 can be used to calibrate pins 7, 9, 11, 20, 22, and 24 of the packaged chip, respectively; obviously, although Figure 4 The matched load calibration chip shown only has 6 test pins, but it achieves [the following is a separate, unrelated sentence:] Figure 1 The matching load calibration of all ports of the chip under test is shown.
[0071] Example 4:
[0072] against Figure 1 The through-pass calibration chip shown is designed for calibrating the RF performance of the chip under test. Its top and bottom surfaces and one side are as follows. Figure 5 As shown in (a) to 5(d), the through calibration chip has the same size as the chip under test, and any two test pins of the through calibration chip that have a through relationship are electrically connected.
[0073] in, Figure 5 (a) A schematic diagram of the first surface of a through-calibration chip in a specific embodiment is shown; Figure 5 (b) A schematic diagram of one side of a through-calibration chip in a specific embodiment is shown; Figure 5 (c) A schematic diagram of the second surface of the through calibration chip opposite to the first surface in a specific embodiment is shown; Figure 5 (d) shows Figure 5 (a) Schematic diagram of the B-B' cross section of the through calibration chip.
[0074] Furthermore, the through calibration chip includes a first metal layer X1, a first dielectric layer N4, and a second metal layer X2, wherein the first metal layer X1 and the second metal layer X2 are metal layers respectively covering two opposite surfaces of the first dielectric layer N4.
[0075] The first metal layer X1 includes a grounded metal area M4 and multiple test pins ( Figure 5 Pins 1 to 6), the grounding metal area M4 and any two of the multiple test pins (i.e., the grounding metal area and...) Figure 5 The first dielectric layer N4 insulates any one of the pins from Pin1 to Pin6 or between any two pins.
[0076] The test pins include N groups of through-hole pins, where N ≥ 1, and each through-hole pin group contains two test pins. Figure 5 For example, Figure 5 The through calibration chip shown has three through groups with through relationships: the first through group consisting of Pin1 and Pin6, the second through group consisting of Pin2 and Pin5, and the third through group consisting of Pin3 and Pin4.
[0077] It is understood that in other embodiments, if N=1, the arrangement of the two test pins in the pass-through group corresponds to the input pin and output pin of the chip under test. That is, the pass-through calibration chip is provided with at least a pass-through group for calibrating the pass-through relationship between the input pin and output pin of the chip under test.
[0078] The second metal layer X2 includes N through-strip lines, each corresponding to one of the N through-groups. Figure 5 For example, Figure 5 The through calibration chip shown has three through microstrip lines, namely T1, T2 and T3.
[0079] At least 2N metal vias are provided on the first dielectric layer N4, and each test pin in each through-pass group corresponds to at least one metal via. The two test pins in any through-pass group pass through the first dielectric layer N4 through the corresponding metal vias and are connected to the two ends of the through-pass microstrip line corresponding to that through-pass group.
[0080] like Figure 5 As shown in (d), in Figure 5 In the specific embodiment shown, metal vias H1 to H3 are provided on the B-B' side cross-section of the through-pass calibration chip. These metal vias H1 to H3 are the metal vias corresponding to the test pins Pin1 to Pin3, respectively. That is, the test pins Pin1 to Pin3 are connected to one end of the through-pass microstrip line T1 to T3 corresponding to their respective through-pass groups through the metal vias H1 to H3, and are thus connected to another test pin Pin6 to Pin4 that has a through-pass relationship through the through-pass microstrip line T1 to T3, respectively.
[0081] It is understandable that, in order to ensure the electrical connection between each test pin and the through-microstrip line, each test pin may have more than one metal via, but the function of each metal via is the same: to provide the test pin with the connection to the through-microstrip line.
[0082] Furthermore, N+1 metal channels are provided on the first dielectric layer. The number of metal channels is one more than the number of through microstrip lines. The metal channels are insulated from the metal vias. The N+1 metal channels are spaced apart from the N through microstrip lines to isolate each through microstrip line individually.
[0083] like Figure 5 As shown in (a) and 5(d), in Figure 5In the illustrated embodiment, the through-calibration chip is provided with metal channels S1 to S4. Metal channels S1 and S2 form a metal isolation cavity to isolate the metal vias connected to both ends of the through-microstrip line T1 (the metal via at one end is H1, and the metal via at the other end is not labeled); metal channels S2 and S3 form a metal isolation cavity to isolate the metal vias connected to both ends of the through-microstrip line T2 (the metal via at one end is H2, and the metal via at the other end is not labeled); metal channels S3 and S4 form a metal isolation cavity to isolate the metal vias connected to both ends of the through-microstrip line T3 (the metal via at one end is H3, and the metal via at the other end is not labeled).
[0084] More preferably, such as Figure 5 As shown in (a), metal channels S1 to S4, each metal channel can be multiple metal through holes arranged continuously on the same straight line. Figure 5 The metal channels S1~S4 in (a) correspond to Figure 5 (c) shows multiple metal channels formed by multiple metal vias. It is understood that the metal channels are preferably metal-filled channels; however, if interconnected channels are used, the dielectric substrate would be divided into multiple sections by the multiple metal channels, which might cause unevenness between the surfaces of the first metal layer X1 and the second metal layer X2. Therefore, more preferably, each metal channel can adopt a structure of densely arranged metal vias on the same straight line.
[0085] Preferably, the second metal layer X2 has grounding metal areas M5 corresponding one-to-one with the metal channels. The grounding metal area M4 on the first metal layer X1 is connected to the grounding metal area M5 on the second metal layer X2 through metal channels S1~S4. The width of each grounding metal area is greater than or equal to the diameter of any metal via in the metal channel covered by the grounding metal area, and the width of the grounding metal area between any two metal microstrip lines is less than the distance between the edge lines of the two through microstrip lines; the length of each grounding metal area is equal to the length of the through microstrip line.
[0086] Furthermore, the circuits (including through microstrip lines, ground metal areas, and test pins, etc.) on the first metal layer X1 and the second metal layer X2 of the through calibration chip are printed circuits. The size of the printed circuits is calculated by optimizing the outline size and pin size of the chip under test. The optimization goal is to match the load calibration chip to meet the S-parameters S11<-20dB and S22<-20dB in the operating frequency band of the chip under test.
[0087] exist Figure 5 The example shown is for Figure 1 In the embodiment of the through-calibration chip design of the chip under test, in order to meet the above S parameters, any test pin ( Figure 5Taking Pin 3 as an example, the vertical side C1 is 0.72mm, and the horizontal side F2 is 1.20mm; any test pin ( Figure 5 Taking Pin 3 as an example, the short vertical side C2 of the surrounding spacing region N41 is 2.28 mm, the long vertical side C3 is 2.58 mm, the short horizontal side F1 is 1.11 mm, and the long horizontal side F3 is 1.80 mm; in the second metal layer X2, any continuous microstrip line ( Figure 5 Taking T3 as an example, the width G1 is 0.72mm, and the edge line spacing G2 of the grounding metal area at both ends of the through microstrip line is 2.28mm.
[0088] Figure 5 The shown through-pass calibration chip has three through-pass groups, with the two test pins of each through-pass group lying on a straight line parallel to the side of the through-pass calibration chip. Preferably, Figure 5 The test pins can be arranged non-centrally and symmetrically according to the pin arrangement on the chip under test, so as to achieve the minimum number of test pins but calibrate all pins on the chip under test.
[0089] by Figure 1 Taking the QFN4x4-24L packaged chip shown as an example, the test pins of the through-calibration chip are as follows: Figure 5 (c) Arrangement, then if the through calibration chip is arranged as follows: Figure 5 The placement position is calibrated, and pins 1 through 6 can be respectively aligned with... Figure 5 The pins 1, 3, 5, 14, 16, and 18 of the packaged chip correspond to the following: Pin 1 and Pin 6 calibrate the through-connection relationship between pins 1 and 18 of the packaged chip; Pin 2 and Pin 5 calibrate the through-connection relationship between pins 3 and 16 of the packaged chip; and Pin 3 and Pin 4 calibrate the through-connection relationship between pins 5 and 14 of the packaged chip. If this through-connection calibration chip is... Figure 5 Rotate 90° clockwise, and pins 1-6 will correspond to pins 19, 21, 23, 8, 10, and 12 of the packaged chip, respectively. Pins 1 and 6 calibrate the through-connection relationship between pins 19 and 12 of the packaged chip; pins 2 and 5 calibrate the through-connection relationship between pins 21 and 10 of the packaged chip; and pins 3 and 4 calibrate the through-connection relationship between pins 23 and 8 of the packaged chip. If this through-connection calibration chip is... Figure 5 Rotate 180° clockwise. Pins 1 through 6 can correspond to pins 13, 15, 17, 2, 4, and 6 of the packaged chip, respectively. Pins 1 and 6 calibrate the through-connection relationship between pins 13 and 6 of the packaged chip; pins 2 and 5 calibrate the through-connection relationship between pins 15 and 4 of the packaged chip; and pins 3 and 4 calibrate the through-connection relationship between pins 17 and 2 of the packaged chip. If this through-connection calibration chip is... Figure 5Rotate 270° clockwise and place the pins. Pins 1 through 6 can correspond to pins 7, 9, 11, 20, 22, and 24 of the packaged chip, respectively. Pins 1 and 6 calibrate the through-connection relationship between pins 7 and 24 of the packaged chip; pins 2 and 5 calibrate the through-connection relationship between pins 9 and 22 of the packaged chip; and pins 3 and 4 calibrate the through-connection relationship between pins 11 and 20 of the packaged chip. Clearly, although... Figure 5 The through-calibration chip shown only has 6 test pins, but it achieves [the following is a separate, unrelated sentence:] Figure 1 The through-through calibration of all ports of the chip under test is shown.
[0090] Example 5:
[0091] Based on Embodiment 4, the through calibration chip may also include a second dielectric layer and a third metal layer.
[0092] like Figure 6 As shown in (a) to 6(e), Figure 6 (e) corresponds to Figure 5 (a), Figure 6 (b)~6(d) respectively with Figure 5 (b) ~ 5 (d) correspond to, Figure 6 (a) is a schematic diagram of one of the bottom surfaces of the second dielectric layer (only the third metal layer is shown after full metallization).
[0093] Example 5, based on Example 4, further includes a second dielectric layer N5 and a third metal layer X3. The first metal layer X1, the first dielectric layer N4, the second metal layer X2, the second dielectric layer N5, and the third metal layer X3 are stacked sequentially.
[0094] As shown in the figure Figure 6 As shown in (a), the second metal layer X2 is a fully metallized metal layer.
[0095] Metal channels S1~S4 penetrate the first dielectric layer N4 and the second dielectric layer N5, and connect to the ground metal area M5 of the second metal layer X2 and the ground metal area M6 of the third metal layer. That is, the positions of the metal channels on the first dielectric layer N4 and the second dielectric layer N5 correspond one-to-one. The ground metal area M4 on the first metal layer X1 is connected to ground metal areas M5 and M6 through metal channels S1~S4. Thus, all ground metal channels isolate the metal vias and through-strip lines corresponding to each test pin into independent metal isolation areas, preventing energy scattering in the corresponding through-strip groups and thus avoiding impact on calibration results.
[0096] According to another aspect of the present invention, a calibration chipset is also provided, including the short-circuit calibration chip in Embodiment 1, the open-circuit calibration chip in Embodiment 2, the load matching calibration chip in Embodiment 3, and the through calibration chip in Embodiment 4 (or Embodiment 5).
[0097] The calibration chip and its combination disclosed in this invention can be used with test equipment and a vector network analyzer to form a direct calibration device for chip testing.
[0098] Calibration chips or combinations thereof are used for the calibration of vector network analyzers.
[0099] During vector network analyzer calibration, the calibration chip is installed in the test fixture, and the test fixture with the calibration chip installed is connected to the vector network analyzer for TOSL (Through Open Short Load) calibration. The calibration process requires placing the short-circuit calibration chip, open-circuit calibration chip, load-matching calibration chip, and through-circuit calibration chip into the test fixture respectively, and then testing the corresponding S-parameter calibration values under short-circuit, open-circuit, load-matching, and through-circuit conditions.
[0100] After calibration, the chip under test (DUT) is tested using a calibrated vector network analyzer within the testing equipment. It can be understood that during calibration, the vector network analyzer has already corrected for errors introduced by the testing equipment using the testing equipment as a calibration surface. Therefore, during the testing of the DUT, the RF performance measured based on the calibration surface obtained during calibration is the actual RF performance of the DUT, eliminating the need for "de-embedding".
[0101] Specifically, the test equipment can be existing or future equipment used for testing chips. In one specific embodiment, such as... Figure 7 As shown, the test equipment may include an evaluation circuit board 2, an interposer 1, a test slot 8, a coaxial connector 6, and a pressure plate (not shown).
[0102] Evaluation board 2 is a board used to evaluate the performance of the chip under test. It is equipped with pin circuits 5 and microstrip line circuits (not shown), etc.
[0103] The chip under test (DUT) or calibration chip can be installed in the test slot 8 and accurately positioned by the test slot. Under the action of the cover plate, it makes reliable contact with the pin circuitry 5 on the evaluation circuit board through the interposer layer 1. The interposer layer can be a structure such as a spring pin or a conductive film to ensure a reliable connection between the pins of the DUT and the PCB circuitry.
[0104] Coaxial connector 6 is the port for cable connection to the vector network analyzer.
[0105] More specifically, the evaluation circuit board 2 is also provided with positioning holes 4, and the lower part of the test card slot 8 is provided with positioning pins 3 that fit with the positioning holes 4. It can be understood that the positioning holes 4 and positioning pins 3 are used to fix the test card slot 8 and the evaluation circuit board 2.
[0106] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A calibration chipset, characterized in that, The calibration chip set is used to calibrate the radio frequency performance of a chip under test (DUT). It includes a short-circuit calibration chip, an open-circuit calibration chip, a matched-load calibration chip, and a through-circuit calibration chip. The size of any calibration chip in the calibration chip set is the same as that of the DUT. The test pin of the short-circuit calibration chip is short-circuited to its own ground metal layer; The test pin of the open-circuit calibration chip is open-circuited with its own ground metal layer; The test pins of the matching load calibration chip are connected to its own grounded metal layer through a load resistor; The through calibration chip is electrically connected between any two test pins that have a through relationship; The short-circuit calibration chip includes a dielectric substrate, the bottom surface of which is completely metallized to serve as the ground metal layer of the short-circuit calibration chip, and the test pins of the short-circuit calibration chip are metal at any position on the bottom surface. The open-circuit calibration chip includes a dielectric substrate. The bottom surface of the dielectric substrate has a grounding area and a plurality of pin areas. The grounding area is covered with a metal layer as the grounding metal layer of the open-circuit calibration chip. The plurality of pin areas are covered with a metal layer as a plurality of test pins of the open-circuit calibration chip. Any two of the grounding metal layer and the plurality of test pins of the open-circuit calibration chip are insulated from each other by the dielectric substrate. The matching load calibration chip includes a dielectric substrate. The bottom surface of the dielectric substrate has a grounding area and several pin areas. The grounding area is covered with a metal layer as the grounding metal layer of the matching load calibration chip. The several pin areas are covered with a metal layer as the test pins of the matching load calibration chip. The grounding metal layer and the test pins are insulated from each other by the dielectric substrate. The load resistor of any test pin is set on the insulated area between the test pin and the grounding metal layer and is connected across the test pin and the grounding metal layer. The through-calibration chip includes a first metal layer, a first dielectric layer, and a second metal layer, with the first metal layer and the second metal layer respectively covering two opposite surfaces of the first dielectric layer. The first metal layer includes a ground metal area and a plurality of test pins, wherein the ground metal area and any two of the plurality of test pins are insulated from each other by the first dielectric layer. The multiple test pins include N groups of through-connection relationships, where N≥1, and each through-connection group includes two test pins. The second metal layer includes N through microstrip lines that correspond one-to-one with the N through groups. The first dielectric layer has at least 2N metal vias. The test pins in each through-hole group correspond to at least one metal via. Two test pins in any through-hole group pass through the first dielectric layer and are connected to the two ends of the through-hole microstrip line corresponding to the through-hole group through the corresponding metal vias.
2. The calibration chipset as described in claim 1, characterized in that, The load resistance is a sheet resistance obtained from a thin-film process; and / or The load resistor of any test pin is two thin-film process sheet resistors connected in parallel, and the two thin-film process sheet resistors are respectively set on both sides of the test pin.
3. The calibration chipset as described in claim 1, characterized in that, The through calibration chip further includes a second dielectric layer and a third metal layer. The first metal layer, the first dielectric layer, the second metal layer, the second dielectric layer, and the third metal layer are stacked sequentially. The first dielectric layer and the second dielectric layer are also provided with N+1 corresponding metal channels. The metal channels are insulated from the metal vias. The grounding metal area is electrically connected to the third metal layer through the metal channels. The N+1 metal channels are spaced apart from the N through microstrip lines to isolate each through microstrip line individually.
4. The calibration chipset according to any one of claims 1 to 3, characterized in that, The dimensions of the printed circuits on the open-circuit calibration chip, the matched load calibration chip, and the through-circuit calibration chip are obtained by optimizing the external dimensions and pin dimensions of the chip under test. The optimization objectives are as follows: the open-circuit calibration chip satisfies S-parameter < 0.3dB in the operating frequency band of the chip under test; the matched load calibration chip satisfies S-parameter S11 > -20dB in the operating frequency band of the chip under test. The through-calibration chip satisfies the S-parameters S11<-20dB and S22<-20dB within the operating frequency band of the chip under test.