Display panel and preparation method thereof

Abstract

The application provides a display panel and a preparation method thereof. The display panel comprises: a plurality of common electrodes; a first metal oxide layer disposed on the common electrodes, comprising a body part and a first protruding part protruding from the body part; and a second metal oxide layer disposed on the first metal oxide layer, the second metal oxide layer comprising a connecting electrode, the connecting electrode being electrically connected to the common electrode through a first via, and the connecting electrode being electrically connected to the body part through a second via; wherein the first protruding part is located on the side of the first via, and the minimum distance between the first protruding part and the sidewall of the first via is zero. The display panel and the preparation method thereof provided by the application can reduce the risk of short circuit of the pixel electrodes of the first metal oxide layer and the second metal oxide layer.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Technology

[0002] Transparent metal oxides (MOOs) are widely used in pixel electrodes of liquid crystal display (LCD) panels due to their high transmittance and good conductivity. Existing technology involves placing an intermediate MOO layer between the common electrode and the pixel electrode on the array substrate. This intermediate MOO layer is electrically connected to the common electrode, acting as a common signal line and shielding the parasitic capacitance between the source / drain layer and the pixel electrode. However, since the intermediate MOO layer is formed after the color resist layer, the protrusions on the film surface caused by the color resist layer can lead to an excessively thin organic planarization layer between the intermediate MOO layer above the color resist and the pixel electrode. Existing technology typically uses the organic planarization layer as a mask to etch openings in the underlying insulating layer. During the etching process, the absence of the organic planarization layer can cause a short circuit between the intermediate MOO layer and the pixel electrode.

[0003] In conclusion, existing display panels need improvement. Summary of the Invention

[0004] This application provides a display panel and its fabrication method to solve the technical problem in existing display panels where, when an organic planarization layer is used as a mask to create openings in the underlying insulating layer, the organic planarization layer may be missing during the etching process, leading to a short circuit between the intermediate metal oxide layer and the pixel electrode.

[0005] On one hand, this application provides a display panel, including:

[0006] Multiple common electrodes;

[0007] A first metal oxide layer, disposed on the common electrode, includes a body portion and a first protrusion protruding from the body portion; and

[0008] A second metal oxide layer is disposed on the first metal oxide layer. The second metal oxide layer includes a connection electrode. The connection electrode is electrically connected to the common electrode through a first via and to the body portion through a second via.

[0009] The first protrusion is located on the periphery of the first through hole, and the minimum distance between the first protrusion and the sidewall of the first through hole is zero.

[0010] In some embodiments of this application, the first protrusion surrounds the first through hole.

[0011] In some embodiments of this application, a plurality of the common electrodes extend along a first direction and are arranged along a second direction, the orthographic projection of the body portion on the common electrode is located between two adjacent common electrodes, and the projection of the first protrusion on the common electrode partially overlaps with the common electrode.

[0012] In some embodiments of this application, the second metal oxide layer further includes a pixel electrode that is insulated from the connection electrode, and the pixel electrode is electrically connected to one of the source and drain electrodes of the source-drain layer through a third via.

[0013] In some embodiments of this application, the third through hole penetrates the body portion, and the minimum distance between the body portion and the sidewall of the third through hole is greater than zero.

[0014] On the other hand, this application also provides a method for manufacturing a display panel, comprising the following steps:

[0015] An array substrate is provided, the array substrate comprising a first metal layer, a gate insulating layer, an active layer, a source drain layer, and a passivation layer stacked sequentially, wherein the first metal layer includes at least a common electrode;

[0016] A first metal oxide preform is formed on the passivation layer;

[0017] A first photoresist pattern is formed on the first metal oxide preform layer. The first photoresist pattern has a first etch hole and a second etch hole. The first etch hole is disposed corresponding to one of the source and drain electrodes of the source-drain layer, and the second etch hole is disposed corresponding to the common electrode.

[0018] Using the first photoresist pattern as a mask, the passivation layer corresponding to the first etched hole is etched to form a third via, the third via exposing at least a portion of the surface of one of the source and drain electrodes of the source-drain layer; simultaneously, the passivation layer and the gate insulating layer corresponding to the second etched hole are etched to form a first via, the first via exposing at least a portion of the surface of the common electrode; and

[0019] The first photoresist pattern is patterned to form a second photoresist pattern. Using the second photoresist pattern as a mask, the first metal oxide pre-film layer is etched to form a patterned first metal oxide layer.

[0020] In some embodiments of this application, the fabrication method further includes, prior to the etching of the passivation layer and the insulating layer by the third via:

[0021] Using the first photoresist pattern as a mask, the first metal oxide preform layer located in the first etch hole and the second etch hole is etched.

[0022] In some embodiments of this application, the second photoresist pattern includes a third etched hole and a fourth etched hole, wherein,

[0023] The third etched hole exposes the annular surface of the first metal oxide pre-film layer surrounding the third via.

[0024] The fourth etched hole is located at the junction of the light-transmitting area and the non-light-transmitting area, and exposes the first metal oxide pre-film layer.

[0025] In some embodiments of this application, the step of etching the first metal oxide preform layer using the second photoresist pattern as a mask includes:

[0026] Using the second photoresist pattern as a mask, the first metal oxide preform layer located in the third and fourth etch holes is etched to obtain a patterned first metal oxide layer.

[0027] In some embodiments of this application, the preparation method further includes:

[0028] A patterned organic planarization layer is formed on the first metal oxide layer, the organic planarization layer including a second via that exposes at least a portion of the surface of the first metal oxide layer;

[0029] A patterned second metal oxide layer is formed on the organic planarization layer, wherein the second metal oxide layer includes mutually insulated pixel electrodes and connection electrodes, wherein the pixel electrodes are connected to one of the source and drain electrodes of the source-drain layer through the third via, the connection electrodes are connected to the common electrode through the first via, and the connection electrodes are connected to the first metal oxide layer through the second via.

[0030] The beneficial effects of this application are as follows: This application provides a display panel and its manufacturing method. By using the same photoresist film layer as a mask, the patterning of the first metal oxide layer and the opening of the passivation layer and the insulating layer can be realized simultaneously. This not only saves the photomask process, but also avoids the risk of short circuit between the first metal oxide layer and the pixel electrode of the upper second metal oxide layer caused by the absence of the organic planarization layer during the etching process when the opening of the gate insulating layer and the passivation layer is made using the organic planarization layer as a mask in the prior art. At the same time, it can also save the material of the organic planarization layer. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the film layer stacking structure of a display panel in the prior art;

[0033] Figure 2 A flowchart illustrating the steps of a method for manufacturing a display panel according to an embodiment of this application.

[0034] Figure 3 This is a schematic diagram of the structure of the array substrate provided in an embodiment of this application.

[0035] Figure 4 This is a schematic diagram of the structure of forming a first metal oxide preform layer on a color resist layer, as provided in an embodiment of this application.

[0036] Figure 5 This is a schematic diagram of the structure of forming a patterned photoresist layer on a first pre-fabricated film layer, provided in an embodiment of this application.

[0037] Figure 6 This is a schematic diagram of the structure for the first etching of the first metal oxide pre-film layer provided in an embodiment of this application.

[0038] Figure 7 This is a schematic diagram of the structure for etching the passivation layer and the gate insulating layer, provided in an embodiment of this application.

[0039] Figure 8 This application provides a schematic diagram of the structure for the second etching of the first metal oxide pre-film layer.

[0040] Figure 9 This is a schematic diagram of the structure of each film layer after the photoresist layer has been removed, as provided in the embodiments of this application.

[0041] Figure 10 This is a schematic diagram of the structure of forming an organic planarization layer on a first metal oxide layer, provided in an embodiment of this application.

[0042] Figure 11 This is a schematic diagram of a patterned second metal oxide layer formed on an organic planarization layer, as provided in an embodiment of this application.

[0043] Figure 12 This is a plan view of the display panel provided in an embodiment of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0045] In the description of this application, it should be understood that the terms "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. In this application, unless otherwise expressly specified and limited, "upper" or "lower" of the first feature and the second feature may include direct contact between the first and second features, or contact between the first and second features not in direct contact but through another feature between them.

[0046] Please see Figure 1 ,like Figure 1 The fabrication process of the display panel with the structure shown generally includes: sequentially stacking a first metal layer 10, a gate insulating layer 20, an active layer 30, a source / drain layer 40, a passivation layer 50, a color resist layer 60, a first metal oxide layer 70, an organic planarization layer 80, and a second metal oxide layer 90 on a substrate. The first metal layer 10 is used to form at least a common electrode 12. The first metal oxide layer 70 is electrically connected to the common electrode 12 below through vias at corresponding locations. The second metal oxide layer 90 is used to form at least a pixel electrode 91, and the pixel electrode is electrically connected to the source / drain layer 40 below through vias at corresponding locations. This fabrication process involves six photomask processes, including: patterning of the first metal layer 10, patterning of the active layer 30, patterning of the source / drain layer 40, patterning of the first metal oxide layer 70, formation of vias, and patterning of the second metal oxide layer.

[0047] Since the organic planarization layer 80 is typically an organic photoresist material, existing technologies generally use the organic planarization layer 80 as a mask to create openings in the underlying passivation layer 50 and gate insulating layer 20, forming vias of different depths at different locations (such as the first via 102 and the third via 101). However, in this approach, on the one hand, the presence of the color resist layer 60 causes the organic planarization layer 80 directly above the color resist layer 60 to be relatively thinner than other locations, resulting in the first metal oxide layer 70 directly above the color resist layer 60 and its corresponding second metal oxide layer 90 being too close. This could lead to the organic planarization layer 80 being missing in subsequent processes, causing a short circuit between the first metal oxide layer 70 and the second metal oxide layer 90. On the other hand, since the organic planarization layer 80 is used as a photomask, dry etching can cause a portion of the organic planarization layer 80 to be etched away simultaneously, resulting in a reduction in the film thickness of the organic planarization layer 80. Therefore, when coating the material of the organic planarization layer 80, the preset thickness is generally thicker than the actual thickness of the organic planarization layer 80 that will eventually be formed, which increases material costs.

[0048] Please see Figure 2 This application provides a method for manufacturing a display panel, comprising the following steps:

[0049] S10, an array substrate is provided, the array substrate comprising a first metal layer 10, a gate insulating layer 20, an active layer 30, a source / drain layer 40, and a passivation layer 50 stacked sequentially, wherein the first metal layer 10 includes at least a common electrode 12, such as... Figure 3 As shown.

[0050] S20, a first metal oxide pre-film layer 70' is formed on the passivation layer 50, such as Figure 4 As shown.

[0051] S30, a first photoresist pattern 200 is formed on the first metal oxide pre-film layer 70'. The first photoresist pattern 200 has a first etched hole 201 and a second etched hole 202. The first etched hole 201 is corresponding to one of the source and drain electrodes of the source-drain layer 40, and the second etched hole 202 is corresponding to the common electrode 12. Figure 5 As shown. The first etched hole 201 is correspondingly disposed with one of the source and drain electrodes of the source-drain layer 40, meaning that in the direction perpendicular to the thickness of the display panel, the first etched hole 201 overlaps with one of the source and drain electrodes of the source-drain layer 40, that is, their orthogonal projections on the first metal layer 10 overlap. Similarly, the second etched hole 202 corresponds to the common electrode 12, meaning that they overlap in the direction perpendicular to the thickness of the display panel.

[0052] S40, using the first photoresist pattern 200 as a mask, the passivation layer 50 corresponding to the first etched hole 201 is etched to form a third via 101, the third via 101 exposing at least a portion of the surface of one of the source and drain electrodes of the source-drain layer 40; simultaneously, the passivation layer 50 corresponding to the second etched hole 202 and the gate insulating layer 20 are etched to form a first via 102, the first via 102 exposing at least a portion of the surface of the common electrode 12, such as... Figure 7 As shown; S50, the first photoresist pattern 200 is patterned to form a second photoresist pattern 300. Using the second photoresist pattern 300 as a mask, the first metal oxide pre-film layer 70' is etched to form a patterned first metal oxide layer 70, as shown. Figure 7 and Figure 8 As shown.

[0053] This application achieves the patterning process of the first metal oxide layer 70 and the openings on the gate insulating layer 20 and passivation layer 50 by coating a photoresist material on the first metal oxide layer and using the photoresist as a mask. This not only saves the photomask process, but also avoids the loss of the organic planarization layer 80 during the etching process since no organic planarization layer 80 is used as a mask for etching, thereby avoiding short circuits between the intermediate metal oxide layer and the pixel electrode. In addition, it also saves the material of the organic planarization layer 80.

[0054] Specifically, such as Figure 2 As shown, the array substrate includes multiple thin-film transistors (TFTs). Each TFT may have a bottom-gate structure and includes a gate 11, an active layer 30, and a source / drain layer 40. The TFT may be an amorphous silicon TFT or a metal-oxide TFT, meaning the active material includes amorphous silicon or metal oxides such as IGZO.

[0055] The first metal layer 10 includes the common electrode 12 and the gate electrode 11 disposed on the same layer, that is, the common electrode 12 and the gate electrode 11 can be formed by patterning the same metal layer. Disposing the common electrode 12 and the gate electrode 11 on the same layer can save one photomask process.

[0056] The array substrate can be a COA-type array substrate, that is, the color filter substrate is integrated on the array substrate. For example... Figure 2 and Figure 3 As shown, prior to S20, the preparation method further includes: forming a patterned color resist layer 60 on the passivation layer 50, wherein the color resist layer 60 includes red color resist, green color resist and blue color resist.

[0057] The photomask process of the above-mentioned array substrate includes: patterning of the first metal layer 10, patterning of the active layer 30, patterning of the source-drain layer 40, and patterning of the color resist layer 60.

[0058] In step S20, ITO material is coated all over the color resist layer 60 to form a first metal oxide preform layer 70'.

[0059] like Figure 5 As shown, in S30, photoresist is first coated on the first metal oxide pre-film layer 70', and after exposure and development, the patterning on the first photoresist pattern 200 is completed.

[0060] like Figures 5 to 7 As shown, when forming the third via 101 and the first via 102 by etching, the portions of the third via 101 and the first via 102 that are blocked by the first metal oxide preform 70' must first be removed. Therefore, the fabrication method further includes: using the first photoresist pattern 200 as a mask, etching the first metal oxide preform 70' located in the first etch hole 201 and the second etch hole 202.

[0061] Specifically, wet etching is used to etch the film layer in the first preset region 701 of the first metal oxide pre-film layer 70', and the first preset region 701 corresponds to the first etch hole 201 and the second etch hole 202.

[0062] like Figure 6 and Figure 7 As shown, dry etching is then used to etch the passivation layer 50 corresponding to the first etched hole 201 to form a third via 101, wherein the third via 101 exposes a portion of the surface of one of the source and drain electrodes of the source-drain layer 40; simultaneously, the passivation layer 50 and the gate insulating layer 20 corresponding to the second etched hole 202 are etched to form a first via 102, wherein the first via 102 exposes at least a portion of the surface of the common electrode 12. During the dry etching process of the passivation layer 50 and the gate insulating layer 20, a portion of the first photoresist pattern 200 is etched away, and its film thickness is reduced.

[0063] like Figure 7 As shown, after the third via 101 and the first via 102 are formed, the first photoresist pattern 200 is patterned to form a second photoresist pattern 300, so that the first metal oxide preform layer 70' can be further etched using the second photoresist pattern 300 as a mask to form a patterned first metal oxide layer 70.

[0064] like Figure 7As shown, the step of patterning the first photoresist pattern 200 to form the second photoresist pattern 300 includes: forming a third etch hole 301 and a fourth etch hole 302 on the first photoresist pattern 200, wherein the third etch hole 301 exposes the annular surface of the first metal oxide preformed film layer 70' surrounding the third via 301, and the fourth etch hole 302 is located at the junction of the light-transmitting area 104 and the non-light-transmitting area 105, and exposes the first metal oxide preformed film layer 70'.

[0065] It is worth noting that the display panel includes multiple sub-pixel units, each including a light-transmitting area 104 and a non-light-transmitting area 105. The common electrode 12 is formed in the non-light-transmitting area 105. The common electrode 12 in the non-light-transmitting area 105 can be electrically connected to the first metal oxide layer 70 located in the light-transmitting area 104 through a subsequently formed connection electrode at the fourth etch hole 302.

[0066] Subsequently, the first metal oxide preform 70' is etched using the second photoresist pattern 300 as a mask. The steps include: using the second photoresist pattern 300 as a mask, etching the first metal oxide preform 70' located in the third etching hole 301 and the fourth etching hole 302 to obtain the patterned first metal oxide layer 70.

[0067] like Figure 7 As shown, specifically, wet etching is used to etch the portion of the first metal oxide preform 70' that is not obscured by the second photoresist pattern 300 to form a patterned first metal oxide layer 70. In this etching step, in addition to etching away the area to be patterned to form the pattern of the first metal oxide layer 70, the first metal oxide preform 70' around the third via 101 is also etched away. This prevents the pixel electrode 91 passing through the third via 101 from contacting and connecting with the first metal oxide layer 70 at that location, thus avoiding a short circuit.

[0068] Thus, by applying photoresist material once and etching in three stages, the patterning of the first metal oxide layer 70 and the openings on the passivation layer 50 and the gate insulating layer 20 are completed. On the one hand, this not only saves on the manufacturing process, but also, compared to forming an organic planarization layer 80 later and using the organic planarization layer 80 as a mask to create the openings in the passivation layer 50 and the gate insulating layer 20, the method provided in this application can reduce the amount of organic planarization layer 80 used (the material of the organic planarization layer 80 is organic photoresist material; using the organic planarization layer 80 as photoresist requires a thicker organic planarization layer 80 beforehand to prevent it from being etched away). It can also prevent the organic planarization layer 80 on the color resist layer 60 from being too thin, which would cause the organic planarization layer 80 to be missing during the etching process, resulting in a short circuit between the subsequently deposited pixel electrode 91 and the first metal oxide layer 70.

[0069] like Figure 8 and Figure 9 As shown, after the patterning of the first metal oxide layer 70 is completed, the third photoresist pattern 300 on the first metal oxide layer 70 needs to be removed.

[0070] like Figure 10 and Figure 11 As shown, the fabrication method further includes: forming a patterned organic planarization layer 80 on the first metal oxide layer 70, the organic planarization layer 80 including a second via 103, the second via 103 exposing a portion of the surface of the first metal oxide layer 70; forming a patterned second metal oxide layer 90 on the organic planarization layer 80, wherein the second metal oxide layer 90 includes a pixel electrode 91 and a connection electrode 92 that are insulated from each other, wherein the pixel electrode 91 is connected to one of the source and drain electrodes of the source-drain layer 40 through the third via 101, the connection electrode 92 is connected to the common electrode 12 through the first via 102, and the connection electrode 92 is connected to the first metal oxide layer 70 through the second via 103.

[0071] After forming the passivation layer 50, the gate insulating layer 20 via, and the first metal oxide layer 70 using the same photoresist film layer as described above, when preparing the organic planarization layer 80, it is not necessary to deposit a thicker organic planarization material; only the thickness required for the organic planarization layer 80 itself needs to be deposited, which saves material.

[0072] Based on the preparation method provided in the above embodiments, this application also provides a display panel prepared by the above preparation method.

[0073] like Figure 11As shown, the display panel includes multiple common electrodes 12, a first metal oxide layer 70, and a second metal oxide layer 90. The first metal oxide layer 70 is disposed on the common electrodes 12, and the second metal oxide layer 90 is disposed on the first metal oxide layer 70.

[0074] like Figure 11 and Figure 12 As shown, the first metal oxide layer 70 includes a body portion 72 and a first protrusion 71 protruding from the body portion 72; the second metal oxide layer 90 includes a connecting electrode 92, which is electrically connected to the common electrode 12 through a first via 102 and to the body portion 72 through a second via 103; wherein, the first protrusion 71 is located on the periphery of the first via 102, and the minimum distance between the first protrusion 71 and the sidewall of the first via 102 is zero. Since the film layer of the first metal oxide layer 70 at the first via 102 is formed with the inorganic insulating layer at the first via 102 using the same photomask (first photoresist pattern 200), the film layer of the first metal oxide layer 70 within the first via 102 is etched away, but the surrounding film layer is not etched away due to the blocking effect of the photoresist, thus forming the first protrusion 71.

[0075] Furthermore, the first protrusion 71 surrounds the first via 102. Although the first protrusion 71 contacts the sidewall of the first via 102 and is connected to the connecting electrode 92 passing through the first via 102, the connecting electrode 92 itself serves to connect the first metal oxide layer 70 and the common electrode 12. Therefore, the contact of the first protrusion 71 with the sidewall of the first via 102 has no impact on the performance of the display panel.

[0076] like Figure 12 As shown, the plurality of common electrodes 12 extend along the first direction X and are arranged along the second direction Y. The orthographic projection of the body portion 72 on the common electrode 12 is located between two adjacent common electrodes 12, and the projection of the first protrusion 71 on the common electrode 12 partially overlaps with the common electrode 12.

[0077] In some embodiments, adjacent body portions 72 on both sides of the common electrode are electrically connected via a common line 73.

[0078] The second metal oxide layer 90 also includes a pixel electrode 91 that is insulated from the connection electrode 92. The pixel electrode 91 is electrically connected to one of the source and drain electrodes of the source-drain layer 40 through a third via 101.

[0079] The third via 101 penetrates the body portion 72, and the minimum distance S1 between the body portion 72 and the sidewall of the third via 101 is greater than zero. That is, the body portion 72 and the third via 101 are spaced a certain distance apart, so as to avoid the pixel electrode 91 from short-circuiting with the body portion 71 when passing through the third via 101.

[0080] Specifically, such as Figure 11 As shown, the array substrate includes a first metal layer 10, a gate insulating layer 20, an active layer 30, a source-drain layer 40, and a passivation layer 50 stacked sequentially. The first metal layer 10 includes at least a common electrode 12. A first metal oxide layer 70 is disposed on the passivation layer 50. An organic planarization layer 80 is disposed on the first metal oxide layer 70. A second metal oxide layer 90 is disposed on the organic planarization layer 80. The second metal oxide layer 90 includes a pixel electrode 91 and a connection electrode 92 that are insulated from each other. The pixel electrode 91 is electrically connected to one of the source and drain electrodes of the source-drain layer 40 through a third via 101. The connecting electrode 92 is electrically connected to the common electrode 12 through the first via 102, and the connecting electrode 92 is electrically connected to the first metal oxide layer 70 through the second via 103. The connecting electrode 92 achieves electrical connection between the first metal oxide layer 70 and the common electrode 12 by connecting the common electrode 12 and the first metal oxide layer 70 respectively. The first metal oxide layer 70 acts as a common electrode line and can also shield the parasitic capacitance signal between the pixel electrode 91 and the source / drain layer 40, thereby increasing the area of ​​the pixel electrode 91 and improving the pixel aperture ratio.

[0081] Please see Figure 11 and Figure 12 Since the pixel electrode 91 needs to pass downwards through the third via 101 to connect electrically to the source or drain, it is necessary to remove the third via 101 and the surrounding first metal oxide layer 70 to prevent the pixel electrode 91 from connecting with the first metal oxide layer 70 at the third via 101 and causing a short circuit. Using the above-described fabrication method of this application, the metal oxide film layer inside the third via 101 can be removed during the first wet etching, and the metal oxide film layer around the third via 101 can be removed during the second wet etching. Figure 11 As shown, the third via 101 penetrates the first metal oxide layer 70. At the third via 101, the minimum spacing S1 between the pattern of the first metal oxide layer 70 and the sidewall of the third via 101 is greater than zero. In this way, the pixel electrode 91 and the first metal oxide layer 70 can be prevented from short-circuiting at the third via 101.

[0082] The first via 102 penetrates the first metal oxide layer 70. At the first via 102, the lowest spacing between the pattern of the first metal oxide layer 70 and the sidewall of the first via 102 is zero. Specifically, as shown... Figure 8 As shown, because the first metal oxide layer 70 surrounding the first via 102 is covered by the upper second photoresist pattern 300, it cannot be etched away and will protrude outward relative to the entire first metallization layer 70, forming the first protrusion 71, as shown. Figure 12 As shown. That is, the first metal oxide layer 70 includes a first protrusion 71, the first protrusion 71 is located on the periphery of the first via 102, and the minimum distance between the first protrusion 71 and the sidewall of the first via 102 is zero. For example... Figure 11 As shown, although the connecting electrode 92 will come into contact with the first protrusion 71 when it passes through the first via 102, the connecting electrode 92 itself is used to electrically connect the first metal oxide layer 70 and the common electrode 12. Therefore, the existence of the first protrusion 71 does not affect the function of each device.

[0083] The display panel can be a large-size display panel, which can be used in display devices such as computers and televisions. The display panel can be a liquid crystal display panel. In addition to the structure mentioned in the above preparation method, the display panel also includes a liquid crystal layer disposed on the pixel electrode 91 and a counter substrate. The liquid crystal layer is sandwiched between the array substrate and the counter substrate. The side of the counter substrate facing the liquid crystal layer is also provided with a black matrix for light blocking.

[0084] In summary, this application provides a display panel and its fabrication method. The fabrication method utilizes the same photoresist film layer as a mask to simultaneously pattern the first metal oxide layer and create openings in the passivation layer and insulating layer. This not only saves on photomask processes but also avoids the risk of short circuits between the first metal oxide layer and the pixel electrodes on top of it, which can occur in the prior art when creating openings in the gate insulating layer and passivation layer using an organic planarization layer as a mask, and the organic planarization layer may be missing during etching. It also saves on the material of the organic planarization layer.

[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0086] The display panel and its manufacturing method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes: Multiple common electrodes; A first metal oxide layer, disposed on the common electrode, includes a body portion and a first protrusion protruding from the body portion; and A second metal oxide layer is disposed on the first metal oxide layer. The second metal oxide layer includes a connecting electrode. The connecting electrode is electrically connected to the common electrode through a first via and electrically connected to the body portion through a second via. The first protrusion is located on the periphery of the first through hole, and the minimum distance between the first protrusion and the sidewall of the first through hole is zero.

2. The display panel according to claim 1, characterized in that, The first protrusion surrounds the first through hole.

3. The display panel according to claim 2, characterized in that, The plurality of said common electrodes extend along a first direction and are arranged along a second direction. The orthographic projection of the body portion on the common electrode is located between two adjacent said common electrodes, and the projection of the first protrusion on the common electrode partially overlaps with the common electrode.

4. The display panel according to claim 1, characterized in that, The second metal oxide layer also includes a pixel electrode that is insulated from the connection electrode, and the pixel electrode is electrically connected to one of the source and drain electrodes of the source-drain layer through a third via.

5. The display panel according to claim 4, characterized in that, The third through hole penetrates the body portion, and the minimum distance between the body portion and the sidewall of the third through hole is greater than zero.

6. A method for manufacturing a display panel, characterized in that, Includes the following steps: An array substrate is provided, the array substrate comprising a first metal layer, a gate insulating layer, an active layer, a source drain layer, and a passivation layer stacked sequentially, wherein the first metal layer includes at least a common electrode; A first metal oxide preform is formed on the passivation layer; A first photoresist pattern is formed on the first metal oxide preform layer. The first photoresist pattern has a first etch hole and a second etch hole. The first etch hole is disposed corresponding to one of the source and drain electrodes of the source-drain layer, and the second etch hole is disposed corresponding to the common electrode. Using the first photoresist pattern as a mask, the passivation layer corresponding to the first etched hole is etched to form a third via, the third via exposing at least a portion of the surface of one of the source and drain electrodes of the source-drain layer; at the same time, the passivation layer and the gate insulating layer corresponding to the second etched hole are etched to form a first via, the first via exposing at least a portion of the surface of the common electrode. as well as The first photoresist pattern is patterned to form a second photoresist pattern. Using the second photoresist pattern as a mask, the first metal oxide pre-film layer is etched to form a patterned first metal oxide layer.

7. The preparation method according to claim 6, characterized in that, Before etching the passivation layer and the gate insulating layer corresponding to the second etched hole to form the first via, the fabrication method further includes: Using the first photoresist pattern as a mask, the first metal oxide preform layer located in the first etch hole and the second etch hole is etched.

8. The preparation method according to claim 7, characterized in that, The step of patterning the first photoresist pattern to form the second photoresist pattern includes: A third etched hole and a fourth etched hole are formed on the first photoresist pattern, wherein... The third etched hole exposes the annular surface of the first metal oxide pre-film layer surrounding the third via. The fourth etched hole is located at the junction of the light-transmitting area and the non-light-transmitting area, and exposes the first metal oxide pre-film layer.

9. The preparation method according to claim 8, characterized in that, The step of etching the first metal oxide preform using the second photoresist pattern as a mask includes: Using the second photoresist pattern as a mask, the first metal oxide preform layer located in the third and fourth etch holes is etched to obtain a patterned first metal oxide layer.

10. The preparation method according to claim 6, characterized in that, The preparation method further includes: A patterned organic planarization layer is formed on the first metal oxide layer, the organic planarization layer including a second via that exposes at least a portion of the surface of the first metal oxide layer; A patterned second metal oxide layer is formed on the organic planarization layer, wherein the second metal oxide layer includes mutually insulated pixel electrodes and connection electrodes, wherein the pixel electrodes are connected to one of the source and drain electrodes of the source-drain layer through the third via, the connection electrodes are connected to the common electrode through the first via, and the connection electrodes are connected to the first metal oxide layer through the second via.

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