Liquid crystal display device

Abstract

The application discloses a liquid crystal display device, which comprises a liquid crystal display panel and a backlight module. The liquid crystal display panel comprises display data lines, display scan lines, a source driver and a gate drive circuit. The gate drive circuit is connected with the display scan lines, and the source driver is electrically connected with the display data lines and the gate drive circuit. The backlight module comprises backlight data lines, backlight scan lines, pixel circuits and a selection amplification circuit. The pixel circuits are connected with the backlight data lines and the backlight scan lines. The backlight scan lines are connected with the gate drive circuit. The selection amplification circuit is connected with the source driver and the backlight data lines. The display data lines and the backlight data lines are synchronously driven through the source driver. The common use of display driving and backlight driving is realized. The backlight driver and the design process thereof are reduced. The required driving hardware is reduced as a whole, and the hardware cost and the required occupied space for installation are reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a liquid crystal display device. Background Technology

[0002] Liquid crystal display devices typically require separate display driver and backlight driver components. However, the display driver and backlight driver components use different driver hardware, which increases hardware costs and space requirements. Summary of the Invention

[0003] This application provides a liquid crystal display device to alleviate the technical problem that display driving and backlight driving need to be implemented separately.

[0004] In a first aspect, this application provides a liquid crystal display device, which includes a liquid crystal display panel and a backlight module. The liquid crystal display panel includes display data lines, display scan lines, a source driver, and a gate driving circuit. The gate driving circuit is connected to the display scan lines, and the source driver is electrically connected to the display data lines and the gate driving circuit. The backlight module includes backlight data lines, backlight scan lines, a pixel circuit, and a selection amplification circuit. The pixel circuit is connected to the backlight data lines and the backlight scan lines, the backlight scan lines are connected to the gate driving circuit, and the selection amplification circuit is connected to the source driver and the backlight data lines.

[0005] In some implementations, the source driver operates in column inversion mode, and the selection amplifier circuit includes a selection circuit and an output buffer circuit. The selection circuit is connected to the source driver, and the output buffer circuit is connected to the selection circuit and the backlight data line.

[0006] In some embodiments, the selection circuit includes a selection module, the two input terminals of each selection module are connected to two adjacent output pins of the source driver, the control terminal of the selection module is connected to the clock output terminal of the source driver, and the output terminal of the selection module is connected to the output buffer circuit.

[0007] In some embodiments, each selection module includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the Nth output pin of the source driver, the second terminal of the first transistor is connected to an input terminal of the output buffer circuit, and the gate of the first transistor is connected to the clock output terminal of the source driver. The first terminal of the second transistor is connected to the N+1th output pin of the source driver, the second terminal of the second transistor is connected to the second terminal of the first transistor, and the gate of the second transistor is connected to the clock output terminal of the source driver.

[0008] In some embodiments, the channel type of the first transistor is the same as that of the second transistor, the gate of the first transistor is connected to the first clock output terminal of the source driver, and the gate of the second transistor is connected to the second clock terminal of the source driver.

[0009] In some implementations, the channel type of the first transistor is different from that of the second transistor, and a clock output terminal of the source driver is connected to the gate of the first transistor and the gate of the second transistor.

[0010] In some embodiments, the output buffer circuit includes amplifiers, with the non-inverting input of each amplifier connected to an output of the selection circuit, and the output of the amplifier connected to the inverting input of the amplifier and a corresponding backlight data line.

[0011] In some embodiments, the pixel circuit includes a light-emitting device and a reset transistor, the cathode of the light-emitting device being connected to a negative power supply line; the first terminal of the reset transistor being connected to the anode of the light-emitting device, the second terminal of the reset transistor being connected to the common voltage terminal of the source driver, and the gate of the reset transistor being connected to a control terminal of the source driver.

[0012] In some embodiments, the pixel circuit further includes a write transistor, a drive transistor, and a storage capacitor. The first terminal of the write transistor is connected to the backlight data line, and the gate of the write transistor is connected to the backlight scan line. The first terminal of the drive transistor is connected to the power output terminal of the source driver, the second terminal of the drive transistor is connected to the anode of the light-emitting device, and the gate of the drive transistor is connected to the second terminal of the write transistor. One end of the storage capacitor is connected to the gate of the drive transistor, and the other end of the storage capacitor is connected to the source or drain of the drive transistor.

[0013] In some implementations, the source driver provides a clock signal, a start control signal, and a constant voltage signal to the gate drive circuit.

[0014] The liquid crystal display device provided in this application synchronously drives the display data line and the backlight data line through the source driver, which not only realizes the sharing of the display driver and the backlight driver, but also reduces the backlight driver and its design process. This reduces the required driving hardware as a whole, thereby reducing the hardware cost and the space required for installation.

[0015] Furthermore, by synchronously driving the display scan lines and backlight scan lines through the gate drive circuit, the display driver and backlight driver can be shared, which further reduces the required driver hardware, thereby reducing hardware costs and installation space requirements. Attached Figure Description

[0016] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0017] Figure 1 This is a schematic diagram of a first structure of a liquid crystal display device provided in an embodiment of this application.

[0018] Figure 2 This is a schematic diagram of a second structure of the liquid crystal display device provided in an embodiment of this application.

[0019] Figure 3 This is a schematic diagram of a third structure of the liquid crystal display device provided in the embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0022] In view of the aforementioned technical problem that display drivers and backlight drivers need to be implemented separately, this embodiment provides a liquid crystal display device, such as... Figure 1 As shown, the liquid crystal display device includes a liquid crystal display panel and a backlight module. The liquid crystal display panel includes display data lines, display scan lines, a source driver 100, and a gate driving circuit 200. The gate driving circuit 200 is connected to the display scan lines, and the source driver 100 is electrically connected to the display data lines and the gate driving circuit 200. The backlight module includes backlight data lines, backlight scan lines, a pixel circuit 500, and a selection amplification circuit 300. The pixel circuit 500 is connected to the backlight data lines and the backlight scan lines. The backlight scan lines are connected to the gate driving circuit 200, and the selection amplification circuit 300 is connected to the source driver 100 and the backlight data lines.

[0023] It is understood that the liquid crystal display device provided in this embodiment synchronously drives the display data line and the backlight data line through the source driver 100, which not only realizes the sharing of display driver and backlight driver, but also reduces the backlight driver and its design process. This reduces the required driver hardware as a whole, thereby reducing hardware costs and the space required for installation.

[0024] Furthermore, by synchronously driving the display scan lines and backlight scan lines through the gate drive circuit 200, the sharing of display drive and backlight drive is further realized, which further reduces the required drive hardware, thereby reducing hardware costs and the space required for installation.

[0025] Furthermore, since the number of output pins of the source driver 100 is much greater than the number of output pins of the dedicated backlight driver, the number of backlight partitions 410 that each source driver 100 can drive is also much greater than the number of backlight partitions 410 that the backlight driver can drive.

[0026] It should be noted that the display scan lines are used to provide display scan signals to the liquid crystal display panel. The display data lines are used to provide display data signals to the liquid crystal display panel. The backlight scan lines are used to provide backlight scan signals (BGS) to the backlight module. The backlight data lines are used to provide backlight data signals (BDS) to the backlight module. The pixel circuit 500 is used to provide the corresponding backlight. The selection amplifier circuit 300 is used to select the required polarity of the backlight data signal (BDS) and improve its driving capability.

[0027] In this embodiment, the source driver 100 can be a source driver chip, which has higher integration, occupies less space and has more output pins, which is beneficial to increasing the number of backlight partitions 410 it drives.

[0028] In this embodiment, the source driver 100 may have the function of a timing controller. That is, the timing controller may be integrated into the source driver 100 to further improve the integration and reduce the occupied border space.

[0029] In one embodiment, such as Figure 1 As shown, the source driver 100 operates in column inversion mode. The selection amplifier circuit 300 includes a selection circuit 310 and an output buffer circuit 320. The selection circuit 310 is connected to the source driver 100. The output buffer circuit 320 is connected to the selection circuit 310 and the backlight data line.

[0030] It should be noted that the selection circuit 310 in this embodiment is used to select the positive polarity backlight data signal BDS and provide it to the output buffer circuit 320 to provide the driving capability of the positive polarity backlight data signal BDS.

[0031] In other embodiments, the source driver 100 may also operate in dot flip mode, line flip mode or frame flip mode. Correspondingly, the selection circuit 310 can select the backlight data signal BDS of the corresponding polarity according to the charging requirements of the pixel circuit 500.

[0032] In one embodiment, such as Figure 1As shown, the selection circuit 310 includes a selection module 311. The two input terminals of each selection module 311 are connected to two adjacent output pins of the source driver 100. The control terminal of the selection module 311 is connected to the clock output terminal of the source driver 100. The output terminal of the selection module 311 is connected to the output buffer circuit 320.

[0033] It should be noted that the clock output terminal of the source driver 100 can output corresponding clock signals CK7 and / or CK8. The selection module 311 outputs a backlight data signal BDS of the required polarity according to the clock signal CK7 and / or clock signal CK8 to charge the corresponding pixel circuit 500.

[0034] In one embodiment, such as Figure 1 As shown, each selection module 311 includes a first transistor M1 and a second transistor M2. The first terminal of the first transistor M1 is connected to the Nth output pin of the source driver 100, the second terminal of the first transistor M1 is connected to an input terminal of the output buffer circuit 320, and the gate of the first transistor M1 is connected to the clock output terminal of the source driver 100. The first terminal of the second transistor M2 is connected to the N+1th output pin of the source driver 100, the second terminal of the second transistor M2 is connected to the second terminal of the first transistor M1, and the gate of the second transistor M2 is connected to the clock output terminal of the source driver 100.

[0035] It should be noted that N can be an integer such as 1, 2, 3, etc. For example, when N equals 1, the first output pin S1 of the source driver 100 is electrically connected to the first electrode of the first transistor M1 from left to right, and the second output pin S2 of the source driver 100 is electrically connected to the first electrode of the first transistor M2 from left to right. When N equals 2, the third output pin S3 of the source driver 100 is electrically connected to the first electrode of the second transistor M1 from left to right, and the fourth output pin S4 of the source driver 100 is electrically connected to the first electrode of the second transistor M2 from left to right. Other transistors can be deduced similarly.

[0036] In other words, the first terminal of the first transistor M1 can be connected to the odd-numbered output pin of the source driver 100, and the first terminal of the second transistor M2 can be connected to the even-numbered output pin of the source driver 100. Thus, in column-flipping mode, each selection module 311 can always select the backlight data signal BDS of the required polarity from two adjacent output pins of the source driver 100.

[0037] In this configuration, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, when the first electrode is the source, the second electrode is the drain; or, when the first electrode is the drain, the second electrode is the source.

[0038] In one embodiment, such as Figure 1 As shown, the channel type of the first transistor M1 is the same as that of the second transistor M2. The gate of the first transistor M1 is connected to the first clock output terminal of the source driver 100, and the gate of the second transistor M2 is connected to the second clock terminal of the source driver 100.

[0039] It should be noted that in this embodiment, the first clock output terminal can be used to output one of the clock signals CK7 and CK8, and the second clock output terminal can be used to output the other of the clock signals CK7 and CK8. This allows the first transistor M1 and the second transistor M2 to be turned on in a time-division manner; that is, when the first transistor M1 is in the on state, the second transistor M2 is in the off state; or, when the first transistor M1 is in the off state, the second transistor M2 is in the on state.

[0040] In one embodiment, such as Figure 1 As shown, the channel type of the first transistor M1 is different from that of the second transistor M2, and a clock output terminal of the source driver 100 is connected to the gate of the first transistor M1 and the gate of the second transistor M2.

[0041] It should be noted that, compared with the previous embodiment, this embodiment only requires one clock output terminal of the source driver 100 to realize the time-division conduction of the first transistor M1 and the second transistor M2, and also reduces the number of traces from the source driver 100 to the selection circuit 310.

[0042] In one embodiment, such as Figure 1 As shown, the output buffer circuit 320 includes amplifiers OP. The non-inverting input terminal of each amplifier OP is connected to an output terminal of the selection circuit 310, and the output terminal of the amplifier OP is connected to the inverting input terminal of the amplifier OP and a corresponding backlight data line.

[0043] It should be noted that in this embodiment, the amplifier OP operates under negative feedback amplification, which not only improves the output capability but also stabilizes the gain of the amplifier OP to provide stable amplification capability.

[0044] In one embodiment, such as Figure 1 As shown, the pixel circuit 500 includes a light-emitting device D1 and a reset transistor T3. The cathode of the light-emitting device D1 is connected to the negative power supply line; the first terminal of the reset transistor T3 is connected to the anode of the light-emitting device D1, the second terminal of the reset transistor T3 is connected to the common voltage terminal of the source driver 100, and the gate of the reset transistor T3 is connected to a control terminal of the source driver 100.

[0045] It should be noted that the common voltage terminal is used to provide the common voltage signal VCOM. A control terminal of the source driver 100 is used to provide an enable signal EN, which can control the reset transistor T3 to release the residual charge on the anode of the light-emitting device D1 after emitting light, so as to improve the accuracy of the brightness of the light-emitting device D1 in the next emission.

[0046] The light-emitting device D1 can be an organic light-emitting diode, a micro light-emitting diode, a mini light-emitting diode, or a quantum dot light-emitting diode. The negative power line is used to transmit the negative power signal VSS.

[0047] In one embodiment, the pixel circuit 500 further includes a write transistor T2, a drive transistor T1, and a storage capacitor Cst. The first terminal of the write transistor T2 is connected to the backlight data line, and the gate of the write transistor T2 is connected to the backlight scan line. The first terminal of the drive transistor T1 is connected to the power output terminal of the source driver 100, the second terminal of the drive transistor T1 is connected to the anode of the light-emitting device D1, and the gate of the drive transistor T1 is connected to the second terminal of the write transistor T2. One end of the storage capacitor Cst is connected to the gate of the drive transistor T1, and the other end of the storage capacitor Cst is connected to the source or drain of the drive transistor T1.

[0048] It should be noted that the power output terminal of the source driver 100 is used to provide a positive power signal VDD. In other embodiments, the other end of the storage capacitor Cst can also be connected to the negative power supply line.

[0049] In one embodiment, the source driver 100 provides a clock signal, a start control signal STV, and a constant voltage signal to the gate drive circuit 200.

[0050] It should be noted that the clock signals can be at least two of CK1-CK6. The number of clock signals can also be greater, for example, an integer number such as 8, 10, or 12.

[0051] The start control signal STV can be used to trigger the gate drive circuit 200 to start outputting the corresponding scan signal. This scan signal can be used as a display scan signal or as a backlight scan signal BGS. The constant voltage signal can include a high-potential signal VGH and a low-potential signal VGL. The high-potential signal VGH can turn on the N-channel thin-film transistor or turn off the P-channel thin-film transistor, and the low-potential signal VGL can turn on the P-channel thin-film transistor or turn off the N-channel thin-film transistor.

[0052] It should be noted that the backlight area 400 of the backlight module may include multiple backlight partitions 410, and each backlight area 400 may contain one or more pixel circuits 500. These multiple pixel circuits 500 can be configured as follows: Figure 2 The array shown is distributed in the backlight area 400.

[0053] One backlight scan line can be connected to a row of pixel circuits 500. One backlight data line can be connected to a column of pixel circuits 500.

[0054] In one embodiment, the liquid crystal display device further includes a driver board 600 and a flexible circuit board 700 (FPC). The driver board 600 receives externally provided video data, which may be, but is not limited to, low voltage differential signal (LVDS), and transmits it to the source driver 100 via the flexible circuit board 700.

[0055] It should be noted that the driver board 600 also includes a DC-DC conversion circuit 610, which converts the received external voltage into various DC voltages required by the liquid crystal display device.

[0056] It should be noted that you should refer to [link / reference]. Figure 1 , Figure 2 The working principle of the above-mentioned liquid crystal display device can be described as follows:

[0057] The video data (backlight zone control data) is transmitted to the source driver 100 in the form of low voltage differential signal (LVDS). The source driver 100 converts the received video data from digital to analog and then outputs it to the selection amplifier circuit 300 in the form of voltage through each output pin (e.g., S1-S4).

[0058] Taking the source driver 100 operating in column-flip mode as an example, when the selection amplifier circuit 300 receives the backlight data signal BDS output by the source driver 100, if the polarity of the backlight data signal BDS output by the odd-numbered output pin is positive, then the clock signal CK7 is at a high potential to control each first transistor M1 to be in the conducting state; while the clock signal CK8 is at a low potential to control each second transistor M2 to be in the cut-off state. In this way, the selected positive polarity backlight data signal BDS can be transmitted to the output buffer circuit 320 to enhance the charging capability.

[0059] Alternatively, if the polarity of the backlight data signal BDS output by the even-numbered output pin is positive, then the clock signal CK8 is at a high potential to control each second transistor M2 to be in the conducting state; while the clock signal CK7 is at a low potential to control each first transistor M1 to be in the cut-off state.

[0060] When the selected amplifier circuit 300 outputs the backlight data signal BDS of the corresponding polarity, the source driver 100 controls the gate drive circuit 200 to output the corresponding backlight scan signal BGS, so as to control the write transistor T2 to write the backlight data signal BDS to the gate of the drive transistor T1 and the storage capacitor Cst. After the storage capacitor Cst is fully charged, the drive transistor T1 is turned on, and the light-emitting device D1 begins to provide backlight.

[0061] The process continues to scan all pixel circuits 500 line by line. Once all pixel circuits 500 have provided backlight, the reset transistor T3 is turned on to reset the anode potential of the light-emitting device D1.

[0062] like Figure 3 The liquid crystal display device shown also includes a lower POL (polarizer) located between the backlight module and the liquid crystal display panel, and an upper POL (polarizer) located on the side of the liquid crystal display panel away from the backlight module.

[0063] The backlight module may include at least one of a backlight unit (BLU), a reflector, a light guide plate, a diffuser, and a prism.

[0064] A liquid crystal display panel may include a TFT (array substrate), a CF (color filter substrate), and liquid crystal located between the array substrate and the color filter substrate.

[0065] The light source provided by the backlight unit passes sequentially through at least one of the following: a reflector, a light guide plate, a diffuser, and a prism, followed by a lower polarizer, an array substrate, a color filter substrate, and an upper polarizer, so that the image displayed on the liquid crystal display panel enters the human eye.

[0066] There are generally two light emission methods for backlight units: one is side emission, which has higher power but lower contrast; the other is local dimming, which has lower power and higher contrast. Preferably, the backlight module provided in this application operates in the local dimming light emission mode.

[0067] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0068] The liquid crystal display device provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A liquid crystal display device, characterized in that, The liquid crystal display device includes: A liquid crystal display panel, comprising display data lines, display scan lines, a source driver, and a gate driving circuit, wherein the gate driving circuit is connected to the display scan lines, and the source driver is electrically connected to the display data lines and the gate driving circuit; and A backlight module, comprising a backlight data line, a backlight scan line, a pixel circuit, and a selection amplification circuit, wherein the pixel circuit is connected to the backlight data line and the backlight scan line, the backlight scan line is connected to the gate driving circuit, and the selection amplification circuit is connected to the source driver and the backlight data line; The source driver operates in column inversion mode, and the selection amplifier circuit includes: A selection circuit, the selection circuit being connected to the source driver; and An output buffer circuit is connected to the selection circuit and the backlight data line. The selection circuit includes a selection module. The two input terminals of each selection module are connected to two adjacent output pins of the source driver. The control terminal of the selection module is connected to the clock output terminal of the source driver. The output terminal of the selection module is connected to the output buffer circuit.

2. The liquid crystal display device according to claim 1, characterized in that, Each of the selection modules includes: A first transistor, wherein the first terminal of the first transistor is connected to the Nth output pin of the source driver, the second terminal of the first transistor is connected to an input terminal of the output buffer circuit, and the gate of the first transistor is connected to the clock output terminal of the source driver; and The second transistor has its first terminal connected to the (N+1)th output pin of the source driver, its second terminal connected to the second terminal of the first transistor, and its gate connected to the clock output terminal of the source driver.

3. The liquid crystal display device according to claim 2, characterized in that, The first transistor has the same channel type as the second transistor, the gate of the first transistor is connected to the first clock output terminal of the source driver, and the gate of the second transistor is connected to the second clock terminal of the source driver.

4. The liquid crystal display device according to claim 2, characterized in that, The channel type of the first transistor is different from that of the second transistor, and a clock output terminal of the source driver is connected to the gate of the first transistor and the gate of the second transistor.

5. The liquid crystal display device according to claim 1, characterized in that, The output buffer circuit includes an amplifier, the non-inverting input of each amplifier is connected to an output of the selection circuit, and the output of the amplifier is connected to the inverting input of the amplifier and a corresponding backlight data line.

6. The liquid crystal display device according to any one of claims 1-5, characterized in that, The pixel circuit includes: A light-emitting device, wherein the cathode of the light-emitting device is connected to a negative power supply line; and A reset transistor, wherein the first terminal of the reset transistor is connected to the anode of the light-emitting device, the second terminal of the reset transistor is connected to the common voltage terminal of the source driver, and the gate of the reset transistor is connected to a control terminal of the source driver.

7. The liquid crystal display device according to claim 6, characterized in that, The pixel circuit also includes: A write transistor, wherein the first terminal of the write transistor is connected to the backlight data line, and the gate of the write transistor is connected to the backlight scan line; A driving transistor, wherein the first terminal of the driving transistor is connected to the power output terminal of the source driver, the second terminal of the driving transistor is connected to the anode of the light-emitting device, and the gate of the driving transistor is connected to the second terminal of the writing transistor; and A storage capacitor, one end of which is connected to the gate of the driving transistor, and the other end of which is connected to the source or drain of the driving transistor.

8. The liquid crystal display device according to any one of claims 1-5, characterized in that, The source driver provides a clock signal, a start control signal, and a constant voltage signal to the gate drive circuit.

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