Pixel driving circuit, display panel

Abstract

The application provides a pixel driving circuit and a display panel. The pixel driving circuit comprises a compensation module electrically connected with a second node and a third node, so as to adjust the difference between the pressure difference of the second node and the third node electrically connected with a pixel electrode and the pressure difference between the first node and the second node electrically connected with a first data line, thereby reducing the leakage current of the pixel electrode electrically connected with the second node, prolonging the holding time of the pixel voltage, and reducing the screen refresh rate. The display panel comprises a sub-pixel, and the sub-pixel comprises the compensation module.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel driving circuit and a display panel. BACKGROUND

[0002] Low frequency driving transistor is made by using low leakage characteristic of indium gallium zinc oxide transistor, which can reduce the leakage speed of pixel electrode, so that the display panel realizes low frequency display in a way of reducing leakage current. However, the realization of low frequency display by using indium gallium zinc oxide transistor needs to introduce new material, and the reduction degree is limited. SUMMARY

[0003] The pixel driving circuit and the display panel provided by the embodiments of the present application can reduce the leakage speed of pixel electrode, prolong the holding time of pixel voltage, and reduce the screen refresh rate.

[0004] The pixel driving circuit provided by the embodiments of the present application comprises a driving module, a storage module and a power compensation module. The driving module is electrically connected to a first node through a first data line, and is electrically connected to a pixel electrode through a second node. The driving module is configured to transmit a first data signal transmitted by the first data line to the second node through the first node according to a scanning signal. The storage module is electrically connected between the pixel electrode and a common electrode. The power compensation module is electrically connected between the second node and a third node, and is configured to adjust the pressure difference between the second node and the third node according to a control signal.

[0005] Optionally, in some embodiments of the present application, the driving module comprises a driving transistor, the source and the drain of the driving transistor are electrically connected between the first node and the second node, and the gate of the driving transistor is configured to receive the scanning signal. The storage module comprises a capacitor, and the capacitor is connected in series between the pixel electrode and the common electrode. The power compensation module comprises a power compensation transistor, the source and the drain of the power compensation transistor are electrically connected between the second node and the third node, and the gate of the power compensation transistor is configured to receive the control signal.

[0006] Optionally, in some embodiments of the present application, the third node is electrically connected to a second data line, and the second data line is configured to transmit a second data signal. The first data signal corresponds to a voltage with a first polarity in a blanking interval phase, the second data signal corresponds to a voltage with a second polarity in the blanking interval phase, and the first polarity and the second polarity are opposite.

[0007] Optionally, in some embodiments of the present application, the compensation transistor is an N-type transistor, and the control signal is a direct-current low power signal; or the compensation transistor is a P-type transistor, and the control signal is a direct-current high power signal.

[0008] Optionally, in some embodiments of the present application, the channel width-length ratio of the driving transistor is the same as the channel width-length ratio of the compensation transistor.

[0009] Optionally, in some embodiments of the present application, the compensation module comprises a compensation capacitor connected in series between the third node and the common electrode. In the blanking interval phase, the voltage difference between the third node and the second node is equal to the voltage difference between the second node and the first node.

[0010] The present application also provides a display panel comprising a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixels. The plurality of scan lines and the plurality of data lines are arranged in a cross manner. Each of the sub-pixels comprises at least a driving transistor, a compensation module, and a capacitor. One of the source and the drain of the driving transistor is electrically connected to the corresponding data line through a first node, the other of the source and the drain of the driving transistor is electrically connected to a pixel electrode of the sub-pixel through a second node, and the gate of the driving transistor is electrically connected to the corresponding scan line. The capacitor is connected in series between the pixel electrode and a common electrode. The compensation module is electrically connected between the second node and a third node, and is configured to adjust the voltage difference between the second node and the third node according to a control signal.

[0011] Optionally, in some embodiments of the present application, the compensation module comprises a compensation transistor, the source and the drain of the compensation transistor are electrically connected between the second node and the third node, the gate of the compensation transistor is electrically connected to a control line, and the control line is configured to transmit the control signal.

[0012] Optionally, in some embodiments of the present application, the plurality of data lines comprises a first data line and a second data line arranged adjacently, and the plurality of sub-pixels comprises a first sub-pixel and a second sub-pixel arranged adjacently along the extension direction of the scan lines. The driving transistor of the first sub-pixel is electrically connected to the first data line, the compensation transistor of the first sub-pixel is electrically connected to the second data line through the third node, and the driving transistor of the second sub-pixel is electrically connected to the second data line. The first data signal transmitted by the first data line corresponds to a voltage with a first polarity in a blanking interval phase, the second data signal transmitted by the second data line corresponds to a voltage with a second polarity in the blanking interval phase, and the first polarity and the second polarity are opposite.

[0013] Optionally, in some embodiments of the present application, the power compensation module further comprises a power compensation capacitor connected in series between the third node and the common electrode. In the blanking interval phase, the voltage difference between the third node and the second node is equal to the voltage difference between the second node and the first node.

[0014] The present application provides a pixel driving circuit and a display panel. The pixel driving circuit comprises a power compensation module electrically connected to a second node and a third node. The power compensation module adjusts the voltage difference between the second node and the third node electrically connected to a pixel electrode and the voltage difference between the first node and the second node electrically connected to a first data line. The leakage current of the pixel electrode electrically connected to the second node is reduced, the holding time of the pixel voltage is prolonged, and the screen refresh rate is reduced. The display panel comprises a sub-pixel, and the sub-pixel comprises a power compensation module. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the following embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figures 1A-1B is a structural schematic diagram of the pixel driving circuit provided by the embodiments of the present application;

[0017] Figures 2A-2B is a timing diagram provided by the embodiments of the present application;

[0018] Figure 3 is a structural schematic diagram of the display panel provided by the embodiments of the present application;

[0019] Figures 4A-4C is a structural schematic diagram of the sub-pixel provided by the embodiments of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower of the device in the actual use or working state, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the outline of the device.

[0021] Specifically, Figures 1A-1B is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application. The embodiment of the present application provides a pixel driving circuit, which comprises a driving module 100, a storage module 200 and a power supply module 300.

[0022] The driving module 100 is electrically connected with a first data line DL1 through a first node N1, the driving module 100 is electrically connected with a second node N2, and the driving module 100 is configured to transmit a first data signal data1 transmitted by the first data line DL1 to the second node N2 through the first node N1 according to a scan signal Gate.

[0023] Optionally, the pixel driving circuit can be applied to a passive light-emitting display panel (such as a liquid crystal display panel), a self-luminous display panel and the like.

[0024] Optionally, the pixel driving circuit can be applied to a passive light-emitting display panel, and the display panel comprises a pixel electrode and a common electrode Com, and the driving module 100 is electrically connected with the pixel electrode through the second node N2.

[0025] Optionally, the driving module 100 comprises a driving transistor T1, the source and the drain of the driving transistor T1 are electrically connected between the first node N1 and the second node N2, the gate of the driving transistor T1 is electrically connected with a scan line SL, and the gate of the driving transistor T1 is configured to receive the scan signal Gate transmitted by the scan line SL.

[0026] The storage module 200 is electrically connected between the pixel electrode and the common electrode Com.

[0027] Optionally, the storage module 200 comprises a capacitor C1, and the capacitor C1 is electrically connected with the second node N2.

[0028] Optionally, the capacitor C1 is connected in series between the pixel electrode and the common electrode Com.

[0029] Optionally, the capacitor C1 comprises a storage capacitor and a liquid crystal capacitor. Optionally, the storage capacitor and the liquid crystal capacitor are connected in parallel between the pixel electrode and the common electrode Com. Optionally, the storage capacitor is connected in series between the second node N2 and a corresponding scan line, and the liquid crystal capacitor is connected in parallel between the pixel electrode and the common electrode Com.

[0030] The power compensation module 300 is electrically connected to the second node N2 and the third node N3, and is configured to adjust the voltage difference between the second node N2 and the third node N3 according to a control signal VG.

[0031] By including the power compensation module 300 in the pixel driving circuit, the voltage difference between the second node N2 and the third node N3 is adjusted, and the difference between the voltage difference between the second node N2 and the third node N3 and the voltage difference between the first node N1 and the second node N2 is adjusted, so that the leakage current of the pixel electrode electrically connected to the second node N2 in the display panel using the pixel driving circuit is reduced, the holding time of the pixel voltage is prolonged, and the screen refresh rate is reduced.

[0032] Optionally, please continue to refer to Figures 1A-1B The power compensation module 300 includes a power compensation transistor T2, the source and drain of the power compensation transistor T2 are electrically connected between the second node N2 and the third node N3, and the gate of the power compensation transistor T2 is configured to receive the control signal VG.

[0033] Optionally, the channel width-length ratio of the driving transistor T1 and the channel width-length ratio of the power compensation transistor T2 are the same or different.

[0034] Optionally, the channel width-length ratio of the driving transistor T1 and the channel width-length ratio of the power compensation transistor T2 are the same, so that the driving transistor T1 and the power compensation transistor T2 have the same leakage current capability, thereby forming effective complementarity between the leakage current between the first node N1 and the second node N2 and the leakage current between the second node N2 and the third node N3, and effectively reducing the leakage current speed at the second node N2.

[0035] Optionally, the channel width-length ratio of the driving transistor T1 and the channel width-length ratio of the power compensation transistor T2 are determined to be the same or different according to the display requirements of the display panel using the pixel driving circuit. For example, the channel width-length ratio of the driving transistor T1 and the channel width-length ratio of the power compensation transistor T2 are determined according to the performance of the display panel using the pixel driving circuit when displaying a certain gray scale (such as a gray scale that shows display problems or a gray scale that can show the best display performance).

[0036] Optionally, the voltage difference between the second node N2 and the third node N3 can be adjusted by directly applying a voltage to the third node N3, or the potential change of the third node N3 can be adjusted by related devices, thereby achieving the adjustment of the voltage difference between the second node N2 and the third node N3.

[0037] Please continue to refer toFigure 1A The third node N3 is electrically connected with a second data line DL2, and the second data line DL2 is configured to transmit a second data signal data2. The first data signal data1 has a voltage of a first polarity corresponding to a blanking interval stage Blank, and the second data signal data2 has a voltage of a second polarity corresponding to the blanking interval stage Blank, and the first polarity and the second polarity are opposite.

[0038] By making the first data signal data1 transmitted by the first data line DL1 and the second data signal data2 transmitted by the second data line DL2 have opposite polarities in the blanking interval stage Blank, the pressure difference between the second node N2 and the third node N3 is similar to the pressure difference between the first node N1 and the second node N2, and the leakage current between the first node N1 and the second node N2 is complementary to the leakage current between the second node N2 and the third node N3, thereby reducing the leakage current speed at the second node N2, and further delaying the leakage rate of the pixel electrode of the display panel using the pixel driving circuit.

[0039] Optionally, the blanking interval stage Blank includes at least one of a horizontal blanking interval stage and a vertical blanking interval stage.

[0040] Optionally, to avoid the second data signal data2 directly affecting the potential of the second node N2 (for example, when the first data signal data1 is transmitted to the second node N2 or when the blanking interval stage Blank, the compensation transistor T2 is turned on, which will cause the second data signal data2 to affect the potential of the second node N2; the display panel using the pixel driving circuit will have display problems due to the potential change of the second node N2), the compensation transistor T2 always maintains a cut-off state during the working stage of the pixel driving circuit.

[0041] Optionally, the compensation transistor T2 is an N-type transistor, and the control signal VG is a direct-current low power signal; or the compensation transistor T2 is a P-type transistor, and the control signal VG is a direct-current high power signal.

[0042] Optionally, during the blank interval stage Blank, the first data signal data1 has a voltage equal in absolute value to a voltage of the second data signal data2, so as to achieve the gray scale display requirement of the display panel to which the pixel driving circuit is applied. For example, according to the highest gray scale (e.g., 255 gray scale) that can be achieved by the display panel to which the pixel driving circuit is applied, it is determined that the first data signal data1 has a voltage of 5V and the second data signal data2 has a voltage of -5V during the blank interval stage Blank.

[0043] Optionally, during the blank interval stage Blank, the voltage of the first data signal data1 and the voltage of the second data signal data2 can be set according to the use requirement.

[0044] Optionally, please refer to Figure 1B , the power supply module 300 further comprises a power supply capacitor C2 electrically connected to the third node N3. Wherein, during the blank interval stage Blank, the voltage difference between the third node N3 and the second node N2 is equal to the voltage difference between the second node N2 and the first node N1, so as to make the leakage current between the first node N1 and the second node N2 and the leakage current between the second node N2 and the third node N3 complementary to each other during the blank interval stage Blank, and reduce the degree of potential change at the second node N2.

[0045] Optionally, the power supply capacitor C2 is connected in series between the third node N3 and the first voltage terminal.

[0046] Optionally, the pixel driving circuit can be applied to a passive light-emitting display panel, and the power supply capacitor C2 is connected in series between the third node N3 and the common electrode Com, so as to reduce the leakage rate of the pixel electrode through the power supply transistor T2 and the power supply capacitor C2.

[0047] Figures 2A-2B is a timing diagram provided by an embodiment of the present application; wherein, Figure 2A is a timing diagram corresponding to Figure 1A , the timing diagram of the pixel driving circuit, Figure 2B is a timing diagram corresponding to Figure 1B , the timing diagram of the pixel driving circuit. Taking an example of the driving transistor T1 and the power supply transistor T2 both being N-type transistors, the working principle of the pixel driving circuit is described.

[0048] Please refer to Figure 1A and Figure 2A , the working process of the pixel driving circuit comprises a first stage t1 and a blank interval stage Blank.

[0049] In the first stage t1, when the scan signal Gate is high, the driving transistor T1 is turned on, and the first data signal data1 charges the second node N2; the control signal VG is a direct current low power signal, so that the complementary power transistor T2 is always in the off state, thereby avoiding the first data signal data1 being transmitted to the third node N3 through the second node N2, and also avoiding the second data signal data2 being transmitted to the second node N2 through the third node N3.

[0050] In the blanking interval stage Blank, the scan signal Gate makes the driving transistor T1 in the off state, and the control signal VG still makes the complementary power transistor T2 in the off state, the first data line DL1 applies a voltage with a first polarity to the first node N1, and the second data line DL2 applies a voltage with a second polarity to the third node N3. At this time, the leakage current between the first node N1 and the second node N2 and the leakage current between the second node N2 and the third node N3 flow in opposite directions, so that the leakage speed at the second node N2 is slowed down.

[0051] In the prior art, if the complementary power module 300 is not set, only the leakage current between the first node N1 and the second node N2 exists, so that the potential of the second node N2 is affected by the leakage current between the first node N1 and the second node N2 and changes. After the complementary power module 300 is set, the leakage current between the second node N2 and the third node N3 can be used to balance the leakage current between the first node N1 and the second node N2, so that the potential of the second node N2 can be kept from changing too much.

[0052] Optionally, if the potential at the second node N2 is positive during the blanking interval phase, the first data line DL1 can apply a positive voltage to the first node N1, and the second data line DL2 can apply a negative voltage to the third node N3. In this case, if the pixel driving circuit does not include the supplementary transistor T2 and the second data line DL2, leakage current will occur between the second node N2 and the first node N1 via the driving transistor T1, with the leakage current flowing from the first data line DL1 to the second node N2. After setting the supplementary transistor T2, a new leakage path is added. In this case, the current in the supplementary transistor T2 flows from the second node N2 to the second data line DL2. For the second node N2, the leakage current flowing through the driving transistor T1 flows into the second node N2, and the leakage current flowing through the supplementary transistor T2 flows out of the second node N2. The leakage current velocity at the second node N2 is reduced due to the influence of the leakage current flowing through the driving transistor T1 and the leakage current flowing through the supplementary transistor T2.

[0053] Optionally, during the blanking interval phase, the potential at the second node N2 is negative, the first data line DL1 can apply a negative voltage to the first node N1, and the second data line DL2 can apply a positive voltage to the third node N3.

[0054] Please continue reading. Figure 1B and Figure 2B The operation of the pixel driving circuit includes a first charging stage t11, a second charging stage t12, and a blanking interval stage.

[0055] During the first charging phase t11, when the scan signal Gate and the control signal VG are at a high level, the driving transistor T1 and the charging transistor T2 are turned on, and the first data signal data1 charges the second node N2 and the third node N3 so that the third node N3 has a first voltage V1.

[0056] During the second charging phase t12, the scan signal Gate is at a high level, the control signal VG is at a low level, the driving transistor T1 is still on, the charging transistor T2 is off, and the first data signal data1 continues to charge the second node N2 so that the second node N2 has a second voltage V2.

[0057] In the blanking interval phase Blank, the scan signal Gate makes the driving transistor T1 in the off state, the control signal VG still makes the compensation transistor T2 in the off state, and the first data line DL1 applies a third voltage V3 to the first node N1, so that the difference between the third voltage V3 and the second voltage V2 is equal to the difference between the second voltage V2 and the first voltage V1 (i.e. V3-V2 = V2-V1). At this time, the leakage current between the first node N1 and the second node N2 and the leakage current between the second node N2 and the third node N3 flow in opposite directions, so that the leakage speed at the second node N2 is slowed down.

[0058] Figure 3 is a structural schematic diagram of a display panel provided by an embodiment of the present application; Figures 4A-4C is a structural schematic diagram of a sub-pixel provided by an embodiment of the present application. The present application further provides a display panel, comprising a plurality of data lines DL, a plurality of scan lines SL, and a plurality of sub-pixels SPi.

[0059] The plurality of scan lines SL and the plurality of data lines DL are arranged in a cross manner. Optionally, the plurality of sub-pixels SPi are located in regions defined by the intersection of the plurality of scan lines SL and the plurality of data lines DL.

[0060] Each of the sub-pixels SPi comprises at least a driving transistor T1, a compensation module, and a capacitor C1.

[0061] Optionally, one of the source and the drain of the driving transistor T1 is electrically connected to the corresponding data line DL through a first node N1, the other of the source and the drain of the driving transistor T1 is electrically connected to a pixel electrode of the sub-pixel SPi through a second node N2, and the gate of the driving transistor T1 is electrically connected to the corresponding scan line SL.

[0062] The capacitor C1 is connected in series between the pixel electrode and a common electrode Com. Optionally, the capacitor C1 comprises a storage capacitor and a liquid crystal capacitor connected in parallel.

[0063] The compensation module is electrically connected to the second node N2 and a third node N3, and is configured to adjust the voltage difference between the second node N2 and the third node N3 according to a control signal VG.

[0064] By making the sub-pixel SPi correspond to include the compensation module, the difference between the pressure difference between the second node N2 and the third node N3 of the sub-pixel SPi and the pressure difference between the first node N1 and the second node N2 is reduced by adjusting the pressure difference between the second node N2 and the third node N3 of the sub-pixel SPi, and then the leakage rate of the sub-pixel SPi corresponding to the second node N2 is reduced, thereby delaying the leakage rate of the pixel electrode of the sub-pixel SPi, which is beneficial to reduce the refresh rate of the display panel and reduce power consumption.

[0065] Optionally, please continue to refer to Figure 3 and Figures 4A-4C The compensation module includes a compensation transistor T2, the source and drain of the compensation transistor T2 are electrically connected between the second node N2 and the third node N3, and the gate of the compensation transistor T2 is electrically connected with the control line VGL, and the control line VGL is configured to transmit the control signal VG.

[0066] Optionally, the channel width-length ratio of the driving transistor T1 and the channel width-length ratio of the compensation transistor T2 are the same or different.

[0067] Optionally, the please continue to refer to Figure 4A A plurality of data lines include a first data line DL1 and a second data line DL2 arranged adjacent to each other; a plurality of sub-pixels SPi include a first sub-pixel SPi1 and a second sub-pixel SPi2 adjacent in the extension direction of the scan line SL; the driving transistor T11 of the first sub-pixel SPi1 is electrically connected with the first data line DL1, the compensation transistor T21 of the first sub-pixel SPi1 is electrically connected with the second data line DL2 through the third node N31 of the first sub-pixel SPi1, and the driving transistor T12 of the second sub-pixel SPi2 is electrically connected with the second data line DL2.

[0068] The first data signal data1 transmitted by the first data line DL1 has a voltage of a first polarity corresponding to the blanking interval stage Blank, and the second data signal data2 transmitted by the second data line DL2 has a voltage of a second polarity corresponding to the blanking interval stage Blank, the first polarity and the second polarity being opposite, so that the leakage current between the first node N11 and the second node N21 of the first sub-pixel SPi1 and the leakage current between the second node N21 and the third node N31 of the first sub-pixel SPi1 are complementary to each other, so as to reduce the leakage current speed at the second node N21 of the first sub-pixel SPi1, and in turn slow down the leakage rate of the pixel electrode of the first sub-pixel SPi1.

[0069] Optionally, the plurality of data lines further comprises a third data line DL3 located on the side of the second data line DL2 away from the first data line DL1, and a fourth data line DL4 located on the side of the third data line DL3 away from the second data line DL2; the plurality of sub-pixels SPi further comprises a third sub-pixel SPi3 located on the side of the second sub-pixel SPi2 away from the first sub-pixel SPi1. The complementary power transistor T22 of the second sub-pixel SPi2 is electrically connected to the third data line DL3 through the third node N32 of the second sub-pixel SPi2, the driving transistor T13 of the third sub-pixel SPi3 is electrically connected to the third data line DL3 through the first node N13 of the third sub-pixel SPi3, and the complementary power transistor T23 of the third sub-pixel SPi3 is electrically connected to the fourth data line DL4 through the third node N33 of the third sub-pixel SPi3. The third data signal transmitted by the third data line DL3 has a voltage of a third polarity corresponding to the blanking interval stage Blank, and the fourth data signal transmitted by the fourth data line DL4 has a voltage of a fourth polarity corresponding to the blanking interval stage Blank, the third polarity and the fourth polarity being opposite, so that the leakage current between the first node N13 and the second node N23 of the third sub-pixel SPi3 and the leakage current between the second node N23 and the third node N33 of the third sub-pixel SPi3 are complementary to each other, so as to reduce the leakage current speed at the second node N23 of the third sub-pixel SPi3, and in turn slow down the leakage rate of the pixel electrode of the third sub-pixel SPi3.

[0070] Optionally, the third polarity and the second polarity are opposite, so that the leakage current between the first node N12 and the second node N22 of the second sub-pixel SPi2 and the leakage current between the second node N22 and the third node N32 of the second sub-pixel SPi2 are complementary to reduce the leakage current speed at the second node N2 of the second sub-pixel SPi2, thereby slowing down the leakage rate of the pixel electrode of the second sub-pixel SPi2.

[0071] By multiplexing the same data line DL for two adjacent sub-pixels SPi along the extension direction of the scan line SL, the number of data lines DL included in the display panel can be reduced while slowing down the leakage rate of the pixel electrode of multiple sub-pixels SPi, thereby reducing the manufacturing cost and saving layout space.

[0072] Optionally, the display panel includes a plurality of pixels, and the plurality of pixels are arranged in an array or mirror image. Each of the pixels includes the first sub-pixel SPi1, the second sub-pixel SPi2, and the third sub-pixel SPi. Optionally, the light-emitting color of the first sub-pixel SPi1 includes red, the light-emitting color of the second sub-pixel SPi2 includes green, and the light-emitting color of the third sub-pixel SPi3 includes blue.

[0073] Optionally, referring to Figure 4A , the compensation transistor T2 is an N-type transistor, and the control signal VG is a direct-current low power supply signal; or the compensation transistor T2 is a P-type transistor, and the control signal VG is a direct-current high power supply signal, so as to reduce the direct influence of the compensation transistor T2 on the potential of the second node N2.

[0074] Since the compensation transistor T2 is always in an off state, even if the first sub-pixel SPi1 and the second sub-pixel SPi2 are both electrically connected to the second data line DL2, the second data signal data2 transmitted on the second data line DL2 will not directly affect the potential of the second node N21 of the first sub-pixel SPi1 when the driving transistor T11 of the first sub-pixel SPi1 and the driving transistor T12 of the second sub-pixel SPi2 are turned on and during the blanking interval phase Blank.

[0075] Optionally, referring to Figure 4B, the first sub-pixel SPi1 and the second sub-pixel SPi2 can also not multiplex the second data line DL2, but use an additional data line. Correspondingly, the voltage transmitted by the additional second data line DL2 in the blanking interval phase Blank still maintains the opposite polarity to the voltage transmitted by the first data line DL1. Wherein, Figure 4B DL11 represents the first data line to which the first sub-pixel SPi1 is electrically connected, and DL21 represents the second data line to which the first sub-pixel SPi1 is electrically connected; DL12 represents the first data line to which the second sub-pixel SPi2 is electrically connected, and DL22 represents the second data line to which the second sub-pixel SPi2 is electrically connected; DL13 represents the first data line to which the third sub-pixel SPi3 is electrically connected, and DL23 represents the second data line to which the third sub-pixel SPi3 is electrically connected.

[0076] Optionally, please continue to refer to Figure 4C , the power supply module further includes a power supply capacitor C2 connected in series between the third node N3 and the common electrode Com. Wherein, in the blanking interval phase Blank, the voltage difference between the third node N3 and the second node N2 is equal to the voltage difference between the second node N2 and the first node N1, so as to make the leakage current between the first node N1 and the second node N2 of the sub-pixel SPi complementary to the leakage current between the second node N2 and the third node N3 of the sub-pixel SPi in the blanking interval phase Blank, and slow down the leakage rate of the sub-pixel SPi.

[0077] Optionally, the control signal VG transmitted by the control line VGL is configured to control the third node N3 of the sub-pixel SPi to have a first voltage in a first charging phase located before the blanking interval phase Blank, and control the power supply transistor T2 of the sub-pixel SPi to be off in a second charging phase located between the first charging phase and the blanking interval phase Blank. The scan signal Gate transmitted by the scan line SL is configured to control the driving transistor T1 to be on in the first charging phase, and control the driving transistor T1 to be on in the second charging phase to make the second node N2 of the sub-pixel SPi have a second voltage. The data line DL to which the first node N1 of the sub-pixel SPi is electrically connected has a third voltage in the blanking interval phase Blank, so as to make the voltage difference between the third node N3 and the second node N2 of the sub-pixel SPi equal to the voltage difference between the second node N2 and the first node N1 of the sub-pixel SPi in the blanking interval phase Blank.

[0078] Optionally, the extension direction of the control line VGL is the same as the extension direction of the scan line SL.

[0079] Optionally, the application also provides a display device, which comprises any of the above display panel or any of the above pixel driving circuit.

[0080] The principles and implementation modes of the present application are described herein by using specific examples, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation modes and application ranges will have changes, and the above description should not be understood as a limitation on the present application.

Claims

1. A pixel driving circuit, characterized by comprising: The pixel driving circuit comprises: a driving module electrically connected to a first node and a second node, and configured to transmit a first data signal transmitted by a first data line to the second node through the first node according to a scan signal; a storage module electrically connected between the pixel electrode and a common electrode; and a compensation module electrically connected between the second node and a third node, and configured to adjust a voltage difference between the second node and the third node according to a control signal; the compensation module comprises a compensation transistor, the compensation transistor is always in an off state during a working stage of the pixel driving circuit; the third node is electrically connected to a second data line, and the second data line is configured to transmit a second data signal; wherein the first data signal has a first polarity voltage corresponding to a blanking interval stage, the second data signal has a second polarity voltage corresponding to the blanking interval stage, and the first polarity and the second polarity are opposite.

2. The pixel driving circuit according to claim 1, wherein the driving module comprises a driving transistor, a source and a drain of the driving transistor are electrically connected between the first node and the second node, and a gate of the driving transistor is configured to receive the scan signal; the storage module comprises a capacitor, the capacitor is connected in series between the pixel electrode and the common electrode; a source and a drain of the compensation transistor are electrically connected between the second node and the third node, and a gate of the compensation transistor is configured to receive the control signal.

3. The pixel driving circuit according to claim 1, wherein the compensation transistor is an N-type transistor, and the control signal is a direct-current low power signal; or the compensation transistor is a P-type transistor, and the control signal is a direct-current high power signal. a channel width-length ratio of the driving transistor is the same as a channel width-length ratio of the compensation transistor.

4. The pixel driving circuit of claim 2, wherein, the compensation module comprises a compensation capacitor, the compensation capacitor is connected in series between the third node and the common electrode; 5. The pixel driving circuit of claim 2, wherein, wherein, during the blanking interval stage, a voltage difference between the third node and the second node is equal to a voltage difference between the second node and the first node. The pixel driving circuit comprises:

6. A display panel, characterized by, a plurality of data lines; a plurality of scan lines intersecting the plurality of data lines; a plurality of sub-pixels, each of the sub-pixels comprising at least a driving transistor, a compensation module, and a capacitor; wherein one of a source and a drain of the driving transistor is electrically connected to a corresponding data line through a first node, the other of the source and the drain of the driving transistor is electrically connected to a pixel electrode of the sub-pixel through a second node, a gate of the driving transistor is electrically connected to a corresponding scan line; the capacitor is connected in series between the pixel electrode and a common electrode; the compensation module is electrically connected between the second node and a third node, and is configured to adjust a voltage difference between the second node and the third node according to a control signal; the compensation module comprises a compensation transistor, the compensation transistor is always in an off state during a working stage of the sub-pixel. ​ The plurality of data lines include a first data line and a second data line arranged adjacently; the plurality of sub-pixels include a first sub-pixel and a second sub-pixel arranged adjacently along the extension direction of the scan lines; the driving transistor of the first sub-pixel is electrically connected with the first data line, the complementary power transistor of the first sub-pixel is electrically connected with the second data line through the third node, and the driving transistor of the second sub-pixel is electrically connected with the second data line; wherein the first data signal transmitted by the first data line corresponds to a voltage with a first polarity in a blanking interval phase, the second data signal transmitted by the second data line corresponds to a voltage with a second polarity in the blanking interval phase, and the first polarity and the second polarity are opposite.

7. The display panel of claim 6, wherein, The source and the drain of the complementary power transistor are electrically connected between the second node and the third node, and the gate of the complementary power transistor is electrically connected with a control line configured to transmit the control signal.

8. The display panel of claim 7, wherein, The complementary power module further includes a complementary power capacitor connected in series between the third node and the common electrode. In the blanking interval phase, the voltage difference between the third node and the second node is equal to the voltage difference between the second node and the first node.

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