A fast transient response LDO

Abstract

The application discloses a fast transient response LDO, and belongs to the field of integrated circuits. The MP7 in the form of a diode connection can realize load tracking compensation of a loop by changing the resistance of the gate end of the output power tube MP8, the stability of the LDO under a full load range is improved through the load tracking compensation, the LDO is limited to the output capacitor C OUT and the parasitic resistance R ESR of the output capacitor C OUT The common source amplifier composed of the NMOS tube MN6 and the PMOS tube MP6 can improve the charging and discharging speed of the gate end of the power tube when the load jump changes, improve the loop gain, and the LDO transient large signal response speed is accelerated through the loop gain enhancement, and the LDO transient voltage fluctuation is reduced; the circuit transient performance can be improved through the above optimization.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fast transient response LDO. Background Art

[0002] Advances in semiconductor technology have led to a surge in demand for low-voltage IC systems. However, due to increasing device integration and functionality, the power consumption of modern IC systems operating at low voltages has increased rather than decreased. Designing an LDO for low-voltage applications that delivers high current output capability and minimizes output voltage fluctuations during load changes presents significant challenges.

[0003] In LDO applications where the LDO provides low-voltage power and high-current output, the traditional solution is to place a large external capacitor at the LDO output to reduce output voltage fluctuations during load changes. This capacitor uses its energy storage properties to provide the required load current when the LDO loop cannot respond to load changes in a timely manner. Figure 1 The figure shows the specific architecture of the traditional LDO for low voltage power supply and high current output applications. Figure 2 The loop response is shown as the output capacitance C OUT Schematic diagram of changes. Figure 1 The LDO in the figure is a zero-point architecture with main pole compensation at the output. The output capacitor C OUT and R ESR (C OUT The zero point z formed by the parasitic resistance ESR Used for power tube M power The secondary point p2 at the gate end is compensated to ensure that the loop is a single-pole system within the bandwidth gain bandwidth UGF. Figure 2 It can be seen that with C OUT Increase the main pole by p 1A Reduce to p 1B The loop bandwidth also decreases accordingly, △UGF. As UGF decreases, the loop response speed slows down. Therefore, traditional LDOs for low-voltage power supply and high-current output applications have the following problems:

[0004] 1. Cost and small signal bandwidth requirements C OUT Small enough but loop stability requires C OUT A big enough contradiction.

[0005] 2. Figure 1 Zhong Sui C OUT Decrease, R ESR Need to be increased accordingly so that both produce zero point z ESR Fixed, thus keeping z ESR Effective compensation for the loop secondary pole, but R ESR The increase of will lead to an increase in output voltage fluctuation when the load jumps. Summary of the Invention

[0006] The purpose of the present invention is to provide a fast transient response LDO to solve the problem that conventional LDOs for low voltage power supply and high current output have conflicting requirements on output capacitance value between transient response speed and loop stability.

[0007] To solve the above technical problems, the present invention provides a fast transient response LDO, comprising a first resistor, a second resistor, a first capacitor, a second capacitor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor; wherein,

[0008] The upper end of the first resistor is connected to the external reference voltage V REF The lower end is connected to the drain of the second NMOS tube; the upper end of the second resistor is connected to the output port V OUT , the lower end is connected to the upper end of the second capacitor;

[0009] The upper end of the first capacitor is connected to the gate terminal of the second NMOS transistor, and the lower end is grounded GND; the upper end of the second capacitor is connected to the lower end of the second resistor, and the lower end is grounded GND;

[0010] The drain terminal of the first NMOS tube is connected to the source terminal of the eighth NMOS tube, the gate terminal is connected to the lower end of the first resistor, and the source terminal is grounded GND; the drain terminal of the second NMOS tube is connected to the lower end of the first resistor, the gate terminal is connected to the lower end of the first resistor, and the source terminal is grounded GND; the drain terminal of the third NMOS tube is connected to the drain terminal of the ninth PMOS tube, the gate terminal is connected to the lower end of the first resistor, and the source terminal is grounded GND; the drain terminal of the fourth NMOS tube is connected to the drain terminal of the fourth PMOS tube, the gate terminal is connected to the lower end of the first resistor, and the source terminal is grounded GND; the drain terminal of the fifth NMOS tube is connected to the drain terminal of the fifth PMOS tube, the gate terminal is connected to the The gate terminal of the seventh NMOS tube is connected to the ground GND; the drain terminal of the sixth NMOS tube is connected to the drain terminal of the sixth PMOS tube, the gate terminal is connected to the drain terminal of the fifth PMOS tube, and the source terminal is connected to the ground GND; the drain terminal of the seventh NMOS tube is connected to the drain terminal of the tenth PMOS tube, the gate terminal is connected to the drain terminal of the tenth PMOS tube, and the source terminal is connected to the ground GND; the drain terminal of the eighth NMOS tube is connected to the drain terminal of the first PMOS tube, the gate terminal is connected to the drain terminal of the third PMOS tube, and the source terminal is connected to the drain terminal of the first NMOS tube; the drain terminal of the ninth NMOS tube is connected to the drain terminal of the second PMOS tube, and the gate terminal is connected to the external reference voltage V REF , the source terminal is connected to the drain terminal of the first NMOS tube;

[0011] The drain terminal of the first PMOS tube is connected to the drain terminal of the eighth NMOS tube, the gate terminal is connected to the drain terminal of the eighth NMOS tube, and the source terminal is connected to the power supply voltage VDD; the drain terminal of the second PMOS tube is connected to the drain terminal of the ninth NMOS tube, the gate terminal is connected to the drain terminal of the ninth NMOS tube, and the source terminal is connected to VDD; the drain terminal of the third PMOS tube is connected to the source terminal of the ninth PMOS tube, the gate terminal is connected to the gate terminal of the second PMOS tube, and the source terminal is connected to VDD; the drain terminal of the fourth PMOS tube is connected to the drain terminal of the fourth NMOS tube, the gate terminal is connected to the drain terminal of the fourth NMOS tube, and the source terminal is connected to VDD; the drain terminal of the fifth PMOS tube is connected to the drain terminal of the fifth NMOS tube, the gate terminal is connected to the gate terminal of the fourth PMOS tube, and the source terminal is connected to VDD; the drain terminal of the sixth PMOS tube is connected to the drain terminal of the sixth NMOS tube, the gate terminal is connected to the gate terminal of the fifth PMOS tube, and the source terminal is connected to VDD; the drain terminal of the seventh PMOS tube is connected to the drain terminal of the sixth PMOS tube, the gate terminal is connected to the gate terminal of the sixth PMOS tube, and the source terminal is connected to VDD; the drain terminal of the eighth PMOS tube is connected to the output port V OUT , the gate terminal is connected to the gate terminal of the seventh PMOS tube, and the source terminal is connected to VDD; the drain terminal of the ninth PMOS tube is connected to the drain terminal of the third NMOS tube, the gate terminal is connected to the drain terminal of the third NMOS tube, and the source terminal is connected to the drain terminal of the third PMOS tube; the drain terminal of the tenth PMOS tube is connected to the drain terminal of the seventh NMOS tube, the gate terminal is connected to the gate terminal of the ninth PMOS tube, and the source terminal is connected to the output port V OUT .

[0012] In one embodiment, the sixth NMOS transistor and the sixth PMOS transistor form a common-source amplifier. OUT When a load jump occurs, the charging and discharging speed of the power tube gate terminal is improved.

[0013] In one embodiment, the tenth PMOS transistor is a common-gate amplifier, and its gate bias voltage is generated by a clamping structure composed of the first NMOS transistor, the third NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the ninth PMOS transistor. The seventh NMOS transistor, the fifth NMOS transistor, and the fifth PMOS transistor serve as current mirror loads of the common-gate amplifier.

[0014] In one embodiment, the second resistor is a parasitic resistor of the second capacitor.

[0015] In one embodiment, the gate-source voltage difference of the seventh PMOS transistor is consistent with that of the eighth PMOS transistor.

[0016] The fast transient response LDO provided by the present invention has the following beneficial effects:

[0017] (1) Load tracking compensation improves the stability of the LDO under the full load range and reduces the LDO's dependence on the output capacitor C OUTand the limitation of the value of parasitic resistance RESR;

[0018] (2) By enhancing the loop gain, the charging and discharging speed of the power tube gate is improved, the LDO transient large signal response speed is accelerated, and the LDO transient voltage fluctuation is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of a traditional LDO circuit for low-voltage power supply and high-current output applications.

[0020] Figure 2 This is a traditional LDO circuit for low voltage power supply and high current output applications. Its loop response varies with the output capacitor C. OUT Schematic diagram of changes;

[0021] Figure 3 This is a structural diagram of a fast transient response LDO circuit with load tracking compensation and loop gain enhancement characteristics proposed by the present invention. DETAILED DESCRIPTION

[0022] The following is a detailed description of a fast transient response LDO proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0023] The present invention provides a fast transient response LDO circuit with load tracking compensation and loop gain enhancement characteristics. Figure 3 For its specific circuit implementation. Figure 3 In the example, the diode-connected MP7 can achieve load tracking compensation for the loop by changing the gate resistance of the output power tube MP8. The load tracking compensation improves the stability of the LDO under the full load range and reduces the LDO's dependence on the output capacitor C. OUT and its parasitic resistance R ESR The common source amplifier composed of NMOS tube MN6 and PMOS tube MP6 can be OUT When a load jump occurs, the charging and discharging speed of the power tube gate terminal is increased, the loop gain is improved, and the loop gain enhancement speed is accelerated by the LDO transient large signal response speed and the LDO transient voltage fluctuation is reduced. The above optimization can improve the transient performance of the circuit.

[0024] The circuit structure of the present invention is as follows Figure 3 As shown, the resistors R1 and R ESR , capacitor C1, capacitor C OUT, NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor MN5, NMOS transistor MN6, NMOS transistor MN7, NMOS transistor MN8, NMOS transistor MN9, PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, PMOS transistor MP4, PMOS transistor MP5, PMOS transistor MP6, PMOS transistor MP7, PMOS transistor MP8, PMOS transistor MP9 and PMOS transistor MP10.

[0025] The upper end of resistor R1 is connected to the external reference voltage V REF , the lower end is connected to the drain end of NMOS tube MN2; the resistor R ESR The upper end is connected to the output port V OUT , the lower end is connected to the capacitor C OUT The upper end of capacitor C1 is connected to the gate of NMOS tube MN2, and the lower end is grounded GND; capacitor C OUT The upper termination resistor R ESR The drain terminal of the NMOS tube MN1 is connected to the source terminal of the NMOS tube MN8, the gate terminal is connected to the lower end of the resistor R1, and the source terminal is grounded GND; the drain terminal of the NMOS tube MN2 is connected to the lower end of the resistor R1, the gate terminal is connected to the lower end of the resistor R1, and the source terminal is grounded GND; the drain terminal of the NMOS tube MN3 is connected to the drain terminal of the PMOS tube MP9, the gate terminal is connected to the lower end of the resistor R1, and the source terminal is grounded GND; the drain terminal of the NMOS tube MN4 is connected to the drain terminal of the PMOS tube MP4, the gate terminal is connected to the lower end of the resistor R1, and the source terminal is grounded GND; the drain terminal of the NMOS tube MN5 is connected to the drain terminal of the PMOS tube MP5, the gate terminal is connected to the lower end of the resistor R1, and the source terminal is grounded GND. The gate of the NMOS transistor MN7 is connected to the ground, and the source is grounded GND. The drain of the NMOS transistor MN6 is connected to the drain of the PMOS transistor MP6, the gate is connected to the drain of the PMOS transistor MP5, and the source is grounded GND. The drain of the NMOS transistor MN7 is connected to the drain of the PMOS transistor MP10, the gate is connected to the drain of the PMOS transistor MP10, and the source is grounded GND. The drain of the NMOS transistor MN8 is connected to the drain of the PMOS transistor MP1, the gate is connected to the drain of the PMOS transistor MP3, and the source is connected to the drain of the NMOS transistor MN1. The drain of the NMOS transistor MN9 is connected to the drain of the PMOS transistor MP2, and the gate is connected to the external reference voltage V REF, the source terminal is connected to the drain terminal of the NMOS tube MN1; the drain terminal of the PMOS tube MP1 is connected to the drain terminal of the NMOS tube MN8, the gate terminal is connected to the drain terminal of the NMOS tube MN8, and the source terminal is connected to the power supply voltage VDD; the drain terminal of the PMOS tube MP2 is connected to the drain terminal of the NMOS tube MN9, the gate terminal is connected to the drain terminal of the NMOS tube MN9, and the source terminal is connected to VDD; the drain terminal of the PMOS tube MP3 is connected to the source terminal of the PMOS tube MP9, the gate terminal is connected to the gate terminal of the PMOS tube MP2, and the source terminal is connected to VDD; the drain terminal of the PMOS tube MP4 is connected to the drain terminal of the NMOS tube MN4 The drain and gate terminals are connected to the drain of NMOS tube MN4, and the source terminal is connected to VDD; the drain of PMOS tube MP5 is connected to the drain of NMOS tube MN5, the gate terminal is connected to the gate of PMOS tube MP4, and the source terminal is connected to VDD; the drain of PMOS tube MP6 is connected to the drain of NMOS tube MN6, the gate terminal is connected to the gate of PMOS tube MP5, and the source terminal is connected to VDD; the drain of PMOS tube MP7 is connected to the drain of PMOS tube MP6, the gate terminal is connected to the gate of PMOS tube MP6, and the source terminal is connected to VDD; the drain of PMOS tube MP8 is connected to the output port V OUT The gate terminal is connected to the gate terminal of the PMOS tube MP7, and the source terminal is connected to VDD; the drain terminal of the PMOS tube MP9 is connected to the drain terminal of the NMOS tube MN3, the gate terminal is connected to the drain terminal of the NMOS tube MN3, and the source terminal is connected to the drain terminal of the PMOS tube MP3; the drain terminal of the PMOS tube MP10 is connected to the drain terminal of the NMOS tube MN7, the gate terminal is connected to the gate terminal of the PMOS tube MP9, and the source terminal is connected to the output port V OUT .

[0026] The working principle of the present invention is:

[0027] Figure 3 In the figure, PMOS transistor MP8 represents the circuit's output power transistor; PMOS transistor MP10 is a common-gate amplifier, whose gate-terminal bias voltage is generated by a clamping structure consisting of NMOS transistors MN1, MN3, MN8, MN9, PMOS transistors MP1, MP2, MP3, and MP9. NMOS transistors MN7, MN5, and PMOS transistor MP5 serve as the current mirror load of this common-gate amplifier, the output of which is at the gate of NMOS transistor MN6. Load tracking compensation is achieved by diode-connected PMOS transistor MP7, which changes the small-signal resistance at the gate of PMOS transistor MP8 under different load conditions. A low-ESR, low-capacitance output capacitor C can be selected. OUT The purpose of stabilizing the circuit. The loop gain enhancement is achieved by the common source amplifier NMOS tube MN6 and PMOS tube MP6. The external input reference voltage V REF Resistor R1 and diode-connected NMOS transistor MN2 generate the bias current required for circuit operation. Capacitor C1 is a filter capacitor that protects the bias current from interference from noise signals.

[0028] Figure 3 The circuit contains three left half plane poles and one left half plane zero. The main pole p1 is located at the output of the circuit, the first pole p2 is located at the gate of the output power tube MP8, the second pole p3 is located at the gate of the NMOS tube MN6, and the zero z1 is located at the output of the circuit, which can achieve frequency compensation for the first pole p2. To achieve this, a low ESR and low capacitance output capacitor C OUT To compensate the loop and ensure the circuit can work stably, it is necessary to reasonably set the device parameters in the circuit so that p2>>z1>p1>UGF is established, so as to ensure that the circuit is a single-pole system within its unity gain bandwidth (UGF).

[0029] Under the conditions that the above relationship holds, for p1, p2, p3, z1 and unity gain bandwidth UGF:

[0030]

[0031] Where r in formula (1) ds(MP8) is the drain-source resistance of the output power tube MP8, g m(MP10) is the transconductance of the PMOS tube MP10.

[0032]

[0033] In formula (2), C gs(MP8) is the parasitic capacitance between the gate and source of the output power tube MP8, C gd(MP8) is the parasitic capacitance between the gate and drain of the output power tube MP8, g m(MP7) is the transconductance of the PMOS tube MP7, g m(MP8) is the transconductance of the output power tube MP8, g m(MP10) is the transconductance of the PMOS tube MP10, r ds(MN6) is the drain-source resistance of NMOS tube MN6, r ds(MP6) is the drain-source resistance of the PMOS tube MP6, r ds(MP8) is the drain-source resistance of the PMOS tube MP8. Since the output power tube MP8 has a large area, C gs(MP8) and C gd(MP8) Can not be ignored. From formula (2), we can see that p2 and g m(MP7) Approximately proportional, the gate-source voltage difference of the PMOS tube MP7 is consistent with that of the output power tube MP8. MP7 samples the current of MP8. Therefore, as the load current increases, p2 moves toward high frequency, and the loop can maintain stability.

[0034]

[0035] In formula (3), C gs(MN6) is the parasitic capacitance between the gate and source of NMOS tube MN6, C gd(MN6)is the parasitic capacitance between the gate and drain of MN6, g m(MN6) is the transconductance of MN6, r ds(MN5) is the drain-source resistance of NMOS tube MN5, r ds(MP5) is the drain-source resistance of the PMOS transistor MP5. From formula (3), we can see that the size of the NMOS transistor MN6 should not be too large, and it is necessary to ensure that p2>>z1>p1>UGF holds.

[0036]

[0037] Formula (4) shows that UGF is proportional to g m(MN6) , proving that the loop gain is improved after adopting the common-source amplifier composed of MN6 and MP6.

[0038] In the design proposed by the present invention, the response speed of the LDO large signal transient is not limited by the bandwidth. When a load jump occurs, Figure 3 The middle circuit can still achieve fast transient response under the condition of small bias current. When the transient transition occurs from no-load to full-load, the pull-down current of the gate terminal of the output power tube MP8 is determined by the NMOS tube MN6. The gate terminal voltage of the NMOS tube MN6 can fluctuate in the range of close to 0 to VDD. Therefore, the pull-down current of the gate terminal of the output power tube MP8 in the transient state can exceed the limit of the bias current of MN6 in the steady state. When the transient transition occurs from full load to no-load, the PMOS tube MP7 can provide the additional pull-up current required by the gate terminal of the output power tube MP8. Therefore, the pull-up current of the gate terminal of the output power tube MP8 in the transient state can exceed the limit of the bias current of the PMOS tube MP6 in the steady state. From the above analysis, it can be seen that when the NMOS tube MN6 and the PMOS tube MP6 do not need a large bias current to achieve low quiescent current operation of the circuit, Figure 3 The medium circuit can still achieve fast transient response.

[0039] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A fast transient response LDO, characterized in that: The device includes a first resistor, a second resistor, a first capacitor, a second capacitor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor; wherein, The upper end of the first resistor is connected to the external reference voltage V REF , the lower end is connected to the drain end of the second NMOS tube; The upper end of the second resistor is connected to the output port V OUT , the lower end is connected to the upper end of the second capacitor; The upper end of the first capacitor is connected to the gate terminal of the second NMOS transistor, and the lower end is grounded GND; the upper end of the second capacitor is connected to the lower end of the second resistor, and the lower end is grounded GND; The drain terminal of the first NMOS tube is connected to the source terminal of the eighth NMOS tube, the gate terminal is connected to the lower end of the first resistor, and the source terminal is grounded GND; the drain terminal of the second NMOS tube is connected to the lower end of the first resistor, the gate terminal is connected to the lower end of the first resistor, and the source terminal is grounded GND; the drain terminal of the third NMOS tube is connected to the drain terminal of the ninth PMOS tube, the gate terminal is connected to the lower end of the first resistor, and the source terminal is grounded GND; the drain terminal of the fourth NMOS tube is connected to the drain terminal of the fourth PMOS tube, the gate terminal is connected to the lower end of the first resistor, and the source terminal is grounded GND; the drain terminal of the fifth NMOS tube is connected to the drain terminal of the fifth PMOS tube, the gate terminal is connected to the The gate terminal of the seventh NMOS tube is connected to the ground GND; the drain terminal of the sixth NMOS tube is connected to the drain terminal of the sixth PMOS tube, the gate terminal is connected to the drain terminal of the fifth PMOS tube, and the source terminal is connected to the ground GND; the drain terminal of the seventh NMOS tube is connected to the drain terminal of the tenth PMOS tube, the gate terminal is connected to the drain terminal of the tenth PMOS tube, and the source terminal is connected to the ground GND; the drain terminal of the eighth NMOS tube is connected to the drain terminal of the first PMOS tube, the gate terminal is connected to the drain terminal of the third PMOS tube, and the source terminal is connected to the drain terminal of the first NMOS tube; the drain terminal of the ninth NMOS tube is connected to the drain terminal of the second PMOS tube, and the gate terminal is connected to the external reference voltage V REF , the source terminal is connected to the drain terminal of the first NMOS tube; The drain terminal of the first PMOS tube is connected to the drain terminal of the eighth NMOS tube, the gate terminal is connected to the drain terminal of the eighth NMOS tube, and the source terminal is connected to the power supply voltage VDD; the drain terminal of the second PMOS tube is connected to the drain terminal of the ninth NMOS tube, the gate terminal is connected to the drain terminal of the ninth NMOS tube, and the source terminal is connected to VDD; the drain terminal of the third PMOS tube is connected to the source terminal of the ninth PMOS tube, the gate terminal is connected to the gate terminal of the second PMOS tube, and the source terminal is connected to VDD; the drain terminal of the fourth PMOS tube is connected to the drain terminal of the fourth NMOS tube, the gate terminal is connected to the drain terminal of the fourth NMOS tube, and the source terminal is connected to VDD; the drain terminal of the fifth PMOS tube is connected to the drain terminal of the fifth NMOS tube, the gate terminal is connected to the gate terminal of the fourth PMOS tube, and the source terminal is connected to VDD; the drain terminal of the sixth PMOS tube is connected to the drain terminal of the sixth NMOS tube, the gate terminal is connected to the gate terminal of the fifth PMOS tube, and the source terminal is connected to VDD; the drain terminal of the seventh PMOS tube is connected to the drain terminal of the sixth PMOS tube, the gate terminal is connected to the gate terminal of the sixth PMOS tube, and the source terminal is connected to VDD; the drain terminal of the eighth PMOS tube is connected to the output port V OUT , the gate terminal is connected to the gate terminal of the seventh PMOS tube, and the source terminal is connected to VDD; the drain terminal of the ninth PMOS tube is connected to the drain terminal of the third NMOS tube, the gate terminal is connected to the drain terminal of the third NMOS tube, and the source terminal is connected to the drain terminal of the third PMOS tube; the drain terminal of the tenth PMOS tube is connected to the drain terminal of the seventh NMOS tube, the gate terminal is connected to the gate terminal of the ninth PMOS tube, and the source terminal is connected to the output port V OUT .

2. The fast transient response LDO according to claim 1, wherein: The sixth NMOS tube and the sixth PMOS tube form a common source amplifier, and the output port V OUT When a load jump occurs, the charging and discharging speed of the power tube gate terminal is improved.

3. The fast transient response LDO according to claim 1, wherein: The tenth PMOS transistor is a common-gate amplifier, and its gate-end bias voltage is generated by a clamping structure composed of the first NMOS transistor, the third NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the ninth PMOS transistor. The seventh NMOS transistor, the fifth NMOS transistor, and the fifth PMOS transistor serve as a current mirror load for the common-gate amplifier.

4. The fast transient response LDO according to claim 1, wherein: The second resistor is a parasitic resistor of the second capacitor.

5. The fast transient response LDO according to claim 1, wherein: The gate-source voltage difference of the seventh PMOS tube is consistent with that of the eighth PMOS tube.

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