Data processing method, memory controller and storage system

Abstract

At least one embodiment of the present disclosure provides a data processing method, a memory controller, and a storage system. The data processing method includes: reading four burst data from a single storage channel; organizing the four burst data into a group of error correction codewords, wherein a group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of a codeword; and performing a decoding operation based on a group of error correction codewords to obtain a post-error correction codeword. The data processing method can realize simultaneous error correction of, for example, two or more codewords or symbols by reading four burst data from a single storage channel through a single ECC operation.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data processing method, a memory controller, a storage system, an electronic device, and a storage medium. Background Art

[0002] Data is easily disturbed by environmental factors during transmission, communication and storage, which may lead to data errors. For example, Double Data Rate (DDR) memory (e.g., DDR SDRAM or DDR memory) will inevitably be disturbed by environmental factors such as electromagnetics during operation, which may lead to memory errors. For users with high stability requirements, memory errors may cause fatal problems. For example, for servers, the reliability requirements for DDR data are relatively high. DDR memory error correction technology can improve the stability and error correction capabilities of server memory. For example, memory bars that support Error Correcting Code (ECC) can improve the stability and error correction capabilities of server memory.

[0003] For some DDR memory, when a correctable error (CE) occurs, the memory DIMM does not need to be replaced immediately. However, once an uncorrectable error (UE) occurs, if two memory particles have errors at the same time, an uncorrectable error will be reported. In this case, data will generally be lost and cannot be recovered. The loss of data will affect the processor or other computing units to perform corresponding operations, causing related functions or applications to fail to operate normally, or even cause downtime. Summary of the invention

[0004] A first aspect of the present disclosure provides a data processing method comprising: reading four burst data from a single storage channel; organizing the four burst data into a group of error correction codewords, wherein the group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of a codeword; and performing a decoding operation based on the group of error correction codewords to obtain error-corrected codewords.

[0005] A second aspect of the present disclosure provides a memory controller, comprising: a reading unit, configured to: read four burst data from a single storage channel; organize the four burst data into a group of error correction codewords, wherein the group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of a codeword; and a decoding unit, configured to: perform a decoding operation based on the group of error correction codewords to obtain error-corrected codewords.

[0006] A third aspect of the present disclosure provides a storage system, comprising: the memory controller as described above; and a storage unit including a single storage channel.

[0007] A fourth aspect of the present disclosure provides an electronic device, comprising: one or more processors; a memory, comprising one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the one or more processors to implement the processing method as described above.

[0008] A fifth aspect of the present disclosure provides a non-transitory readable storage medium having computer executable instructions stored thereon, wherein the computer executable instructions, when executed by a processor, implement the processing method as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure are briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0010] Figure 1 A flowchart showing a method for processing data according to at least one embodiment of the present disclosure is shown;

[0011] Figure 2 A schematic diagram of a memory controller according to at least one embodiment of the present disclosure is shown;

[0012] Figure 3 A structural diagram showing a method of simultaneously correcting errors in multiple memory chips according to at least one embodiment of the present disclosure is shown;

[0013] Figure 4 A schematic diagram of a storage system according to at least one embodiment of the present disclosure is shown;

[0014] Figure 5 A schematic diagram showing a memory subsystem according to at least one embodiment of the present disclosure is shown;

[0015] Figure 6 A schematic diagram showing an electronic device according to at least one embodiment of the present disclosure; and

[0016] Figure 7 A schematic diagram of a non-transitory readable storage medium according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0017] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. On the contrary, it is intended to cover changes, modifications and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0018] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0019] Note that the examples to be introduced below are only specific examples, and are not intended to limit the embodiments of the present disclosure to the specific shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct more embodiments not mentioned in the present description by reading the present description.

[0020] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0021] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0022] First, the abbreviations and related terms involved in this application are defined and explained.

[0023] Double-Symbol Correction (DSC): A technology that can correct two symbols at the same time.

[0024] DDR (Double Data Rate): double data rate.

[0025] DDR SDRAM: Double data rate synchronous dynamic random access memory, commonly known as DDR.

[0026] Error Check Correction (ECC): A technology that can implement "error checking and correction" to improve the stability of computer operation and increase reliability.

[0027] RS (Reed-Solomon) code: also known as Reed-Solomon code or Reed-solomon code, is a forward error correction channel code that is effective for polynomials generated by correcting oversampled data. RS code is a special type of non-binary BCH code with strong error correction capability. For any positive integer S, a corresponding q-based BCH code with a code length of n=qS-1 can be constructed, and q is a power of a prime number. When S=1, q>2, the q-based BCH code with a code length of n=q-1 is called RS code. When q=2 m (m>1), the binary RS code whose code element symbols are taken from F(2m) can be used to correct burst errors. It is the most commonly used RS code.

[0028] MDEC (Multi Device Error Correction): Multi-device error correction

[0029] SDDC (Single Device Data Correction): Corrects the data on a particle

[0030] DDDC (Double Device Data Correction): Corrects the data on two particles

[0031] Memory channel: referred to as channel for short. Each memory controller can have multiple memory channels, such as the common memory channel 0 and memory channel 1.

[0032] UE (Uncorrectable Error): Uncorrectable error.

[0033] CE (Correctable Error): Correctable error.

[0034] Data Device: A storage device that stores data. In DDR memory, it is also called a data memory device.

[0035] ECC Device: A storage device that stores check bits. In DDR memory, it is also called a check memory device.

[0036] Storage particles: Data storage particles and verification storage particles are collectively referred to as storage particles. Storage particles are also called memory particles in DDR memory, and can be used as a general term for data memory particles and verification memory particles.

[0037] Symbol: Also known as code element, the smallest unit of ECC error correction, usually with x4 and x8 particles, corresponding to 4 bits and 8 bits of data.

[0038] ECC Word, the object data for performing ECC operation, is embodied in the form of data bit + check information in a memory architecture supporting ECC.

[0039] It is understandable that the terms defined above are only exemplary definitions in specific application scenarios to facilitate a better understanding of the present application. For example, the exemplary definitions for specific memory described above can be extended to other types of memory or other storage.

[0040] For memory (such as DDR memory), if two storage particles fail at the same time, the current system will report an uncorrectable error, which cannot be corrected. After rereading, it is still an uncorrectable error, and the data will be lost. In serious cases, the system will cause a system crash. If hardware is used to record the previous correctable error location and other information and algorithm post-processing to achieve the purpose of correcting two memory particles one by one, some of the problems of two simultaneous errors can also be solved. However, there are a series of prerequisites and the coverage rate is low.

[0041] An exemplary mainstream method for correcting two errors is DDDC, which mainly includes the following points:

[0042] ●Lockstep needs to be turned on;

[0043] ●In terms of algorithm, ECC uses parity bit (Parity) + cyclic redundancy check code (CRC);

[0044] ●One algorithm operation can only correct one memory particle;

[0045] ●When the second memory chip needs to be corrected, the previously faulty memory chip must first be replaced and written into the redundant memory chip (spare device), and then the algorithm is used to find the second faulty memory chip.

[0046] ●Only errors of two memory chips can be corrected in time. If two memory chips fail at the same time, DDDC technology is powerless and the system will report an uncorrectable error.

[0047] The hardware structure used in the technology provided by at least one embodiment of the present disclosure does not require any prerequisites. When multiple data particles have random errors, each particle has an error of 1 to 2 bits. There is no need to open the lock synchronization, and there is no need for the hardware to record previous information. The hardware can complete the error correction of multiple particles, which can greatly improve the error correction capability. In addition, the reliability of the storage (such as memory) can be improved, and the risk of data loss and system downtime can be further reduced.

[0048] At least one embodiment of the present disclosure provides a data processing method and a memory controller, a storage system, an electronic device, and a storage medium. For example, when multiple storage particles fail at any time, and each storage particle fails, for example, 1-2 bits, the hardware structure of at least one embodiment of the present disclosure can simultaneously correct multiple storage particle errors without software involvement and without relying on historical record information. The reliability of the memory is greatly improved, and the risk of data loss and system downtime is reduced.

[0049] The following describes in detail a data processing method, a memory controller, a storage system, an electronic device, and a storage medium according to at least one embodiment of the present disclosure with reference to the accompanying drawings.

[0050] First, the data processing method of an embodiment of the present disclosure is introduced below. The data processing method can be applied to a memory controller, a storage system, an electronic device, and other suitable software or hardware, or a combination of hardware and software as further described below.

[0051] Figure 1 A flow chart of a data processing method 100 according to at least one embodiment of the present disclosure is shown. The processing method may include steps S102 to S106.

[0052] In step S102 , four burst data are read from a single storage channel.

[0053] In some embodiments, four burst data may correspond to encoded data stored in a single storage channel, the encoded data may be obtained by encoding k data code elements written into a single storage channel, the encoded data may include k data code elements and m check code elements, wherein the total bit width of the m check code elements is eight times the bit width of a code element.

[0054] In some embodiments, depending on the arrangement of the data storage particles and the check storage particles in the storage channel of the memory, the data bits and check bits included in each burst of data may change. For example, in an exemplary DDR4 or DDR5, a single storage channel may include 8 x4 data memory particles and 2 x4 check memory particles (ecc memory particles), and each burst of data (Burst) includes 8*4=32 bits of data bits and 2*4=8 bits of check bits. However, the present disclosure is not limited to this. However, it is understood that in order to correct a codeword, a check codeword with a bit width twice that of a codeword is generally required. For example, the bit width of a codeword is 4 bits, and an 8-bit check codeword is generally required for error correction.

[0055] In some embodiments, the data symbols can be decoded and error-corrected (if necessary) in a decoding operation to obtain data or instructions for performing calculations to achieve a predetermined function. The check symbols can provide information in decoding and error correction (if necessary) to ensure that correct data is obtained.

[0056] An exemplary memory channel may be one of two memory channels (memory channel 0 (Ch0) and memory channel 1 (Ch1)) such as in DDR4 or DDR5.

[0057] In step S104, four burst data are organized into a group of error correction codewords, wherein a group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of one codeword.

[0058] In some embodiments, the four burst data (also referred to herein as read-back coded data, which is essentially coded data read from a single storage channel) corresponds to the coded data in order to obtain corresponding correct data, but the coded data may be interfered by environmental factors such as electromagnetics during transmission or in the storage unit (including the storage channel), resulting in data errors. Therefore, the k read-back data symbols (i.e., data symbols read back from a single storage channel) and the m read-back check symbols (i.e., check symbols read back from a single storage channel) may be different from the k data symbols and m check symbols included in the coded data.

[0059] In some embodiments, the storage unit may be a memory itself, such as a DDR memory or a DDR internal memory. In other embodiments, the storage unit may be a storage array in the memory.

[0060] In step S106, a decoding operation is performed based on a set of error correction codewords to obtain error-corrected codewords.

[0061] The decoding operation here may refer to performing an ECC operation on the above-mentioned set of error correction codewords to obtain error-corrected data codewords and / or error-corrected check codewords.

[0062] Thus, the data processing method according to at least one embodiment of the present disclosure can realize simultaneous error correction of, for example, two or more code elements or symbols by reading four burst data from a single storage channel through one ECC operation. For example, without opening the lock synchronization, the problem of multiple code element half-chips having errors at the same time can be effectively solved.

[0063] In some examples, errors in two or more code elements or symbols may occur in two or more storage particles, and thus error correction of two or more storage particles may be implemented.

[0064] Other aspects of the data processing method of at least one embodiment of the present disclosure are described in detail below.

[0065] For example, according to the data processing method of at least one embodiment of the present disclosure, four burst data are organized into a group of error correction codewords, including: combining the burst data corresponding to the same pin of the same storage particle in the four burst data read by a single storage channel into one of k read back data code elements or m read back check code elements to obtain k read back data code elements and m read back check code elements; and connecting the k read back data code elements and the m read back check code elements to obtain a group of error correction codewords.

[0066] For example, the burst data corresponding to the same pin of the same data storage particle among the four burst data read by a single storage channel are combined into one of k read-back data code elements, and the data corresponding to the same verification storage particle among the four burst data read by a single storage channel are combined into one of m read-back verification code elements, thereby obtaining k read-back data code elements or m read-back verification code elements (collectively referred to as multiple symbols), and the multiple symbols are connected into a group of error correction code words (i.e., ECC words).

[0067] The inventors of the present disclosure realize that the erroneous bits in multiple data usually correspond to the pins of the same storage particle, and one pin corresponds to one bit of a data. For example, when an error occurs on a pin of a storage particle, the data corresponding to the pin from the multiple data are usually erroneous. Based on this, the data processing method according to at least one embodiment of the present disclosure takes the pins of the storage particles as units, combines the data corresponding to the same pins of the same storage particles in four bursts of data into one symbol (i.e., a 4-bit symbol), so as to obtain multiple symbols for a single storage channel, and connects the multiple symbols into a group of error correction codewords, i.e., forms a group of error correction codewords for a single storage channel. This organization method of ECC words based on the pins of storage particles can reflect the erroneous data for the same pin in four bursts of data into a single symbol, thereby improving the error correction capability.

[0068] Of course, the embodiments of the present disclosure are not limited to this. The data corresponding to the same pin of the same storage particle in four bursts of data can be divided into two or more units or combined into a symbol (i.e., a symbol of 8 bits or more bits) to obtain multiple symbols for a single storage channel, and the multiple symbols can be organized (for example, connected) into a group of error correction code words.

[0069] For example, according to the data processing method of at least one embodiment of the present disclosure, a single storage channel includes 8 data storage particles and 2 check storage particles. The bit width of each storage particle in the 8 data storage particles and the 2 check storage particles is 4 bits.

[0070] In this way, the data processing method according to at least one embodiment of the present disclosure can be applied to specific application scenarios. For example, a single storage channel can be one of Ch0 or Ch1 of DDR5 or other memories with the same structure to achieve error correction of multiple symbols of the corresponding memory.

[0071] Of course, the embodiments are not limited to this. In other variations, a single storage channel may include a first number of data storage particles and a second number of verification storage particles. The bit width of each storage particle in the data storage particles and the verification storage particles may be the same or different, and the bit width may be 4 bits, 8 bits, or other bits.

[0072] For example, according to the data processing method of at least one embodiment of the present disclosure, the same pin burst data corresponding to the same storage particle in four burst data read by a single storage channel are combined into a group of error correction codewords, including: performing the following operations on each storage particle in 8 data storage particles and 2 verification storage particles to obtain data including 32 data symbols and 8 verification symbols as a group of error correction codewords: organizing the data corresponding to the first bit of 4 bits in the four burst data into a first symbol; organizing the data corresponding to the second bit of 4 bits in the four burst data into a second symbol; organizing the data corresponding to the third bit of 4 bits in the four burst data into a third symbol; and organizing the data corresponding to the fourth bit of 4 bits in the four burst data into a fourth symbol.

[0073] In this way, the data processing method according to at least one embodiment of the present disclosure can implement the organization of ECC words with pins as units for 8 x4 data storage particles and 2 x4 check storage particles.

[0074] Of course, the embodiment is not limited thereto, and in other variations as described above, a group of error correction codewords may be similarly combined, as long as the data corresponding to the same bit in the plurality of bits in the four burst data are organized into one symbol.

[0075] For example, according to the data processing method of at least one embodiment of the present disclosure, the single storage channel is a single memory channel of DDR5. For example, the single memory channel can be Ch0 or Ch1 of DDR5.

[0076] In this way, the data processing method according to at least one embodiment of the present disclosure can be applicable to DDR5.

[0077] For example, according to the data processing method of at least one embodiment of the present disclosure, the encoding and decoding operations may use a Vandermonde matrix or RS code.

[0078] For the technology of Vandermonde-like matrix or RS code, for example, reference may be made to application publication number CN112688693A, entitled "A memory multi-matrix encoding method, error correction method and related device", application publication number CN116092567A, entitled "Data processing method, processing device and storage system", application publication number CN116028260A, entitled "Data processing method, processing device and storage system", application publication number CN110071727A, entitled "Encoding method, decoding method, error correction method and device". These applications are incorporated herein by reference and are made a part of this document.

[0079] The following exemplary descriptions describe how encoding and decoding operations may use one or more aspects of Vandermonde-like matrices.

[0080] For example, according to the data processing method of at least one embodiment of the present disclosure, k data symbols written into a single storage channel are encoded, including: encoding the k data symbols based on a coding matrix; performing a decoding operation based on a set of error correction codewords to obtain error-corrected symbols, including: decoding a set of error correction codewords based on a decoding matrix to obtain syndrome data; and obtaining the error-corrected symbols using the syndrome data, wherein the coding matrix is ​​a matrix of at least k+m rows and k columns and includes a quasi-Vandermonde matrix, and the decoding matrix is ​​a matrix of at least m rows and k+m columns and includes a quasi-Vandermonde matrix, wherein the quasi-Vandermonde matrix is ​​a matrix associated with the Vandermonde matrix, wherein k≤p n -1, m≤p n , where n is the number of bits in each symbol and p is the capacity of a single bit.

[0081] Thus, the data processing method according to at least one embodiment of the present disclosure is based on a Vandermonde-like matrix, which can support more check symbols and data symbols relative to RS codes, thereby improving the code rate, thereby improving the error correction capability, and being easy to expand. However, the embodiment is not limited thereto, and the above encoding and decoding can also be implemented by other methods.

[0082] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, the coding matrix may include a first interval and a second interval, wherein the first interval may include a unit matrix of k rows and k columns, and the second interval may include a Vandermonde-like matrix of m rows and k columns; and encoding k data codewords based on the coding matrix may include: multiplying the k data codewords using the unit matrix of k rows and k columns to obtain k data codewords; and multiplying the k data codewords using the Vandermonde-like matrix of m rows and k columns to obtain m check codewords.

[0083] Thus, the processing method according to at least one embodiment of the present disclosure can form a variety of coding matrices, thereby improving the flexibility of the formed coding matrix. It is understood that the coding matrix can also additionally include other intervals, and 0 or 1 or other suitable values ​​can be set in other intervals without affecting the implementation of the above coding.

[0084] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, the decoding matrix may include a third interval and a fourth interval, wherein the third interval may include a Vandermonde-like matrix with m rows and k columns, and the fourth interval may include an identity matrix with m rows and m columns; and decoding the readback encoded data based on the decoding matrix to obtain syndrome data may include: using the decoding matrix to multiply k readback data code elements and m readback check code elements to obtain syndrome data.

[0085] Thus, the processing method according to at least one embodiment of the present disclosure can form a variety of decoding matrices, thereby improving the flexibility of the formed decoding matrix. It is understood that the decoding matrix can also additionally include other intervals, and 0 or 1 or other suitable values ​​can be set in other intervals without affecting the implementation of the above decoding.

[0086] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, obtaining the error-corrected codeword using the syndrome data may include: reading the syndrome data; in response to the syndrome data being all 0, outputting k readback data codewords as the error-corrected codewords, wherein the syndrome data being all 0 may indicate that the k readback data codewords and the m readback check codewords have no errors; in response to the syndrome data having one 1, outputting k readback data codewords as the error-corrected codewords, wherein the syndrome data having one 1 may indicate that the k readback data codewords have no errors and the m readback check codewords have no errors. The readback check codeword corresponding to the companion data whose companion data is 1 has an error; in response to the companion data having v 1s, the error codewords in the k readback data codewords and the m readback check codewords are corrected using the companion data to obtain the corrected codewords, wherein the companion data having v 1s can indicate that v1 readback data codewords corresponding to the companion data of 1 in the k readback data codewords have errors and v2 readback check codewords corresponding to the companion data of 1 in the m readback check codewords have errors, wherein v≥2, v1≤m, v2≤m, v1+v2=v.

[0087] In this way, the processing method according to at least one embodiment of the present disclosure can determine whether the readback data codeword and the readback check codeword are erroneous and the error positions based on the acquired syndrome data.

[0088] For example, according to the data processing method of at least one embodiment of the present disclosure, the Vandermonde-like matrix includes a Vandermonde matrix, a left-right flip of a Vandermonde matrix, an up-and-down flip of a Vandermonde matrix, or a transpose of a Vandermonde matrix.

[0089] For example, according to the data processing method of at least one embodiment of the present disclosure, the encoding and decoding operations can use the Vandermonde matrix. The exemplary Vandermonde matrix can have the following form:

[0090]

[0091] For example, according to the data processing method of at least one embodiment of the present disclosure, the number of rows and columns of the Vandermonde-like matrix can be adaptively adjusted according to the ECC word.

[0092] Corresponding to the data processing method according to at least one embodiment of the present disclosure, the present disclosure also provides a memory controller.

[0093] Figure 2 FIG. 2 shows a schematic diagram of a memory controller 200 according to at least one embodiment of the present disclosure. Figure 2As shown, the memory controller 200 includes a reading unit 210 and a decoding unit 220. The decoding unit may be a decoder or a part of a decoder. It is understood that the memory controller 200 may alternatively or additionally include other units, such as an encoding unit (or encoder) for performing encoding operations. For example, the reading unit 210 may be a part of the transceiver unit of the memory controller, and the decoding unit 220 may be a part of the codec unit of the memory controller.

[0094] The read unit 210 is configured to read four burst data from a single storage channel; organize the four burst data into a group of error correction codewords, wherein a group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of a codeword.

[0095] The decoding unit 220 is configured to perform a decoding operation based on a set of error correction codewords to obtain error-corrected codewords.

[0096] Thus, the data memory controller according to at least one embodiment of the present disclosure can realize simultaneous error correction of, for example, two or more code elements or symbols by reading four burst data from a single storage channel through one ECC operation. For example, without opening the lock synchronization, the problem of multiple code element half-chips having errors at the same time can be effectively solved.

[0097] Other exemplary aspects of the memory controller according to at least one embodiment of the present disclosure are described in detail below.

[0098] For example, in a data memory controller according to at least one embodiment of the present disclosure, a read unit is further configured to: combine burst data corresponding to the same pin of the same storage particle among four burst data read by a single storage channel into one of k read back data code elements or m read back check code elements to obtain k read back data code elements and m read back check code elements; and connect the k read back data code elements and the m read back check code elements to obtain a set of error correction code words.

[0099] For example, according to the data memory controller of at least one embodiment of the present disclosure, a single storage channel includes 8 data storage particles and 2 check storage particles, and the bit width of each storage particle in the 8 data storage particles and the 2 check storage particles is 4 bits.

[0100] For example, in a data memory controller according to at least one embodiment of the present disclosure, a reading unit is further configured to: perform the following operations on each of 8 data storage particles and 2 check storage particles to obtain data including 32 data symbols and 8 check symbols as a set of error correction codewords: organize the data corresponding to the first bit of 4 bits in four bursts of data into a first symbol; organize the data corresponding to the second bit of 4 bits in the four bursts of data into a second symbol; organize the data corresponding to the third bit of 4 bits in the four bursts of data into a third symbol; and organize the data corresponding to the fourth bit of 4 bits in the four bursts of data into a fourth symbol.

[0101] For example, in a data memory controller according to at least one embodiment of the present disclosure, a single storage channel is a single memory channel of DDR5.

[0102] The above is only combined with Figure 2 Part of the memory controller 200 according to at least one embodiment of the present disclosure is described, and the remaining part of the memory controller 200 may be combined with the present disclosure. Figure 1 Various aspects of the data processing method 100 described herein are referenced and combined according to the present disclosure Figure 1 The effects of various aspects of the data processing method 100 described can also be mapped to the combination of the present disclosure. Figure 2 The memory controller 200 is described and will not be elaborated here.

[0103] For example, the memory controller 200 according to at least one embodiment of the present disclosure may alternatively or additionally include an encoding unit to perform the above encoding.

[0104] Below through Figure 3 To describe an example application scenario in which a data processing method or a memory controller according to at least one embodiment of the present disclosure can be used. It can be understood that Figure 3 The application scenarios shown are only exemplary and do not exhaustively list and illustrate various aspects of the above data processing methods or memory controllers. Figure 3 Aspects and combinations of descriptions Figure 1 and Figure 2 The various aspects described may be referenced to each other without departing from the scope of the present disclosure.

[0105] In this example application scenario, using Ch0 of DDR5 as the above single storage channel, when multiple memory particles fail at any time, and each memory particle fails by 1-2 bits, the hardware structure of the method of the present invention can be used, without the involvement of software and without the need to rely on historical record information, and the hardware will be able to correct multiple memory particle errors at the same time. In this way, the reliability of the memory is greatly improved, and the risk of data loss and system downtime is reduced.

[0106] Figure 3 A structural diagram of simultaneously correcting errors of multiple memory cells according to at least one embodiment of the present disclosure is shown.

[0107] exist Figure 3 In the application scenario shown, taking a memory chip with a one-bit error as an example, one ECC operation can correct up to four memory chip errors at the same time. Using this method, the following technical effects can be achieved:

[0108] ●It can correct errors in 4 memory cells, each with 1 bit of data error; and the position of the error bit is arbitrary.

[0109] ● It can correct errors in 3 memory chips, where two memory chips have 1 bit of data error and the other memory chip has 2 bits of data error. The error memory chip can be arbitrary and the position of the error bit is also arbitrary;

[0110] ● It can correct errors in two memory chips. The two memory chips can each have two bits of data errors, or one memory chip can have one bit error, and the other memory chip can have three bits error. The error memory chip can be arbitrary, and the error bit position is also arbitrary;

[0111] ●It can correct 1 memory chip error, 4 bits error. The memory supports 4-bit error correction (x4chipkill). The memory chip that has an error can be any.

[0112] See below for detailed description Figure 3 One or more aspects of the application scenario shown.

[0113] See also Figure 3 , DDR5 Ch0 includes 8 x4 data memory chips ( Figure 3 8 memory chips shown as "x4" in the figure) and 2 x4 parity memory chips ( Figure 3 2 memory chips are shown as “ecc” in the figure).

[0114] Read or receive four bursts of data Burst0, Burst1, Burst2, and Burst3 from DDR5 Ch0. Among them, Burst0 includes data D0, D4, D8, D12, D16, D20, D24, D28 corresponding to 8 x4 data memory particles and data C0 and C4 corresponding to two x4 check memory particles; Burst1 includes data D1, D5, D9, D13, D17, D21, D25, D29 corresponding to 8 x4 data memory particles and data C1 and C5 corresponding to two x4 check memory particles; Burst2 includes data D2, D6, D10, D14, D18, D22, D26, D30 corresponding to 8 x4 data memory particles and data C2 and C6 corresponding to two x4 check memory particles; Burst3 includes data D3, D7, D11, D15, D19, D23, D27, D31 corresponding to 8 x4 data memory particles and data C3 and C7 corresponding to two x4 check memory particles.

[0115] Exemplarily, D0-D31 and C0-C7 of the four burst data may be generated by encoding the data corresponding to D0-D31. In the absence of an error, D0-D31 is consistent with the corresponding data, and in the event of an error, D0-D31 is inconsistent with the corresponding data.

[0116] exist Figure 3 In the example application scenario, taking the x4-bit memory particle as an example, multiple bit errors are corrected without turning on the lock synchronization function. When writing data, a piece of data is only written to the four bursts of data of one memory channel. As shown in the figure, DDR5 Ch0, a piece of data written corresponds to or is reflected in Burst0 / 1 / 2 / 3. The four bursts of data Burst0 / 1 / 2 / 3 read are 160 bits in total, forming a group of ECC words.

[0117] A group of ECC words is formed by organizing the data of the same pins (embodied as the same bits of the same storage particles) of the same storage particles corresponding to the memory particles (data memory particles and check memory particles) in four burst data into one symbol.

[0118] For example, Figure 3 The four 4×4 boxes in the middle respectively show four burst data of four x4-bit memory particles (i.e. Figure 3 Detailed diagram of the data structure of the 4×4 boxes (the upper 4 dotted boxes). Each row in the 4×4 box corresponds to one of the four burst data of the corresponding x4-bit memory particle, and each column in the 4×4 box corresponds to one of the 4 bits of the corresponding x4-bit memory particle.

[0119] Figure 3 The bottom portion shows four 4-bit symbols, where each symbol is composed of data corresponding to the same bit in four burst data of a corresponding x4-bit memory cell.

[0120] Therefore, for the memory chip of DDR5 Ch0, the exemplary ECC word composition structure is:

[0121] Symbol 1 is a symbol composed of the highest bit 3 data of D0 / D1 / D2 / D3 corresponding to the four data of Burst0 / 1 / 2 / 3 of the first x4 data memory particle;

[0122] Symbol 2 is a symbol composed of the bit 2 data of D0 / D1 / D2 / D3 corresponding to the four data of Burst0 / 1 / 2 / 3 of the first x4 data memory particle;

[0123] Symbol 3 is a symbol composed of the bit 1 data of D0 / D1 / D2 / D3 corresponding to the four data of Burst0 / 1 / 2 / 3 of the first x4 data memory particle;

[0124] Symbol 4 is a symbol composed of the bit0 data of D0 / D1 / D2 / D3 corresponding to the four data of Burst0 / 1 / 2 / 3 of the first x4 data memory particle;

[0125] …

[0126] The DDR5 data bit width is 40 bits (8 data memory particles + 2 check memory particles). Each bit of data position (i.e. bit position) corresponds to four data of Burst0 / 1 / 2 / 3. Each position has 4 bits of data, forming a symbol. In this way, 32 data symbols + 8 check symbols are formed.

[0127] After ECC is organized, it can be achieved by using, for example, the above-mentioned Vandermonde matrix-based algorithm, which can achieve a single ECC operation and correct four symbol errors at the same time. There is no need to replace the particle chip like DDDC, nor is there a need to turn on the lock synchronization. While improving the error correction capability and probability, it will not have a negative impact on the performance of DDR, and no software involvement is required.

[0128] In the above example application scenario, it is possible to correct errors in multiple memory chips at the same time, effectively solving the problem of multiple chips reporting UE errors, thereby improving the reliability and robustness of the memory and reducing the risk of data loss and downtime. Figure 3 ,exist Figure 3 The application scenario of exemplarily shows that four memory particles have errors, where Figure 3The data errors in the memory chips shown in the four dotted boxes at the top are located at Figure 3 The second bit, the third bit, the third bit and the third bit (i.e., the wrong bit is shown in dark gray) of the four bits in the corresponding data memory particles shown in the middle, and there are four error symbols in the 32 data symbols + 8 check symbols organized thereby. Further, by, for example, an algorithm based on the Vandermonde matrix, one ECC operation can be achieved, and four symbol errors can be corrected at the same time, thereby realizing error correction of four data memory particles. Of course, the embodiment is not limited thereto, and the error can also be located in the check memory particles, or both the data memory particles and the check memory particles, the error can also be located in other bits, or the error can also be located in a single memory particle, two memory particles, three memory particles, etc., thereby realizing error correction of a corresponding number of memory particles. The above-mentioned example application scenario is only a part or additional aspect of realizing the data processing method and memory controller according to at least one embodiment of the present disclosure, and other aspects of the above-mentioned example application scenario can refer to the data processing method and memory controller and their additional aspects according to at least one embodiment of the present disclosure.

[0129] Figure 4 FIG. 4 is a schematic diagram of a storage system 400 according to at least one embodiment of the present disclosure. Figure 4 As shown, the memory system 400 includes a memory controller 410 and a memory unit 420 .

[0130] The memory controller 410 may be Figure 2 The memory controller described in the embodiment of the present invention. The storage unit 420 may include a storage channel. In some embodiments, the storage unit 420 may be a memory itself, such as a DDR memory or a DDR memory. In other embodiments, the storage unit may be a storage array in a memory.

[0131] Figure 5 FIG. 5 is a schematic diagram of a memory subsystem 500 according to at least one embodiment of the present disclosure. The memory subsystem 500 here may be an exemplary example of the storage system 400 described above.

[0132] See also Figure 5 , the memory subsystem 500 may include a memory controller 510 and a memory unit 520. The memory controller 510 may be an exemplary instance of the memory controller described above, and the memory unit 520 may be an exemplary instance of the storage unit described above, for example, the memory unit may be DDR, such as DDR5 described above. The memory controller 510 is also commonly referred to as a master control chip.

[0133] The memory unit 520 may include a DDR column group 525. The DDR column group 525 may be an exemplary example of the DDR5 Ch0 described above. The DDR column group 525 may include a plurality of DRAM particles, such as DRAM particles 522, DRAM particles 524, and DRAM particles 526, etc. These DRAM particles may be an exemplary example of the data storage particles and the verification storage particles or the data memory particles and the verification memory particles described above. In addition, the DRAM particles may include encoders, decoders, etc., to perform corresponding encoding operations and ECC operations when reading and writing operations on the DRAM particles. The memory unit 520 may be a dual in-line memory unit (DIMM), a plurality of DRAM particles directly soldered on a circuit board (also referred to as DRAM particle chips), or other forms.

[0134] Continue to see Figure 5 , the memory controller 510 can interact with the memory unit 520 via the DDR channel. Figure 5 One DDR channel is used as an example, but the embodiment is not limited thereto, and the memory subsystem 500 may also include multiple DDR channels. In addition, the memory unit 520 may include multiple DDR rank groups, but at least one embodiment of the present disclosure is not limited thereto.

[0135] Figure 6 A schematic diagram of an electronic device 600 according to at least one embodiment of the present disclosure is shown.

[0136] like Figure 6 As shown, the electronic device 600 includes a processor 610 and a memory 620. The memory 620 includes one or more computer program modules 621. The one or more computer program modules 621 are stored in the memory 620 and are configured to be executed by the processor 610. The one or more computer program modules 621 include instructions for executing the data processing method according to at least one embodiment of the present disclosure. When the instructions are executed by the processor 610, the data processing method according to at least one embodiment of the present disclosure and one or more steps of additional aspects thereof can be executed. The memory 620 and the processor 610 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown). For example, the bus can be a peripheral component interconnect standard (PCI) bus or an extended industrial standard architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0137] Exemplarily, the processor 610 may be a central processing unit (CPU), a digital signal processor (DSP), or other forms of processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA), etc.; for example, the central processing unit (CPU) may be an X86 or ARM architecture, a RISC-V architecture, etc. The processor 610 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 600 to perform desired functions.

[0138] Exemplarily, the memory 620 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules 621 may be stored on the computer-readable storage medium, and the processor 610 may run one or more computer program modules 621 to implement various functions of the electronic device 600. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0139] For example, the electronic device 600 may also include input devices such as a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices such as a liquid crystal display, a speaker, a vibrator, etc.; storage devices such as a magnetic tape, a hard disk (HDD or SDD), etc.; and communication devices such as a network interface card such as a LAN card, a modem, etc. may also be included. The communication device may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive is connected to the I / O interface as needed. Removable storage media, such as a disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive as needed so that the computer program read therefrom is installed into the storage device as needed.

[0140] For example, the electronic device 600 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and technologies, including but not limited to a global system for mobile communications (GSM), an enhanced data GSM environment (EDGE), wideband code division multiple access (W-CDMA), code division multiple access (CDMA), time division multiple access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), voice transmission over Internet protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or short message service (SMS), or any other suitable communication protocol.

[0141] The electronic device 600 may be, for example, a system on a chip (SOC) or a device including the SOC, for example, a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a home appliance, a communication base station, an industrial controller, a server, or any other device, or a combination of any data processing device and hardware, which is not limited by the embodiments of the present disclosure. The specific functions and technical effects of the electronic device 600 may refer to the description of the data processing method and its additional aspects according to at least one embodiment of the present disclosure, which will not be repeated here.

[0142] Figure 7 A schematic diagram of a non-transitory readable storage medium 700 according to at least one embodiment of the present disclosure is shown.

[0143] like Figure 7 As shown, a non-transitory readable storage medium 700 stores computer instructions 710, which, when executed by a processor, perform one or more steps of the data processing method and additional aspects thereof as described above.

[0144] Exemplarily, the non-transitory readable storage medium 700 can be any combination of one or more computer-readable storage media, for example, a computer-readable storage medium includes a program code for reading four bursts of data from a single storage channel, a program code for organizing the four bursts of data into a group of error correction codewords, and a program code for performing a decoding operation based on a group of error correction codewords to obtain error-corrected codewords.

[0145] Exemplarily, when the program code is read by a computer, the computer may execute the program code stored in the computer storage medium to perform, for example, one or more steps of the data processing method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0146] Exemplarily, the non-transitory readable storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), flash memory, and other non-transitory readable storage media or any combination thereof.

[0147] In the above detailed description, for the purpose of explanation rather than limitation, specific details are set forth in order to provide a thorough understanding of the various aspects and embodiments described in the present disclosure. In some cases, a detailed description of well-known devices, components, circuits and methods is omitted to avoid blurring the description of the embodiments disclosed herein with unnecessary details. All statements of the principles, aspects and embodiments disclosed herein, as well as specific examples thereof, are listed herein, and are intended to cover both their structural equivalents and functional equivalents. In addition, such equivalents are intended to include currently known equivalents and equivalents developed in the future, that is, any element developed to perform the same function, regardless of the structure. Therefore, for example, it is understood that the block diagram herein may represent a conceptual diagram of an illustrative circuit system or other functional unit embodying the principles of the described embodiments. Such functions and the functional blocks shown will be understood to be hardware-implemented and / or computer-implemented.

[0148] The various embodiments of the present disclosure are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0149] It should be noted that, in this article, relational terms such as first, second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "include", "comprises", or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements includes not only those elements, but also further includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. In the absence of further restrictions, the elements defined by the statement "includes..." do not exclude the presence of other identical elements in the process, method, article, or device including the elements.

[0150] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure; the scope of the present disclosure is determined by the claims.

Claims

1. A data processing method, comprising: Read four bursts of data from a single memory channel; Organizing the four burst data into a group of error correction codewords, wherein the group of error correction codewords includes k read-back data codewords and m read-back check codewords, k and m are natural numbers, a total bit width of the m read-back check codewords is eight times the bit width of one codeword, the read-back data codewords are data codewords read from the single storage channel, and the read-back check codewords are check codewords read from the single storage channel; and Performing a decoding operation based on the set of error correction codewords to obtain error-corrected codewords; The four burst data are organized into the group of error correction code words, including: Combining the burst data corresponding to the same pin of the same storage particle among the four burst data read by the single storage channel into one of the k read-back data code elements or the m read-back verification code elements to obtain the k read-back data code elements and the m read-back verification code elements; and The k read-back data symbols and the m read-back check symbols are concatenated to obtain the set of error correction codewords.

2. The method according to claim 1, wherein: The single storage channel includes 8 data storage particles and 2 verification storage particles, and the bit width of each storage particle in the 8 data storage particles and the 2 verification storage particles is 4 bits.

3. The method according to claim 2, wherein: Combining the same pin burst data corresponding to the same storage particle in the four burst data read by the single storage channel into a group of error correction code words, including: The following operation is performed on each of the eight data storage particles and the two check storage particles to obtain data including 32 data symbols and 8 check symbols as the set of error correction code words: Organizing data corresponding to a first bit of the 4 bits in the four burst data into a first symbol; Organizing data corresponding to a second bit of the 4 bits in the four burst data into a second symbol; Organizing data corresponding to a third bit of the 4 bits in the four burst data into a third symbol; and The data corresponding to the fourth bit of the 4 bits in the four burst data are organized into a fourth symbol.

4. The method according to claim 2, wherein: The single storage channel is a single memory channel of DDR5.

5. The method according to any one of claims 1 to 4, wherein: Encoding k data symbols written into the single storage channel comprises: Encoding the k data symbols based on a coding matrix; Performing a decoding operation based on the set of error correction codewords to obtain the error-corrected codewords includes: Decoding the set of error correction codewords based on a decoding matrix to obtain syndrome data; and Utilizing the syndrome data to obtain the error-corrected codeword, The encoding matrix is ​​a matrix of at least k+m rows and k columns and includes a Vandermonde-like matrix, the decoding matrix is ​​a matrix of at least m rows and k+m columns and includes the Vandermonde-like matrix, wherein the Vandermonde-like matrix is ​​a matrix associated with the Vandermonde matrix, wherein k≤p n -1, m≤p n , where n is the number of bits in each symbol and p is the capacity of a single bit.

6. The processing method according to claim 5, wherein: The encoding matrix includes a first interval and a second interval, wherein the first interval includes a unit matrix with k rows and k columns, and the second interval includes a Vandermonde-like matrix with m rows and k columns; and Encoding the k data symbols based on the encoding matrix includes: Multiplying the k data symbols by the k-row and k-column identity matrix to obtain the k data symbols; and The m read-back verification code symbols are obtained by multiplying the k data code symbols by the m-row and k-column Vandermonde-like matrix.

7. The processing method according to claim 5, wherein: The decoding matrix includes a third interval and a fourth interval, wherein the third interval includes a Vandermonde-like matrix with m rows and k columns, and the fourth interval includes an identity matrix with m rows and m columns; and The step of decoding the set of error correction codewords based on a decoding matrix to obtain syndrome data includes: The syndrome data is obtained by multiplying the k readback data symbols and the m readback check symbols using the decoding matrix.

8. The processing method according to claim 5, wherein: The step of obtaining the error-corrected codeword by using the syndrome data comprises: Reading the companion data; In response to the syndrome data being all 0, outputting the k read-back data symbols as the error-corrected symbols, wherein the syndrome data being all 0 indicates that the k read-back data symbols and the m read-back check symbols have no errors; In response to the syndrome data having a 1, outputting the k readback data symbols as the error-corrected symbols, wherein the syndrome data having a 1 indicates that the k readback data symbols have no error and a readback check symbol among the m readback check symbols corresponding to the 1 in the syndrome data has an error; In response to the fact that the syndrome data has v ones, the syndrome data is used to correct the error code elements in the k read back data code elements and the m read back check code elements to obtain the error-corrected code elements, wherein the syndrome data has v ones indicating that v1 read back data code elements corresponding to v1 ones in the syndrome data among the k read back data code elements are erroneous and v2 read back check code elements corresponding to v2 ones in the syndrome data among the m read back check code elements are erroneous, wherein v≥2, v1≤m, v2≤m, v1+v2=v, and v, v1 and v2 are natural numbers.

9. The processing method according to claim 5, wherein: The Vandermonde-like matrix includes a Vandermonde matrix, a left-right flip of a Vandermonde matrix, an up-down flip of a Vandermonde matrix, or a transpose of a Vandermonde matrix.

10. A memory controller comprising: The reading unit is configured as: Read four bursts of data from a single memory channel; Organizing the four burst data into a group of error correction codewords, wherein the group of error correction codewords includes k read-back data codewords and m read-back check codewords, k and m are natural numbers, the total bit width of the m read-back check codewords is eight times the bit width of one codeword, the read-back data codewords are data codewords read from the single storage channel, and the read-back check codewords are check codewords read from the single storage channel, and The decoding unit is configured as follows: Performing a decoding operation based on the set of error correction codewords to obtain error-corrected codewords; Wherein, the reading unit is further configured as: Combining the burst data corresponding to the same pin of the same storage particle among the four burst data read by the single storage channel into one of the k read-back data code elements or the m read-back verification code elements to obtain the k read-back data code elements and the m read-back verification code elements; and The k read-back data symbols and the m read-back check symbols are concatenated to obtain the set of error correction codewords.

11. The memory controller according to claim 10, wherein: The single storage channel includes 8 data storage particles and 2 verification storage particles, and the bit width of each storage particle in the 8 data storage particles and the 2 verification storage particles is 4 bits.

12. The memory controller according to claim 11, wherein: The reading unit is further configured to: The following operation is performed on each of the eight data storage particles and the two check storage particles to obtain data including 32 data symbols and 8 check symbols as the set of error correction code words: Organizing data corresponding to a first bit of the 4 bits in the four burst data into a first symbol; Organizing data corresponding to a second bit of the 4 bits in the four burst data into a second symbol; Organizing data corresponding to a third bit of the 4 bits in the four burst data into a third symbol; as well as The data corresponding to the fourth bit of the 4 bits in the four burst data are organized into a fourth symbol.

13. The memory controller according to claim 11, wherein: The single storage channel is a single memory channel of DDR5.

14. A storage system comprising: The memory controller according to any one of claims 10 to 13; as well as A storage unit includes the single storage channel.

15. An electronic device comprising: one or more processors; a memory including one or more computer program modules; The one or more computer program modules are stored in the memory and are configured to be executed by the one or more processors to implement the processing method according to any one of claims 1-9.

16. A non-transitory readable storage medium having computer executable instructions stored thereon, in, When the computer executable instructions are executed by a processor, the processing method according to any one of claims 1 to 9 is implemented.

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