A method and system for on-orbit reconfiguration and configuration loading of a DSP

Abstract

A DSP on-orbit reconfiguration and configuration loading method and system, the steps are as follows: the control circuit receives the data to be reconfigured and carries out analysis processing; the data to be reconfigured after analysis processing is written into the program data storage area of the continuous address of Flash in sequence according to the programming timing requirement of FLASH; the control circuit carries out logical reset to the reconfigured loading DSP; after reset is completed, the reconfigured loading DSP device sends the continuous data address to the on-orbit reconfiguration and loading control circuit in sequence; the on-orbit reconfiguration and loading control circuit carries out address decoding to the received data address, and maps out the program data storage area address in the corresponding Flash, reads the program data from the corresponding program data storage area of the Flash in sequence, and places the continuous address data on the configuration interface according to the configuration interface timing requirement of the reconfigured loading DSP, until all the continuous address data required by the reconfigured loading DSP is read completely, and the loading is successful.

Description

Technical Field

[0001] This invention relates to a method and system for on-orbit reconfiguration and configuration loading of a DSP, belonging to the field of space single-event protection for integrated circuits. Background Technology

[0002] A DSP (Digital Signal Processor) is a digital signal processing device that, upon power-up, loads program data to implement certain user functions. Due to its ability to implement various digital signal processing algorithms in real-time and quickly, it is widely used as a core digital processing device in onboard digital satellite systems. Previously, onboard DSPs were typically connected directly to external memory, storing the DSP's program data there. Upon power-up, the DSP would autonomously read the program data from the external memory sequentially through the EMIF configuration interface, load the configuration, and run its normal functions. However, as the clock frequencies and scales of DSPs used in onboard systems increase, the amount of program data they run also increases, leading to higher demands on the data read speed and storage capacity of external memory. Furthermore, on-orbit function reconfiguration has gradually become standard onboard systems, creating a pressing need for DSPs to also support on-orbit program reconfiguration. Therefore, it is necessary to use high-capacity, rewritable, non-volatile Nor Flash memory as the external program data storage device for DSPs. This ensures the large-capacity program data storage requirements of the DSP while also accommodating on-orbit function reconfiguration, significantly improving the satellite's on-orbit maintainability and flexibility.

[0003] Meanwhile, Nor FLASH devices are inherently susceptible to single-event upsets (SOME), which can cause errors in stored data bits and pose a risk of DSP program loading failure. Especially for numerous low-cost satellite payload applications, Nor FLASH not only has a capacity exceeding 2 Gbit, but also exhibits poor SOME resistance, significantly increasing the probability of on-orbit SOME. Therefore, it is necessary to implement SOME hardening designs for data storage in Nor FLASH to improve the on-orbit reliability of individual devices. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose an on-orbit reconfiguration and configuration loading method for DSP. For digital processing units with DSP devices as the core, it realizes a hardened design to resist single-event upset for continuous data storage verification in Nor FLASH, thereby further improving the on-orbit maintainability, flexibility and reliability of the payload unit.

[0005] The technical solution of this invention is: a DSP on-orbit reconfiguration and configuration loading method, comprising:

[0006] The control circuit receives the data to be reconstructed and performs parsing processing;

[0007] The parsed and processed data to be reconstructed is written sequentially into the program data storage area of ​​the Flash memory at consecutive addresses, according to the programming timing requirements of the Flash memory.

[0008] The control circuit performs a logic reset on the DSP to be reconfigured; after the reset is completed, the DSP to be reconfigured sends consecutive data addresses to the control circuit in sequence.

[0009] The control circuit decodes the received data address and maps it to the corresponding program data storage area address in Flash. It then reads the program data from the corresponding program data storage area in Flash in sequence. According to the timing requirements of the configuration interface of the DSP to be reconfigured and loaded, it places the continuous address data on the configuration interface until all the data required for the continuous addresses of the DSP to be reconfigured and loaded has been read and the loading is successful.

[0010] While writing the program data into the Flash memory at consecutive addresses, the program data in the Flash memory is also verified.

[0011] Verification of program data in Flash memory includes:

[0012] The control circuit uses the Hamming code EDAC (External Data Acquisition and Verification) algorithm to calculate the check value for the program data stored continuously in Flash. The EDAC check value corresponding to each piece of program data is written into Flash along with the program data. The control circuit reads out the program data and EDAC check value of the corresponding storage area in Flash in sequence, and compares the EDAC check value corresponding to the current program data with the check value read from Flash to obtain the verification result.

[0013] The program data in Flash is validated. If the validation result is correct, the subsequent process continues; if the validation result is incorrect, the process returns and the data to be reconstructed is re-executed.

[0014] The program data in Flash is verified. If the verification result is correct, the subsequent process continues. If the verification result is incorrect, and the EDAC verification value shows that only 1 bit error occurs in any consecutive 32 bits of program data, the error correction and write-back of that 1 bit error is performed, and the subsequent process continues.

[0015] All EDAC checksums are stored in Flash memory using a contiguous address storage method, and are stored after all program data.

[0016] The control circuit is implemented using ASIC or antifuse FPGA.

[0017] A DSP on-orbit reconfiguration and configuration loading system includes: control circuitry and FLASH memory;

[0018] The control circuit receives the data to be reconstructed and performs parsing processing;

[0019] The parsed and processed data to be reconstructed is written sequentially into the program data storage area of ​​the Flash memory at consecutive addresses, according to the programming timing requirements of the Flash memory.

[0020] The control circuit performs a logic reset on the DSP to be reconfigured; after the reset is completed, the DSP device to be reconfigured sends consecutive data addresses to the on-orbit reconfiguration control circuit in sequence.

[0021] The control circuit decodes the received data address and maps it to the corresponding program data storage area address in Flash. It then reads the program data from the corresponding program data storage area in Flash in sequence. According to the timing requirements of the configuration interface of the DSP to be reconfigured and loaded, it places the continuous address data on the configuration interface until all the data required for the continuous addresses of the DSP to be reconfigured and loaded has been read and the loading is successful.

[0022] While writing the program data into consecutive address ranges in the Flash memory, the program data in the Flash memory is verified. The process includes:

[0023] The control circuit uses a Hamming code EDAC (External Data Acquisition and Verification) algorithm to calculate the check value for the program data stored continuously in Flash. The EDAC check value corresponding to each piece of program data is written into Flash along with the program data. The on-orbit reconfiguration loading control circuit reads out the program data and EDAC check value of the corresponding storage area in Flash in sequence, and compares the EDAC check value corresponding to the current program data with the check value read from Flash to obtain the verification result.

[0024] If the verification result is correct, continue with the subsequent process; if the verification result is incorrect, and the EDAC verification value shows that only 1 bit error occurs in any consecutive 32 bits of program data, then the error correction and write-back of that 1 bit error will be performed before continuing with the subsequent process.

[0025] The advantages of this invention compared to the prior art are:

[0026] (1) This invention proposes a simplified system design for on-orbit reconfiguration and loading of a single-chip DSP for satellite digital processing. Based on a single high-reliability on-orbit reconfiguration and loading control circuit, it realizes on-orbit reconfiguration of multiple DSPs, data storage with anti-single-event upset hardening design, configuration loading function, etc., and realizes centralized management of multiple tasks on the satellite. The system is simplified, low-cost and highly reliable.

[0027] (2) The DSP on-orbit reconfiguration and configuration loading implementation method and design flow proposed in this invention are based on the currently common asynchronous serial port and standard on-orbit reconfiguration protocol used on satellites. This enables on-orbit reconfiguration of DSP program data and employs a DSP master mode loading method. Based on the EMIF configuration interface, program data is read sequentially from Flash to complete the configuration loading. The implementation method is simple, with standard interfaces and reconfiguration protocols, and a universal design flow, offering high on-orbit flexibility and strong practicality.

[0028] (3) The DSP continuous data storage verification design method proposed in this invention is compatible with the loading function design and the single-event upset (SED) hardening design of stored data. On the one hand, it realizes the correctness verification of program data storage in FLASH and the accurate detection of erroneous data; on the other hand, it facilitates the DSP to read the continuity of changing addresses and program data in Flash when loading based on the EMIF interface in main mode, thereby improving the data reading rate and meeting the high-speed loading requirements of DSP.

[0029] (4) The present invention is based on the on-orbit reconfiguration loading control circuit to realize the on-orbit autonomous maintenance function of data stored in Flash. It does not require manual intervention from the ground and on the satellite. It can autonomously and seamlessly realize the autonomous error repair of data stored in on-orbit Flash, effectively solve the space single-event flip problem of Nor Flash, and further improve the reliability of data storage in on-orbit Flash. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the system composition of the present invention; Detailed Implementation

[0031] This invention relates to a DSP on-orbit reconfiguration and configuration loading method, comprising:

[0032] The control circuit receives the data to be reconstructed and performs parsing processing;

[0033] The parsed and processed data to be reconstructed is written sequentially into the program data storage area of ​​the Flash memory at consecutive addresses, according to the programming timing requirements of the Flash memory.

[0034] The control circuit performs a logic reset on the DSP to be reconfigured; after the reset is completed, the DSP to be reconfigured sends consecutive data addresses to the control circuit in sequence.

[0035] The control circuit decodes the received data address and maps it to the corresponding program data storage area address in Flash. It then reads the program data from the corresponding program data storage area in Flash in sequence. According to the timing requirements of the configuration interface of the DSP to be reconfigured and loaded, it places the continuous address data on the configuration interface until all the data required for the continuous addresses of the DSP to be reconfigured and loaded has been read and the loading is successful.

[0036] While writing the program data into the Flash memory at consecutive addresses, the program data in the Flash memory is also verified.

[0037] Verification of program data in Flash memory includes:

[0038] The control circuit uses the Hamming code EDAC (External Data Acquisition and Verification) algorithm to calculate the check value for the program data stored continuously in Flash. The EDAC check value corresponding to each piece of program data is written into Flash along with the program data. The control circuit reads out the program data and EDAC check value of the corresponding storage area in Flash in sequence, and compares the EDAC check value corresponding to the current program data with the check value read from Flash to obtain the verification result.

[0039] The program data in Flash is validated. If the validation result is correct, the subsequent process continues; if the validation result is incorrect, the process returns and the data to be reconstructed is re-executed.

[0040] The program data in Flash is verified. If the verification result is correct, the subsequent process continues. If the verification result is incorrect, and the EDAC verification value shows that only 1 bit error occurs in any consecutive 32 bits of program data, the error correction and write-back of that 1 bit error is performed, and the subsequent process continues.

[0041] All EDAC checksums are stored in Flash memory using a contiguous address storage method, and are stored after all program data.

[0042] The control circuit is implemented using ASIC or antifuse FPGA.

[0043] This invention also relates to a DSP on-orbit reconfiguration and configuration loading system, comprising: a control circuit and a FLASH;

[0044] The control circuit receives the data to be reconstructed and performs parsing processing;

[0045] The parsed and processed data to be reconstructed is written sequentially into the program data storage area of ​​the Flash memory at consecutive addresses, according to the programming timing requirements of the Flash memory.

[0046] The control circuit performs a logic reset on the DSP to be reconfigured; after the reset is completed, the DSP device to be reconfigured sends consecutive data addresses to the on-orbit reconfiguration control circuit in sequence.

[0047] The on-orbit reconfiguration loading control circuit decodes the received data address and maps it to the corresponding program data storage area address in Flash. It then reads the program data from the corresponding program data storage area in Flash in sequence, and places the continuous address data on the configuration interface according to the timing requirements of the configuration interface of the DSP to be reconfigured, until all the data required for all continuous addresses of the DSP to be reconfigured has been read, and the loading is successful.

[0048] While writing the program data into consecutive address ranges in the Flash memory, the program data in the Flash memory is verified. The process includes:

[0049] The control circuit uses the Hamming code EDAC (External Data Acquisition and Verification) algorithm to calculate the check value for the program data stored continuously in Flash. The EDAC check value corresponding to each piece of program data is written into Flash along with the program data. The control circuit reads out the program data and EDAC check value of the corresponding storage area in Flash in sequence, and compares the EDAC check value corresponding to the current program data with the check value read from Flash to obtain the verification result.

[0050] If the verification result is correct, continue with the subsequent process; if the verification result is incorrect, and the EDAC verification value shows that only 1 bit error occurs in any consecutive 32 bits of program data, then the error correction and write-back of that 1 bit error will be performed before continuing with the subsequent process.

[0051] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention based on the above-disclosed technical content without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for on-orbit reconfiguration and configuration loading of a DSP, characterized in that, include: Receive the data to be reconstructed and parse it. The parsed and processed data to be reconstructed is written sequentially into the program data storage area of ​​the Flash memory at consecutive addresses, according to the programming timing requirements of the Flash memory. Perform a logic reset on the DSP to be reloaded; After the reset is complete, the DSP device to be reconfigured sends consecutive data addresses to the receiving end in sequence; The receiving end decodes the received data address and maps it to the corresponding program data storage area address in Flash. It then reads the program data from the corresponding program data storage area in Flash in sequence. According to the timing requirements of the configuration interface of the DSP to be reconstructed and loaded, it places the continuous address data on the configuration interface until all the data required for the continuous addresses of the DSP to be reconstructed and loaded have been read and the loading is successful. While writing the program data into the consecutive address areas of the Flash memory, the program data in the Flash memory is verified. Verification of program data in Flash memory includes: The Hamming code EDAC (External Delimited Acquisition and Verification) algorithm is used to calculate the check value for the program data stored continuously in Flash. The EDAC check value corresponding to each piece of program data is written into Flash along with the program data. The program data and EDAC check value of the corresponding storage area in Flash are read out in sequence, and the EDAC check value corresponding to the current program data is compared with the check value read from Flash to obtain the verification result. The program data in Flash is verified. If the verification result is correct, the subsequent process continues. If the verification result is incorrect, and the EDAC verification value shows that only 1 bit error occurs in any consecutive 32 bits of program data, the error correction and write-back of that 1 bit error is performed, and the subsequent process continues. All EDAC checksums are stored in Flash memory using a contiguous address storage method, and are stored after all program data.

2. A DSP on-orbit reconfiguration and configuration loading system, characterized in that, include: Control circuit and FLASH; The control circuit receives the data to be reconstructed and performs parsing processing; The parsed and processed data to be reconstructed is written sequentially into the program data storage area of ​​the Flash memory at consecutive addresses, according to the programming timing requirements of the Flash memory. The control circuit performs a logic reset on the DSP to be reconfigured; after the reset is completed, the DSP to be reconfigured sends consecutive data addresses to the control circuit in sequence. The control circuit decodes the received data address and maps it to the corresponding program data storage area address in Flash. It reads the program data from the corresponding program data storage area in Flash in sequence, and then places the continuous address data on the configuration interface according to the timing requirements of the configuration interface of the DSP to be reconfigured and loaded, until all the data required for all continuous addresses of the DSP to be reconfigured and loaded has been read and the loading is successful. While writing the program data into consecutive address ranges in the Flash memory, the program data in the Flash memory is verified. The process includes: The control circuit uses the Hamming code EDAC (Error Correction-Detection-Verification) algorithm to calculate the verification value for the program data continuously stored in Flash. The EDAC verification value corresponding to each piece of program data is written into Flash along with the program data. The control circuit reads out the program data and EDAC verification value of the corresponding storage area in Flash in sequence, and compares the EDAC verification value corresponding to the current program data with the verification value read from Flash to obtain the verification result. If the verification result is correct, continue with the subsequent process; if the verification result is incorrect, and the EDAC verification value shows that only 1 bit error occurs in any consecutive 32 bits of program data, then the error correction and write-back of that 1 bit error will be performed before continuing with the subsequent process. All EDAC checksums are stored in Flash memory using a contiguous address storage method, and are stored after all program data.

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