Goa circuit and display panel

Abstract

The application discloses a GOA circuit and a display panel. The GOA circuit comprises a pull-up control unit, a pull-up unit, a first pull-down unit, a first pull-down maintenance unit, a second pull-down unit, a second pull-down maintenance unit, an inverting unit, an anti-leakage unit and a leakage blocking unit. The leakage blocking unit is connected with the first pull-down unit and / or the second pull-down unit, and is connected with a pull-up control signal and a high potential signal. When the pull-up control signal is high, the leakage blocking unit is opened, the first pull-down unit and / or the second pull-down unit is charged with the high potential, so as to block the leakage of the first node through the first pull-down unit and / or the second pull-down unit. According to the application, the leakage blocking unit can improve the leakage of the first node due to the negative bias of the threshold voltage of the TFT of the second pull-down unit in the running process of the GOA circuit, effectively blocks the leakage path of the first node and the second pull-down unit, and ensures the normal operation of the subsequent anti-leakage unit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a GOA circuit and a display panel. Background Technology

[0002] GOA (gate driver on array) circuits can fabricate gate scanning drive circuits on thin-film transistor (TFT) array substrates to achieve line-by-line scanning driving, offering advantages such as reduced production costs and enabling narrow bezel designs for panels. GOA circuits boast advantages such as low cost, narrow bezels, and high product yield.

[0003] However, the GOA circuit has high requirements for the stability of the TFT, and during operation, leakage current is easily caused by the deviation of the TFT threshold voltage, which in turn affects the expected performance of the display panel. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a GOA circuit and a display panel that can prevent leakage of current through the pull-down unit of the GOA circuit from affecting the performance of the display panel.

[0005] To achieve the above objectives, the present invention first provides a GOA circuit, comprising:

[0006] The pull-up control unit is connected to the first node and receives a pull-up control signal to pull up the potential of the first node.

[0007] The pull-up unit is connected to the first node and connected to a clock signal to pull up the potentials of the first output signal, the second output signal, and the cascade scan signal.

[0008] The first pull-down unit is connected to the first node, the second node, and the third node, and is connected to the first low-potential signal to pull down the potential of the first node;

[0009] The first pull-down sustaining unit is connected to the first node and the second node, and is connected to the first low-potential signal, the second low-potential signal, the first output signal, the second output signal and the cascade scan signal, and is used to maintain the low potential of the first output signal, the second output signal and the cascade scan signal.

[0010] The second pull-down unit is connected to the first node and the third node, and is connected to the pull-down control signal and the first low potential signal, and is used to pull down the potential of the first node;

[0011] The second pull-down sustaining unit is connected to the second pull-down unit and is connected to the first low-potential signal and the second low-potential signal to maintain the low potential of the first output signal, the second output signal and the cascade scan signal.

[0012] The inverting unit is connected to the first node and the second node, and is connected to the first low-potential signal, the pull-up control signal, the low-frequency clock signal and the third low-potential signal, so as to keep the potentials of the first node and the second node opposite.

[0013] The leakage protection unit is connected to the first node and the third node, and is connected to a high-potential signal to prevent leakage at the first node.

[0014] The leakage resistance interruption unit is connected to the first pull-down unit and / or the second pull-down unit, and is connected to the pull-up control signal and the high potential signal. When the pull-up control signal is high potential, the leakage resistance interruption unit is turned on, and the first pull-down unit and / or the second pull-down unit are charged with high potential to block the first node from leaking current through the first pull-down unit and / or the second pull-down unit.

[0015] Optionally, the leakage resistance interruption unit includes a first transistor; the gate of the first transistor is connected to a pull-up control signal, the first electrode is connected to a high-potential signal, and the second electrode is connected to the first pull-down unit and / or the second pull-down unit at the third node.

[0016] Optionally, the inverting unit includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the gate and first electrode of the second transistor, and the gate of the third transistor are all connected to a low-frequency clock signal; the second electrode of the second transistor is connected to the first electrode of the third transistor, and the second electrode of the third transistor is connected to the first electrode of the fourth transistor; the gate of the fourth transistor is connected to the first node, and the second electrode is connected to a third low-potential signal; the gate of the fifth transistor is connected to the second electrode of the third transistor, the first electrode is connected to a low-frequency clock signal, and the second electrode is connected to the second node; the gate of the sixth transistor is connected to the first node, the first electrode is connected to a first low-potential signal, and the second electrode is connected to the second node; the gate of the seventh transistor is connected to the first node of the next stage, the first electrode is connected to a third low-potential signal, and the second electrode is connected to the second electrode of the third transistor; the gate of the eighth transistor is connected to a pull-up control signal, the first electrode is connected to a first low-potential signal, and the second electrode is connected to the second node.

[0017] Optionally, the pull-up control unit includes an eleventh transistor and a twelfth transistor; the gate and first electrode of the eleventh transistor and the gate of the twelfth transistor are both connected to the pull-up control signal, the second electrode of the eleventh transistor is connected to the first electrode of the twelfth transistor, and the second electrode of the twelfth transistor is connected to the first node.

[0018] Optionally, the pull-up unit includes a 21st transistor, a 22nd transistor, a 23rd transistor, a first storage capacitor, a second storage capacitor, and a third storage capacitor. The clock signal includes a first clock signal, a second clock signal, and a third clock signal. The gate of the 21st transistor is connected to the first node, the first electrode is connected to the first clock signal, and the second electrode is connected to the first output signal. The gate of the 22nd transistor is connected to the first node, the first electrode is connected to the second clock signal, and the second electrode is connected to the stage scan signal. The gate of the 23rd transistor is connected to the first node, the first electrode is connected to the third clock signal, and the second electrode is connected to the second output signal. One end of the first storage capacitor is connected to the first node, and the other end is connected to the second electrode of the 21st transistor. One end of the second storage capacitor is connected to the first node, and the other end is connected to the second electrode of the 22nd transistor. One end of the third storage capacitor is connected to the first node, and the other end is connected to the second electrode of the 23rd transistor.

[0019] Optionally, the first pull-down sustaining unit includes a thirty-first transistor, a thirty-second transistor, and a thirty-third transistor; the gate of the thirty-first transistor is connected to the second node, the first electrode is connected to a first low-potential signal, and the second electrode is connected to a first output signal; the gate of the thirty-second transistor is connected to the second node, the first electrode is connected to a second low-potential signal, and the second electrode is connected to a stage scan signal; the gate of the thirty-third transistor is connected to the second node, the first electrode is connected to a second low-potential signal, and the second electrode is connected to a second output signal.

[0020] Optionally, the first pull-down unit includes a forty-first transistor and a forty-second transistor; the gate of the forty-first transistor and the gate of the forty-second transistor are simultaneously connected to the second node, the first electrode of the forty-second transistor is connected to a first low-potential signal, the first electrode of the forty-first transistor and the second electrode of the forty-second transistor are connected to the third node, and the second electrode of the forty-first transistor is connected to the first node.

[0021] Optionally, the second pull-down sustaining unit includes a 51st transistor, a 52nd transistor, and a 53rd transistor; the gate of the 51st transistor is connected to the second pull-down unit, the first electrode is connected to a first low-potential signal, and the second electrode is connected to a first output signal; the gate of the 52nd transistor is connected to the second pull-down unit, the first electrode is connected to a second low-potential signal, and the second electrode is connected to a stage scan signal; the gate of the 53rd transistor is connected to the second pull-down unit, the first electrode is connected to a second low-potential signal, and the second electrode is connected to a second output signal.

[0022] Optionally, the second pull-down unit includes a forty-third transistor, a forty-fourth transistor, a sixty-first transistor, and a sixty-second transistor; the gates of the forty-third transistor and the forty-fourth transistor are both connected to a pull-down control signal; the first electrode of the forty-fourth transistor is connected to a first low-potential signal, its second electrode is connected to the first electrode of the forty-third transistor at a third node, and the second electrode of the forty-third transistor is connected to the first node; the gates of the sixty-first transistor, the sixty-second transistor, the fifty-first transistor, the fifty-second transistor, and the fifty-third transistor are all connected together; the first electrode of the sixty-second transistor is connected to the first low-potential signal, its second electrode is connected to the first electrode of the sixty-first transistor at a third node, and the second electrode of the sixty-first transistor is connected to the first node.

[0023] The present invention also provides a display panel, including an array substrate and the above-mentioned GOA circuit, wherein the GOA circuit is connected to the array substrate.

[0024] Compared with the prior art, the beneficial effects of the present invention include: The GOA circuit of the present invention includes a pull-up control unit, a pull-up unit, a first pull-down unit, a first pull-down sustaining unit, a second pull-down unit, a second pull-down sustaining unit, an inverting unit, a leakage protection unit, and a leakage resistance interruption unit. The leakage resistance interruption unit is connected to the first pull-down unit and / or the second pull-down unit, and is connected to a pull-up control signal and a high-potential signal. When the pull-up control signal is high, the leakage resistance interruption unit is turned on, and the first pull-down unit and / or the second pull-down unit are charged to a high potential to block the first node from leaking current through the first pull-down unit and / or the second pull-down unit. The present invention, through the leakage resistance interruption unit, can improve the situation where the first node leaks current during the operation of the GOA circuit due to the negative bias of the TFT threshold voltage of the second pull-down unit, effectively blocking the leakage path between the first node and the second pull-down unit, ensuring that the first node is charged normally to the required high potential, and ensuring the normal operation of the subsequent leakage protection unit. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the GOA circuit structure in an embodiment of the present invention. Figure 1 ;

[0027] Figure 2 This is a schematic diagram of the GOA circuit structure in an embodiment of the present invention. Figure 2 ;

[0028] Figure 3 This is a schematic diagram of the GOA circuit structure in an embodiment of the present invention. Figure 3 . Detailed Implementation

[0029] The following descriptions of the embodiments are with reference to the accompanying illustrations, illustrating specific embodiments in which the invention can be implemented. In the description of the invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the module or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0031] This invention provides a GOA circuit, such as... Figures 1 to 3 As shown, it includes a pull-up control unit 100, a pull-up unit 200, a first pull-down unit 300, a first pull-down sustaining unit 400, a second pull-down sustaining unit 500, a second pull-down unit 600, an inverting unit 700, a leakage protection unit 800, and a leakage resistance interruption unit 900, wherein:

[0032] The pull-up control unit 100 is connected to the first node Q[n] and is connected to the pull-up control signal Cout-PU, which is used to pull up the potential of the first node Q[n].

[0033] Pull-up unit 200 is connected to the first node Q[n] and connected to a clock signal to pull up the potentials of the first output signal RD[n], the second output signal WR[n], and the cascade scan signal Cout[n].

[0034] The first pull-down unit 300 is connected to the first node Q[n], the second node QB[n] and the third node N[n], and is connected to the first low potential signal VGL1 to pull down the potential of the first node Q[n].

[0035] The first pull-down sustaining unit 400 is connected to the first node Q[n] and the second node QB[n], and is connected to the first low-potential signal VGL1, the second low-potential signal VGL2, the first output signal RD[n], the second output signal WR[n] and the cascade scan signal Cout[n], in order to maintain the low potential of the first output signal RD[n], the second output signal WR[n] and the cascade scan signal Cout[n].

[0036] The second pull-down unit 600 is connected to the first node Q[n] and the third node N[n], and is connected to the pull-down control signal Cout-PD and the first low potential signal VGL1, which are used to pull down the potential of the first node Q[n].

[0037] The second pull-down sustaining unit 500 is connected to the second pull-down unit 600 and is connected to the first low-potential signal VGL1 and the second low-potential signal VGL2 to maintain the low potential of the first output signal RD[n], the second output signal WR[n] and the cascade scan signal Cout[n].

[0038] The inverting unit 700 is connected to the first node Q[n] and the second node QB[n], and is connected to the first low-potential signal VGL1, the pull-up control signal Cout-PU, the low-frequency clock signal and the third low-potential signal VGL3, so as to keep the potentials of the first node Q[n] and the second node QB[n] opposite;

[0039] The leakage protection unit 800 is connected to the first node Q[n] and the third node N[n], and is connected to a high-potential signal VGH to prevent leakage at the first node Q[n].

[0040] The leakage resistance interruption unit 900 is connected to the first pull-down unit 300 and / or the second pull-down unit 600, and is connected to the pull-up control signal Cout-PU and the high potential signal VGH. When the pull-up control signal Cout-PU is high, the leakage resistance interruption unit 900 is turned on, and the first pull-down unit 300 and / or the second pull-down unit 600 are charged with a high potential to block the first node Q[n] from leaking through the first pull-down unit 300 and / or the second pull-down unit 600.

[0041] In the GOA circuit structure described above in this embodiment, the leakage resistance interruption unit 900 can improve the situation where the first node Q[n] leaks current due to the negative bias of the TFT threshold voltage of the first pull-down unit 300 and / or the second pull-down unit 600 during the operation of the GOA circuit. It effectively blocks the leakage path between the first node Q[n] and the first pull-down unit 300 and / or the second pull-down unit 600, ensuring that the first node Q[n] is charged normally to the required high potential, and the normal operation of the subsequent leakage protection unit 800.

[0042] In this embodiment, the first low-potential signal VGL1, the second low-potential signal VGL2, and the third low-potential signal VGL3 are signals higher than the reference potential, for example, they can be negative potential signals. The high-potential signal VGH can also be a signal higher than the reference potential, for example, it can be a positive potential signal.

[0043] In one embodiment, the drain resistance interruption unit 900 includes a first transistor T1; the gate of the first transistor T1 is connected to a pull-up control signal Cout-PU, the first electrode is connected to a high-potential signal VGH, and the second electrode is connected to a second pull-down unit 600 at a third node N[n]. Specifically, the drain of the first transistor T1 is connected to a high-potential signal VGH, and the source is connected to the second pull-down unit 600 at the third node N[n].

[0044] In one embodiment, the inverting unit 700 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7; the gate and first electrode of the second transistor T2, and the gate of the third transistor T3 are all connected to a low-frequency clock signal; the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3, and the second electrode of the third transistor T3 is connected to the first electrode of the fourth transistor T4; the gate of the fourth transistor T4 is connected to a first node Q[n], and its second electrode is connected to a third low-potential signal VGL3; the gate of the fifth transistor T5 is connected to the second electrode of the third transistor T6. Electrode connections: the first electrode is connected to a low-frequency clock signal, and the second electrode is connected to the second node QB[n]; the gate of the sixth transistor T6 is connected to the first node Q[n], the first electrode is connected to the first low-potential signal VGL1, and the second electrode is connected to the second node QB[n]; the gate of the seventh transistor T7 is connected to the first node Q[n+1] of the next stage, the first electrode is connected to the third low-potential signal VGL3, and the second electrode is connected to the second electrode of the third transistor T3; the gate of the eighth transistor T8 is connected to the pull-up control signal Cout-PU, the first electrode is connected to the first low-potential signal VGL1, and the second electrode is connected to the second node QB[n].

[0045] With the above structure, when the pull-up control signal Cout-PU is high, the first node Q[n] is high, and under the action of the inverting unit 700, the second node QB[n] is low, and the first pull-down sustaining unit 400 is turned off.

[0046] In one embodiment, the pull-up control unit 100 includes an eleventh transistor T11 and a twelfth transistor T12; the gate and first electrode of the eleventh transistor T11 and the gate of the twelfth transistor T12 are all connected to the pull-up control signal Cout-PU; the second electrode of the eleventh transistor T11 is connected to the first electrode of the twelfth transistor T12; and the second electrode of the twelfth transistor T12 is connected to the first node Q[n].

[0047] When the pull-up control signal Cout-PU is high, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the first node Q[n] is charged to a high potential.

[0048] In one embodiment, the pull-up unit 200 includes a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a first storage capacitor C1, a second storage capacitor C2, and a third storage capacitor C3. The clock signals include a first clock signal CKa, a second clock signal CKb, and a third clock signal CKc. The gate of the twenty-first transistor T21 is connected to the first node Q[n], the first electrode is connected to the first clock signal CKa, and the second electrode is connected to the first output signal RD[n]. The gate of the twenty-second transistor T22 is connected to the first node Q[n], and the first electrode is connected to the second clock signal RD[n]. b. The second electrode is connected to the stage scan signal Cout[n]; the gate of the twenty-third transistor T23 is connected to the first node Q[n], the first electrode is connected to the third clock signal CKc, and the second electrode is connected to the second output signal WR[n]; one end of the first storage capacitor C1 is connected to the first node Q[n], and the other end is connected to the second electrode of the twenty-first transistor T21; one end of the second storage capacitor C2 is connected to the first node Q[n], and the other end is connected to the second electrode of the twenty-second transistor T22; one end of the third storage capacitor C3 is connected to the first node Q[n], and the other end is connected to the second electrode of the twenty-third transistor T23.

[0049] When the first node Q[n] is charged to a high potential, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23 are turned on. The first clock signal CKa, the second clock signal CKb, and the third clock signal CKc are input from the first electrodes of the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23, respectively, and the first output signal RD[n], the stage scan signal Cout[n], and the second output signal WR[n] are output from the second electrodes of the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23, respectively.

[0050] In one embodiment, the first pull-down sustaining unit 400 includes a thirty-first transistor T31, a thirty-second transistor T32, and a thirty-third transistor T33; the gate of the thirty-first transistor T31 is connected to the second node QB[n], the first electrode is connected to the first low-potential signal VGL1, and the second electrode is connected to the first output signal RD[n]; the gate of the thirty-second transistor T32 is connected to the second node QB[n], the first electrode is connected to the second low-potential signal VGL2, and the second electrode is connected to the stage scan signal Cout[n]; the gate of the thirty-third transistor T33 is connected to the second node QB[n], the first electrode is connected to the second low-potential signal VGL2, and the second electrode is connected to the second output signal WR[n].

[0051] With the above structure, after the first pull-down unit 300 pulls down the potentials of the first output signal RD[n], the stage transmission scan signal Cout[n], and the second output signal WR[n], the first pull-down holding unit 400 can maintain the low potentials of the first output signal RD[n], the stage transmission scan signal Cout[n], and the second output signal WR[n].

[0052] In one embodiment, the first pull-down unit 300 includes a forty-first transistor T41 and a forty-second transistor T42; the gates of the forty-first transistor T41 and the forty-second transistor T42 are simultaneously connected to the second node QB[n], the first electrode of the forty-second transistor T42 is connected to the first low-potential signal VGL1, the first electrode of the forty-first transistor T41 and the second electrode of the forty-second transistor T42 are connected to the third node N[n], and the second electrode of the forty-first transistor T41 is connected to the first node Q[n].

[0053] With the above structure, the first electrode of the forty-second transistor T42 is connected to the first low-potential signal VGL1, and the potential of the first node Q[n] is pulled down, thereby pulling down the potential of the first output signal RD[n], the stage scan signal Cout[n], and the second output signal WR[n].

[0054] In one embodiment, such as Figure 2As shown, the second electrode of the leakage resistance interruption unit 900 is connected to the first electrode of the forty-first transistor T41 and the second electrode of the forty-second transistor T42 at the third node N[n]. When the pull-up control unit 100 is connected to a high-potential pull-up control signal Cout-PU, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the first node Q[n] is charged to a high potential. If the threshold voltage of the forty-first transistor T41 and the forty-second transistor T42 is negatively biased, the first node Q[n] will leak before the leakage protection unit 800 is turned on, causing the leakage protection unit 800 to fail. In order to ensure that the leakage protection unit 800 outputs a high potential normally, this embodiment uses the leakage resistance interruption unit 900 to pass a high-potential pull-up control signal Cout-PU, blocking the leakage path of the first node Q[n] through the forty-first transistor T41 and the forty-second transistor T42 during the charging process.

[0055] In one embodiment, the second pull-down sustaining unit 500 includes a fifty-first transistor T51, a fifty-second transistor T52, and a fifty-third transistor T53; the gate of the fifty-first transistor T51 is connected to the second pull-down unit 600, the first electrode is connected to a first low-potential signal VGL1, and the second electrode is connected to a first output signal RD[n]; the gate of the fifty-second transistor T52 is connected to the second pull-down unit 600, the first electrode is connected to a second low-potential signal VGL2, and the second electrode is connected to a stage scan signal Cout[n]; the gate of the fifty-third transistor T53 is connected to the second pull-down unit 600, the first electrode is connected to the second low-potential signal VGL2, and the second electrode is connected to a second output signal WR[n].

[0056] With the above structure, after the second pull-down unit 600 pulls down the potentials of the first output signal RD[n], the stage transmission scan signal Cout[n], and the second output signal WR[n], the second pull-down holding unit 500 can maintain the low potentials of the first output signal RD[n], the stage transmission scan signal Cout[n], and the second output signal WR[n].

[0057] In one embodiment, the second pull-down unit 600 includes a forty-third transistor T43, a forty-fourth transistor T44, a sixty-first transistor T61, and a sixty-second transistor T62; the gates of the forty-third transistor T43 and the forty-fourth transistor T44 are both connected to the pull-down control signal Cout-PD; the first electrode of the forty-fourth transistor T44 is connected to the first low-potential signal VGL1, and the second electrode is connected to the first electrode of the forty-third transistor T43 and the leakage resistance disconnection unit 900 at the third node N[n], and the second electrode of the forty-third transistor T43 is connected to the first node Q[n]; the gates of the sixty-first transistor T61, the sixty-second transistor T62, the fifty-first transistor T51, the fifty-second transistor T52, and the fifty-third transistor T53 are all connected; the first electrode of the sixty-second transistor T62 is connected to the first low-potential signal VGL1, and the second electrode is connected to the first electrode of the sixty-first transistor T61 at the third node N[n], and the second electrode of the sixty-first transistor T61 is connected to the first node Q[n].

[0058] With the above structure, when the pull-down control signal Cout-PD is low, the potential of the first node Q[n] is pulled low, thereby pulling down the potentials of the first output signal RD[n], the stage scan signal Cout[n], and the second output signal WR[n].

[0059] In one embodiment, such as Figure 1 As shown, the second electrode of the leakage resistance interruption unit 900 is connected to the first electrode of the forty-third transistor T43 and the second electrode of the forty-fourth transistor T44 at the third node N[n]. When the pull-up control unit 100 is connected to a high-potential pull-up control signal Cout-PU, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the first node Q[n] is charged to a high potential. If the threshold voltage of the forty-third transistor T43 and the forty-fourth transistor T44 is negatively biased, the first node Q[n] will leak before the leakage protection unit 800 is turned on, causing the leakage protection unit 800 to fail. In order to ensure that the leakage protection unit 800 outputs a high potential normally, this embodiment uses the leakage resistance interruption unit 900 to pass a high-potential pull-up control signal Cout-PU, blocking the leakage path of the first node Q[n] through the forty-third transistor T43 and the forty-fourth transistor T44 during the charging process.

[0060] In one embodiment, as shown in Figure 3, the second electrode of the leakage resistance interruption unit 900 is connected to the first electrode of the sixty-first transistor T61 and the second electrode of the sixty-second transistor T62 at the third node N[n]. When the pull-up control unit 100 is connected to a high-potential pull-up control signal Cout-PU, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the first node Q[n] is charged to a high potential. If the threshold voltage of the sixty-first transistor T61 and the sixty-second transistor T62 is negatively biased, the first node Q[n] will leak before the leakage protection unit 800 is turned on, causing the leakage protection unit 800 to fail. In order to ensure that the leakage protection unit 800 outputs a high potential normally, this embodiment uses the leakage resistance interruption unit 900 to pass a high-potential pull-up control signal Cout-PU, blocking the leakage path of the first node Q[n] through the sixty-first transistor T61 and the sixty-second transistor T62 during the charging process.

[0061] In one embodiment, the leakage protection unit 800 includes an eighty-first transistor and an eighty-second transistor; the gates of the eighty-first transistor and the eighty-second transistor are simultaneously connected to a first node Q[n], the first electrode of the eighty-first transistor is connected to a third node N[n], the second electrode of the eighty-first transistor is connected to the first electrode of the eighty-second transistor, and the second electrode of the eighty-second transistor is connected to a high-potential signal VGH.

[0062] With the above structure, when the first node Q[n] is charged to a high potential, a high-point micro signal is applied to the second electrode of the eighty-second transistor. This can prevent leakage of the first node Q[n] before the eighty-first and eighty-second transistors are turned on.

[0063] In this embodiment, all transistors can be thin-film transistors, specifically low-temperature polycrystalline silicon thin-film transistors, oxide semiconductor thin-film transistors, or amorphous silicon thin-film transistors.

[0064] Among them, amorphous silicon thin-film transistors (a-Si TFTs) are widely used thin-film transistors. They have advantages such as mature and stable technology, low driving voltage, low power consumption, and low cost, making them suitable for mass production.

[0065] Low-temperature poly-silicon thin film transistors (LTPS-TFTs) have outstanding advantages such as high carrier mobility and small size, and are a key technology for developing low-power, highly integrated display panels.

[0066] Oxide thin-film transistors (OTFTs) have a carrier concentration approximately ten times that of amorphous silicon (ASS) thin-film transistors (TFTs), and a carrier mobility 20-30 times higher. Therefore, OTFTs can significantly improve the charge-discharge rate of pixel electrodes, increasing pixel response speed and enabling faster refresh rates. OTFTs are well-suited for applications requiring fast response and high current, such as high-frequency, high-resolution, large-size displays and organic light-emitting diode (OLED) displays. OTFTs are increasingly becoming semiconductor components used in next-generation LCD and LED display devices.

[0067] In this embodiment, of the first electrode and the second electrode of each transistor, one is the source and the other is the drain.

[0068] In this embodiment, a first transistor T1 can be connected between the forty-first transistor T41 and the forty-second transistor T42 to block the leakage path of the first node Q[n] through the forty-first transistor T41 and the forty-second transistor T42. Alternatively, a first transistor T1 can be connected between the forty-third transistor T43 and the forty-fourth transistor T44 to block the leakage path of the first node Q[n] through the forty-third transistor T43 and the forty-fourth transistor T44. Furthermore, a first transistor T1 can be connected between the sixty-first transistor T61 and the sixty-second transistor T62 to block the leakage path of the first node Q[n] through the sixty-first transistor T61 and the sixty-second transistor T62.

[0069] This invention provides a display panel, including an array substrate and a GOA circuit provided in the above embodiment, wherein the GOA circuit is connected to the array substrate.

[0070] In the GOA circuit structure of the display panel in this embodiment, the leakage resistance interruption unit 900 can improve the situation where leakage occurs in the first node Q[n] due to the negative bias of the TFT threshold voltage of the first pull-down unit 300 and / or the second pull-down unit 600 during the operation of the GOA circuit. It effectively blocks the leakage path between the first node Q[n] and the first pull-down unit 300 and / or the second pull-down unit 600, ensuring that the first node Q[n] is charged normally to the required high potential, and the normal operation of the subsequent leakage protection unit 800.

[0071] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A GOA circuit, characterized in that, include: The pull-up control unit is connected to the first node and receives a pull-up control signal to pull up the potential of the first node. The pull-up unit is connected to the first node and connected to a clock signal to pull up the potentials of the first output signal, the second output signal, and the cascade scan signal. The first pull-down unit is connected to the first node, the second node, and the third node, and is connected to a first low-potential signal to pull down the potential of the first node. The first pull-down sustaining unit is connected to the first node and the second node, and is connected to the first low-potential signal, the second low-potential signal, the first output signal, the second output signal and the cascade scan signal, for maintaining the low potential of the first output signal, the second output signal and the cascade scan signal; The second pull-down unit is connected to the first node and the third node, and is connected to the pull-down control signal and the first low potential signal, for pulling down the potential of the first node; The second pull-down sustaining unit is connected to the second pull-down unit and is connected to the first low-potential signal and the second low-potential signal, and is used to maintain the low potential of the first output signal, the second output signal and the cascade scan signal; An inverting unit is connected to the first node and the second node, and is connected to the first low-potential signal, the pull-up control signal, the low-frequency clock signal and the third low-potential signal, for keeping the potentials of the first node and the second node opposite; The leakage protection unit is connected to the first node and the third node, and is connected to a high-potential signal to prevent leakage from the first node. A leakage resistance interruption unit is connected to the first pull-down unit and / or the second pull-down unit, and is connected to the pull-up control signal and the high-potential signal. When the pull-up control signal is high, the leakage resistance interruption unit is turned on, and the first pull-down unit and / or the second pull-down unit are charged with a high potential to prevent the first node from leaking current through the first pull-down unit and / or the second pull-down unit. The leakage resistance interruption unit includes a first transistor. The gate of the first transistor is connected to the pull-up control signal, the first electrode is connected to the high-potential signal, and the second electrode is connected to the first pull-down unit and / or the second pull-down unit at the third node.

2. The GOA circuit according to claim 1, characterized in that, The inverting unit includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gate and first electrode of the second transistor, and the gate of the third transistor, are all connected to the low-frequency clock signal. The second electrode of the second transistor is connected to the first electrode of the third transistor, and the second electrode of the third transistor is connected to the first electrode of the fourth transistor. The gate of the fourth transistor is connected to the first node, and its second electrode is connected to the third low-potential signal. The gate of the fifth transistor is connected to the second electrode of the third transistor, its first electrode is connected to the low-frequency clock signal, and its second electrode is connected to the second node. The gate of the sixth transistor is connected to the first node, its first electrode is connected to the first low-potential signal, and its second electrode is connected to the second node. The gate of the seventh transistor is connected to the first node of the next stage, its first electrode is connected to the third low-potential signal, and its second electrode is connected to the second electrode of the third transistor. The gate of the eighth transistor is connected to the pull-up control signal, its first electrode is connected to the first low-potential signal, and its second electrode is connected to the second node.

3. The GOA circuit according to claim 1, characterized in that, The pull-up control unit includes an eleventh transistor and a twelfth transistor; the gate and first electrode of the eleventh transistor and the gate of the twelfth transistor are all connected to the pull-up control signal; the second electrode of the eleventh transistor is connected to the first electrode of the twelfth transistor; and the second electrode of the twelfth transistor is connected to the first node.

4. The GOA circuit according to claim 1, characterized in that, The pull-up unit includes a 21st transistor, a 22nd transistor, a 23rd transistor, a first storage capacitor, a second storage capacitor, and a third storage capacitor. The clock signal includes a first clock signal, a second clock signal, and a third clock signal. The gate of the 21st transistor is connected to the first node, the first electrode is connected to the first clock signal, and the second electrode is connected to the first output signal. The gate of the 22nd transistor is connected to the first node, the first electrode is connected to the second clock signal, and the second electrode is connected to the stage scan signal; the gate of the 23rd transistor is connected to the first node, the first electrode is connected to the third clock signal, and the second electrode is connected to the second output signal. One end of the first storage capacitor is connected to the first node, and the other end is connected to the second electrode of the twenty-first transistor; One end of the second storage capacitor is connected to the first node, and the other end is connected to the second electrode of the 22nd transistor; One end of the third storage capacitor is connected to the first node, and the other end is connected to the second electrode of the twenty-third transistor.

5. The GOA circuit according to claim 1, characterized in that, The first pull-down sustaining unit includes a thirty-first transistor, a thirty-second transistor, and a thirty-third transistor; the gate of the thirty-first transistor is connected to the second node, the first electrode is connected to the first low-potential signal, and the second electrode is connected to the first output signal; The gate of the thirty-second transistor is connected to the second node, the first electrode is connected to the second low-potential signal, and the second electrode is connected to the stage scan signal; the gate of the thirty-third transistor is connected to the second node, the first electrode is connected to the second low-potential signal, and the second electrode is connected to the second output signal.

6. The GOA circuit according to claim 1, characterized in that, The first pull-down unit includes a forty-first transistor and a forty-second transistor; the gate of the forty-first transistor and the gate of the forty-second transistor are simultaneously connected to the second node; the first electrode of the forty-second transistor is connected to the first low-potential signal; the first electrode of the forty-first transistor and the second electrode of the forty-second transistor are connected to the third node; and the second electrode of the forty-first transistor is connected to the first node.

7. The GOA circuit according to claim 1, characterized in that, The second pull-down sustaining unit includes a 51st transistor, a 52nd transistor, and a 53rd transistor; the gate of the 51st transistor is connected to the second pull-down unit, the first electrode is connected to the first low-potential signal, and the second electrode is connected to the first output signal; The gate of the fifty-second transistor is connected to the second pull-down unit, the first electrode is connected to the second low-potential signal, and the second electrode is connected to the stage scan signal; the gate of the fifty-third transistor is connected to the second pull-down unit, the first electrode is connected to the second low-potential signal, and the second electrode is connected to the second output signal.

8. The GOA circuit according to claim 7, characterized in that, The second pull-down unit includes a forty-third transistor, a forty-fourth transistor, a sixty-first transistor, and a sixty-second transistor; the gates of the forty-third transistor and the forty-fourth transistor are both connected to the pull-down control signal; the first electrode of the forty-fourth transistor is connected to the first low-potential signal, and its second electrode is connected to the first electrode of the forty-third transistor at the third node, while the second electrode of the forty-third transistor is connected to the first node; the gates of the sixty-first transistor, the sixty-second transistor, the fifty-first transistor, the fifty-second transistor, and the fifty-third transistor are all connected together; the first electrode of the sixty-second transistor is connected to the first low-potential signal, and its second electrode is connected to the first electrode of the sixty-first transistor at the third node, while the second electrode of the sixty-first transistor is connected to the first node.

9. A display panel, characterized in that, It includes an array substrate and a GOA circuit as described in any one of claims 1 to 8, wherein the GOA circuit is connected to the array substrate.

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