Read-only memory circuit, read-only memory, and electronic device

Abstract

This application provides a read-only memory circuit, a read-only memory, and an electronic device, relating to the field of storage technology. The read-only memory circuit includes a transistor array, a switching circuit, multiple word lines, multiple bit lines, and a ground line. In the transistor array: multiple transistors located in the same row are connected in series; the gates of multiple transistors located in the same column are connected to the same word line; and the multiple bit lines are respectively configured to correspond one-to-one with transistors in different rows. The multiple bit lines are connected to the ground line through the switching circuit. The transistor array includes: a first transistor and a second transistor located in the same column and in adjacent rows; the multiple bit lines include: a first bit line corresponding to the multiple transistors in the row containing the first transistor, and a second bit line corresponding to the multiple transistors in the row containing the second transistor. The first terminal of the first transistor is connected to the first bit line, the second terminal of the first transistor is connected to the second terminal of the second transistor, and the first terminal of the second transistor is connected to the second bit line.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a read-only storage circuit, a read-only memory, and an electronic device. Background Technology

[0002] Read-only memory (ROM) is a type of semiconductor memory that operates in a non-destructive read-only manner, allowing only reading and not writing of information. The data stored in ROM is typically written during the chip manufacturing process; once written, the information is fixed and will not be lost even if power is cut off. It also has a simple structure and is easy to use, making it commonly used to store various fixed programs and data. Mask ROM, in particular, has its data programmed by the integrated circuit manufacturer (i.e., factory programmed). The data is provided by the customer to the manufacturer, converted into a custom mask layer, and ultimately stored in a network of metal wires.

[0003] Masked ROMs are more compact in terms of storage area per byte and are less expensive, giving them an advantage over any other type of semiconductor memory. Figure 1 This is a storage circuit diagram of a mask ROM (hereinafter referred to as ROM) provided in related technologies. Figure 2 It corresponds Figure 1 The layout of storage units. For example... Figure 1 and Figure 2 As shown, in this ROM, a dummy MOS needs to be inserted between every two MOS (metal oxide semiconductor field effect transistors), such as... Figure 1 Inserting an NMOSd between NMOS0 and NMOS1 in the ROM results in wasted memory cell area. Additionally, this ROM requires two metal signal lines (bit line BL and ground line VSS) above each row of MOS, which also wastes memory cell area. Summary of the Invention

[0004] This application provides a read-only memory circuit, a read-only memory, and an electronic device that can reduce the area of ​​the memory cell.

[0005] This application provides a read-only memory circuit, including a transistor array, a switching circuit, multiple word lines, multiple bit lines, and a ground line. The transistor array includes multiple transistors; wherein, in the transistor array: multiple transistors located in the same row are connected in series, the gates of multiple transistors located in the same column are connected to the same word line, and the multiple bit lines are respectively configured to correspond one-to-one with transistors in different rows. The multiple bit lines are connected to the ground line through the switching circuit. The transistor array includes: a first transistor and a second transistor located in the same column and in adjacent rows; the multiple bit lines include a first bit line and a second bit line; the first bit line corresponds to multiple transistors in the row containing the first transistor, and the second bit line corresponds to multiple transistors in the row containing the second transistor. The first terminal of the first transistor is connected to the first bit line, the second terminal of the first transistor is connected to the second terminal of the second transistor, and the first terminal of the second transistor is connected to the second bit line.

[0006] In this read-only memory circuit, the first terminal of the first transistor is connected to the first bit line, and the second terminal of the first transistor is connected to the second bit line through the second transistor. In this case, the first and second transistors are turned on through the word line, and the second bit line is connected to the ground line through the switching circuit. Thus, the high potential stored on the first bit line can be pulled down to a low potential through the second bit line, thereby enabling the reading of the "0" signal in the first transistor.

[0007] Furthermore, compared to the read-only memory circuits in related technologies that require setting up dummy memory cells between adjacent memory cells and arranging two metal signal lines (bit lines and ground lines) above the memory cells, in the read-only memory circuit provided in this application embodiment, each transistor serves as a memory cell for data storage, eliminating the need for dummy memory cells and avoiding the waste of storage area caused by dummy memory cells. Moreover, by setting up connections between adjacent rows of transistors, the bit lines and ground lines corresponding to the transistors in the next row can be connected to serve as the ground lines for the transistors in the previous row, thus fulfilling the storage requirements. Only a separate ground line needs to be set for the last row of transistors to meet its storage requirements, which is equivalent to saving about half (50%) of the ground lines, thereby further reducing the area of ​​the memory cells and increasing the density of the transistor array constrained by metal lines.

[0008] In some possible implementations, the transistor array also includes a third transistor and a fourth transistor located in the same column and in adjacent rows. Multiple bit lines include a third bit line and a fourth bit line; the third bit line corresponds to multiple transistors in the row containing the third transistor, and the fourth bit line corresponds to multiple transistors in the row containing the fourth transistor. The first terminal of the third transistor is connected to the first terminal of the fourth transistor, and the second terminal of the third transistor is connected to the second terminal of the fourth transistor. In this case, neither the first nor the second terminal of the third transistor is connected to the corresponding bit line. This way, when the third transistor is activated via a word line, the stored high potential on the bit line does not change, thus enabling the reading of a "1" signal.

[0009] In some possible implementations, a fifth bit line is included among the multiple bit lines, corresponding to the last row of transistors in the transistor array. The last row of transistors includes a fifth transistor; the first terminal of the fifth transistor is connected to either the fifth bit line or ground; the second terminal of the fifth transistor is also connected to either the fifth bit line or ground. For the last row of transistors in the transistor array, some or all of the first and / or second terminals of the transistors are selectively connected to ground to meet actual memory requirements.

[0010] In some possible implementations, the start or end of multiple transistors arranged in series in each row of the transistor array is connected to the corresponding bit line. By fixing the start or end (i.e., source or drain) of the transistors in each row, the connection method of the other end (i.e., drain or source) of each transistor is set sequentially according to the data storage requirements.

[0011] In some possible implementations, the transistor array includes n rows of transistors, where n is less than or equal to 32; this avoids the potential impact on the bit lines of subsequent rows caused by an excessive number of bit lines in the preceding row, thus ensuring accurate reading of the stored data in each row of transistors.

[0012] In some possible implementations, the transistors and bit lines, ground lines, and intermediate connection lines between transistors in adjacent rows are distributed on a first metal layer; multiple bit lines and ground lines are distributed on a second metal layer; the first metal layer is located between multiple transistors and the second metal layer; the bit lines and ground lines extend along the row direction of the transistor array; the intermediate connection lines extend along the column direction of the transistor array; and the positions of the multiple bit lines are respectively aligned with the positions of the transistors in each row.

[0013] In some possible implementations, the ground wire is positioned directly opposite the position of the last row of transistors in the transistor array.

[0014] In some possible implementations, the bit line corresponding to the last row of transistors is the fifth bit line; the ground line is located on the side of the fifth bit line away from the transistor array.

[0015] This application provides a read-only memory circuit, comprising: multiple transistors arranged in an array of m rows and n columns, m bit lines, n word lines, and a ground line; where m and n are both positive integers greater than or equal to 1. Transistors in the same row are connected in series. The n word lines are connected one-to-one with the gates of the n columns of transistors. The source of the transistor in the i-th row is connected to the i-th bit line, or to the source of a transistor in the same column of the (i+1)-th row. The drain of the transistor in the i-th row is connected to the i-th bit line, or to the drain of a transistor in the same column of the (i+1)-th row; 1 ≤ i ≤ m-1, and i is a positive integer.

[0016] In some possible implementations, the source of the transistor in the m-th row is connected to the m-th bit line or ground. The drain of the transistor in the m-th row is connected to the m-th bit line or ground.

[0017] Compared to the read-only memory circuits in related technologies, which require setting up dummy memory cells between adjacent memory cells and arranging two metal signal lines (bit lines and ground lines) above the memory cells, the memory circuit provided in this application embodiment uses each transistor as a memory cell for data storage, eliminating the need for dummy memory cells and avoiding the waste of storage area caused by dummy memory cells. Furthermore, by setting up connections between adjacent rows of transistors, the bit lines and ground lines corresponding to the transistors in the next row can be connected to serve as the ground lines for the transistors in the previous row, thus fulfilling the storage requirements. Only a separate ground line needs to be set for the last row of transistors to meet its storage requirements, which is equivalent to saving about half (50%) of the ground lines, thereby further reducing the area of ​​the memory cells and increasing the density of the transistor array constrained by metal lines.

[0018] In some possible implementations, the start or end of multiple transistors arranged in m rows in series are connected to the bit line. In this case, the start or end (i.e., source or drain) of each transistor in each row is fixed, and the connection method of the other end (i.e., drain or source) of each transistor is set sequentially according to the data storage requirements.

[0019] In some possible implementations, the storage circuitry also includes a switching circuit; the m bit lines are connected to the ground line via the switching circuit; the switching circuit is configured to control the on / off state between each bit line and the ground line. In this case, the m bit lines are connected to the ground line via the switching circuit, and the on / off state between each bit line and the ground line VSS is controlled by the switching circuit to meet the storage requirements.

[0020] In some possible implementations, n is less than or equal to 32; this avoids the potential impact on subsequent bit lines caused by an excessive number of bit lines in the preceding row, thus ensuring accurate reading of the stored data in each row of transistors.

[0021] In some possible implementations, the sources and drains of multiple transistors, along with bit lines, ground lines, and intermediate connections between transistors in adjacent rows, are distributed on a first metal layer. m bit lines and ground lines are distributed on a second metal layer. The first metal layer lies between the multiple transistors arranged in an array of m rows and n columns and the second metal layer. Bit lines and ground lines extend along the row direction. Intermediate connections extend along the column direction. The position of the i-th bit line is directly opposite the position of the transistor in the i-th row.

[0022] In some possible implementations, the ground wire is positioned directly opposite the position of the transistor in the m-th row.

[0023] In some possible implementations, the ground line is located on the side of the m-th bit line that is away from the (m-1)-th bit line.

[0024] This application embodiment also provides a method for reading a memory circuit as provided in any of the aforementioned possible implementations. The method may include: pre-charging the 1st, 2nd, ..., xth bit lines and controlling the (x+1th, x+2th, ..., mth)th bit lines to be connected to the ground line; wherein 1 ≤ x ≤ m, and x is a positive integer; inputting an enable signal to the yth word line to turn on the yth column transistor, and reading the stored data in the transistor located in the xth row and yth column through the xth row bit line; wherein 1 ≤ y ≤ n, and y is a positive integer.

[0025] This application also provides a read-only memory, including a controller and a storage circuit as provided in any of the aforementioned possible implementations; the controller is connected to the storage circuit.

[0026] This application also provides an electronic device, including a printed circuit board and a read-only memory provided in any of the aforementioned possible implementations; the read-only memory is connected to the printed circuit board. Attached Figure Description

[0027] Figure 1 This is a storage circuit provided in related technologies;

[0028] Figure 2 For the corresponding Figure 1 A schematic diagram of the memory circuit layout;

[0029] Figure 3 A storage circuit provided in an embodiment of this application;

[0030] Figure 4 A storage circuit provided in an embodiment of this application;

[0031] Figure 5 A method for reading a storage circuit provided in an embodiment of this application;

[0032] Figure 6A schematic diagram of a memory circuit provided in an embodiment of this application;

[0033] Figure 7 This is a schematic diagram of a memory circuit provided in an embodiment of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Words such as "connected," "linked," etc., are used to express communication or interaction between different components and may include direct connection or indirect connection through other components. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Terms such as "upper," "lower," "left," and "right," etc., are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0036] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0037] This application provides an electronic device, which includes a printed circuit board (PCB) and a read-only memory (ROM) connected to the PCB. This application does not limit the configuration of the electronic device. For example, the electronic device can be a mobile phone, tablet computer, laptop, in-vehicle computer, smartwatch, smart bracelet, or other electronic products.

[0038] The aforementioned read-only memory is equipped with a controller and a read-only memory circuit (also referred to as a storage circuit) connected to the controller. The controller controls the read-only memory circuit, thereby enabling the data stored in the read-only memory circuit to be read out.

[0039] Compared to Figure 1 In contrast to the traditional storage circuit, which requires setting up dummy storage cells (NMOSd) between every two adjacent storage cells (NMOS0, NMOS1) and arranging two metal signal lines (bit line BL, ground line VSS) above the storage cells, the storage circuit used in the read-only memory provided in this application eliminates the dummy storage cells (equivalent to saving 1 / 3 of the number of transistors) and does not require a ground line VSS on each row of storage cells (equivalent to saving about 1 / 2 of the ground lines), thereby reducing the area of ​​the storage cells.

[0040] The specific configuration of the read-only memory circuit provided in the embodiments of this application will be described below.

[0041] like Figure 3 As shown in the figure, this application embodiment provides a read-only memory circuit, which includes a transistor array. The transistor array contains multiple transistors arranged in an array of m rows and n columns, meaning the read-only memory circuit has m*n transistors (i.e., memory cells) arranged in a matrix. The transistor located in the x-th row and y-th column is denoted as Nx_y. x, y, m, and n are all positive integers greater than or equal to 1, and 1 ≤ x ≤ m, 1 ≤ y ≤ n.

[0042] It should be noted that the aforementioned transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET), which can be simply referred to as a MOS transistor. This MOS transistor can be an NMOS transistor or a PMOS transistor; this application does not impose any limitation on this. The embodiments in this application are all illustrated using an NMOS transistor in the read-only memory circuit as an example.

[0043] It should be understood that a transistor itself has a source, a drain, and a gate. (Reference) Figure 3In the transistor N1_1, this application embodiment does not explicitly distinguish between the source s and the drain d of the transistor. The source s and the drain d can be interchanged, that is, the source s and the drain d are two equivalent poles; that is, of the two poles of the transistor other than the gate (the first pole and the second pole), one is the source s and the other is the drain d; for example, if the first pole is the source s, then the second pole is the drain d; if the first pole is the drain d, then the second pole is the source s.

[0044] To clearly describe the connection relationships of the transistors in the read-only memory circuit, embodiments of this application define the source (s) and drain (d) of each transistor according to their relative positions in the transistor array. Embodiments of this application define electrodes on the same side of each transistor as electrodes of the same type (i.e., source or drain). For example, refer to... Figure 3 As shown, the left electrode of each transistor can be defined as the source (s), and the right electrode as the drain (d); conversely, the left electrode of each transistor can be defined as the drain (d), and the right electrode as the source (s). The following embodiments illustrate this with the left electrode of each transistor as the source (s) and the right electrode as the drain (d).

[0045] Based on this, such as Figure 3 As shown, this read-only memory circuit, in addition to the aforementioned transistor array, also includes m bit lines BL, n word lines WL, a ground line VSS, and a switching circuit C. The m bit lines BL can be represented as BL1, BL2, ..., BLm; the n word lines WL can be represented as WL1, WL2, ..., WLn.

[0046] like Figure 3 As shown, in a transistor array, n transistors (i.e., Nx_1, Nx_2, ..., Nx_n) located in the same row are connected in series; that is, in two adjacent transistors located in the same row (refer to...) Figure 3 In the array N1_1, N1_2), the drain d of the previous transistor is electrically connected to the source s of the next transistor. m bit lines BL are configured one-to-one with m rows of transistors. For example, bit line BL1 is configured to correspond to the transistors in the first row of the transistor array, so that the stored data in the transistors of the first row can be read through bit line BL1; bit line BL2 is configured to correspond to the transistors in the second row of the transistor array, so that the stored data in the transistors of the second row can be read through bit line BL2.

[0047] It should be noted that all or some transistors located in the same row are connected to the corresponding bit lines to enable reading the data stored in each transistor. The specific connection method of each transistor is related to the actual stored data ("0" or "1") in the transistor, which can be found in the relevant description below.

[0048] like Figure 3As shown, n word lines WL are configured one-to-one with n columns of transistors in the transistor array. The gates of m transistors (N1_y, N2_y, ..., Nm_y) in the same column are connected to the same word line WL. Transistors in different columns are connected to different word lines. That is, the n word lines (WL1, WL2, ..., WLn) are connected one-to-one with the gates of the n columns of transistors. For example, word line WL1 is connected to the gates of the m transistors in the first column, word line WL2 is connected to the gates of the m transistors in the second column, and so on.

[0049] like Figure 3 As shown, m bit lines BL are connected to ground VSS via a switching circuit C, so that the switching circuit C controls the on / off connection between each bit line BL and ground VSS. (Illustrative example follows.) Figure 3 As shown, the switching circuit C can include m switches (K1, K2, ..., Km), and the m bit lines BL are connected to the ground line VSS through different switches. Thus, by controlling each switch, the connection and disconnection between each bit line BL and the ground line VSS can be realized.

[0050] It should be noted that, Figure 3 The illustration is merely illustrative, using the example of a switch circuit C where each bit line BL is connected to the ground line VSS. However, this application is not limited to this. In some possible implementations, switches may be provided between some bit lines BL and the ground line VSS in the switch circuit C. For example, no switch may be provided between the first bit line BL1 and the ground line VSS, and switches may only be provided between the second bit line to the m-th bit line and the ground line VSS.

[0051] Compared to Figure 1 In contrast to the previous approach that required a separate ground line VSS for each row of transistors, the read-only memory circuit provided in this application, based on the configuration of m bit lines BL connected to the ground line VSS via a switching circuit C, connects the transistors in adjacent rows to the transistors in the next row. This allows the bit line corresponding to the transistor in the next row to be connected to the ground line, serving as the ground line for the transistor in the previous row, thus meeting the storage requirements of the transistor in the previous row. The following provides a detailed description of the connections between the transistors in each row and between them and the bit lines and ground lines in the read-only memory circuit of this application.

[0052] refer to Figure 3 As shown, in the transistors from row 1 to row m-1 (i.e., except for the last row of transistors), the source s of any row (row i) of transistors can be connected to the bit line (BLi) corresponding to the transistor in that row, or it can be connected to the source s of the transistor in the same column in the next row (row i+1); where 1≤i≤m-1, and i is a positive integer.

[0053] Similarly, the drain d of the transistor in the i-th row can be connected to the i-th bit line BLi, or it can be connected to the drain d of the transistor in the same column in the (i+1)-th row.

[0054] In other words, for any transistor Nx_y in the transistor array, there may be four possible connection methods.

[0055] In the first connection method, the source (s) and drain (d) of transistor Nx_y are both connected to the corresponding bit line BLx.

[0056] In the second connection method, the source s and drain d of transistor Nx_y are connected to the source s and drain d of transistor N(x+1_y) located in the next row and column, respectively.

[0057] In the third connection method, the source s of transistor Nx_y is connected to the corresponding bit line BLx, and the drain d of transistor Nx_y is connected to the drain d of transistor N(x+1_y) located in the next row and column.

[0058] The fourth connection method is that the source s of transistor Nx_y is connected to the source s of transistor N(x+1_y) located in the next row and column, and the drain d of transistor Nx_y is connected to the bit line BLx that is set accordingly.

[0059] It is understandable that in a transistor array, the specific connection method of the source s and drain d of a transistor directly determines the stored data ("0" or "1") in that transistor. Therefore, the connection method of the source s and drain d of the transistor can be set according to the actual storage requirements to ensure that each transistor can satisfy the storage of "0" or "1".

[0060] As illustrated, in actual circuit design, the connection method of the source s (or drain d) of the transistor can be fixed, and the connection method of the drain d (or source s) of the transistor can be set according to the storage requirements ("0" or "1").

[0061] For example, in some possible implementations, such as Figure 3 As shown, multiple transistors arranged in m rows in series can be designed with their starting terminals connected to the bit line corresponding to their respective rows; that is, the source s of the first column transistor (i.e., Nx_1) is connected to the bit line BLx corresponding to its respective row. In this case, the connection method of the drain of the first column transistor (i.e., Nx_1) is set according to its storage requirements, and the connection method of the drain of the second column transistor (i.e., Nx_2) is set according to the connection method of the drain of the first column transistor (i.e., Nx_1) to meet the storage requirements of the second transistor, and so on, the connection method of the drain of subsequent transistors can be designed from left to right.

[0062] Similarly, in other possible implementations, multiple transistors arranged in m rows in series can be designed with their ends connected to the bit line corresponding to their respective row; that is, the drain d of the nth column transistor (i.e., Nx_n) is connected to the bit line BLx corresponding to its row. In this case, the connection method of the source of the nth column transistor is set according to the storage requirements of the nth column transistor, and the connection method of the source of the previous transistor is set according to the connection method of the drain of the nth column transistor to meet the storage requirements of the previous transistor, and so on, and the connection method of the source of the subsequent transistors can be designed from right to left.

[0063] The following is for reference Figure 4 The data storage of a read-only memory circuit is explained using a 4x3 transistor array, combined with the specific source and drain connection methods of the transistors. Figure 4 The example below uses the source s of the first column transistor (i.e., Nx_1) connected to the corresponding bit line BLx in its row as an example. Figure 4 Switching circuit C is not shown in the diagram. The connection of switching circuit C can be found in [reference needed]. Figure 3 .

[0064] by Figure 4 In the example of transistors N1_1 (also called the first transistor) and N1_2 (also called the second transistor), which are located in the same column and adjacent rows respectively, transistor N1_1 stores "0". Note that the first transistor and the second transistor do not refer to two specific transistors; they can be any two transistors located in the same column and adjacent rows in the transistor array.

[0065] For transistor N1_1, the source (i.e., node r1c1) of transistor N1_1 is fixedly connected to bit line BL1. For example... Figure 4 As shown, the drain of transistor N1_1 (i.e., node r1c2) can be connected to the drain of transistor N2_1 (i.e., node r2c2). In this way, when transistors N1_1 and N2_1 are turned on through word line WL2, node r1c2 is at the same potential as bit line BL2. By controlling bit line BL2 to be connected to ground line VSS through switching circuit C, the high potential stored on bit line BL1 can be pulled down to a low potential (the specific control method can be referred to the relevant content below), thereby enabling the reading of the "0" signal.

[0066] Of course, if the source of transistor N1_1 (i.e., node r1c1) is fixedly connected to bit line BL1, and it is necessary to store "1" in transistor N1_1, the drain of transistor N1_1 (i.e., node r1c2) can also be connected to bit line BL1. In this way, when transistor N1_1 is turned on through word line WL1, the high potential stored on bit line BL1 will not change, thus enabling the reading of the "1" signal.

[0067] Taking transistors N1_2 (also known as the third transistor) and N2_2 (also known as the fourth transistor), which are located in the same column and adjacent rows respectively, as an example, transistor N1_2 stores "1". Here, the third and fourth transistors do not refer to two specific transistors; they could be any two transistors located in the same column and adjacent rows in the transistor array.

[0068] For transistor N1_2, the source of transistor N1_2 (i.e., node r1c1) is fixedly connected to node r2c2. For example... Figure 4 As shown, the drain of transistor N1_2 (i.e., node r1c3) can be connected to the drain of transistor N2_2 (i.e., node r2c3). In this case, neither the source nor the drain of transistor N1_2 is connected to bit line BL1. In this way, when transistors N1_2 and N2_2 are turned on through word line WL2, the high potential stored on bit line BL1 will not change, thus enabling the reading of the "1" signal.

[0069] Of course, if the source of transistor N1_2 (i.e., node r1c1) is fixedly connected to node r2c2, and it is necessary to store "1" in transistor N1_2, the drain of transistor N1_2 (i.e., node r1c3) can be connected to bit line BL1. In this way, when transistors N1_2 and N2_2 are turned on through word line WL2, node r1c2 and bit line BL2 are at the same potential. The switching circuit C can control the bit line BL2 to be connected to the ground line VSS, thereby pulling down the high potential stored on bit line BL1 to a low potential, and thus enabling the reading of the "0" signal.

[0070] Taking transistor N2_3 as an example, the source of transistor N2_3 (i.e., node r2c3) is fixedly connected to bit line BL2.

[0071] If it is necessary to store "1" in transistor N2_3, such as Figure 4 As shown, the drain of transistor N2_3 (i.e., node r2c4) can also be connected to bit line BL2. In this way, when transistor N2_3 is turned on through word line WL3, the high potential stored on bit line BL2 will not change, thus enabling the reading of the "1" signal.

[0072] Of course, if it is necessary to store "0" in transistor N2_3, the drain of transistor N2_3 (i.e., node r2c4) can be connected to the drain of transistor N3_3 (i.e., node r3c4). In this way, when transistors N2_3 and N3_3 are turned on through word line WL3, node r2c4 is at the same potential as bit line BL3. By controlling bit line BL3 to connect to ground line VSS through switching circuit C, the high potential stored on bit line BL2 can be pulled down to a low potential, thereby enabling the reading of the "0" signal.

[0073] In summary, compared to the read-only memory circuits in related technologies that require setting up dummy memory cells between adjacent memory cells and arranging two metal signal lines (bit lines and ground lines) above the memory cells, the read-only memory circuit provided in this application uses each transistor as a memory cell for data storage, eliminating the need for dummy memory cells and avoiding the waste of storage area caused by dummy memory cells. Furthermore, by setting up connections between adjacent rows of transistors, the bit lines and ground lines corresponding to the transistors in the next row can be connected to serve as the ground lines for the transistors in the previous row, thus fulfilling the storage requirements. This is equivalent to saving about half (50%) of the ground lines, thereby further reducing the area of ​​the memory cells and increasing the density of the transistor array constrained by metal lines.

[0074] Furthermore, there are no transistors in the next row for the last row of transistors. Therefore, to meet the storage requirements of the last row of transistors, they can be directly connected to ground.

[0075] For illustrative purposes only, please refer to the following: Figure 3 As shown, for the last row (row m) of transistors (also referred to as the fifth transistor), the source s of the transistors in that row (row m) can be connected to the bit line (BLm; also referred to as the fifth bit line) corresponding to the transistor in that row, or it can be connected to the ground line VSS. Similarly, the drain d of the transistors in that row (row m) can be connected to the bit line (BLm) corresponding to the transistor in that row, or it can be connected to the ground line VSS.

[0076] The following is a schematic description of the reading method of the read-only memory circuit provided in the embodiments of this application.

[0077] refer to Figure 3 As shown, taking the reading of stored data from transistor Nx_y (i.e., any transistor) in the x-th row and y-th column of a read-only memory circuit as an example, as follows... Figure 5 As shown, the reading method may include:

[0078] Step 01: Precharge the 1st, 2nd, ..., xth bit lines, and control the (x+1), (x+2), ..., m)th bit lines BL to be connected to the ground line VSS.

[0079] Step 02: Input the enable signal to the y-th word line WLy to turn on the y-th column transistor, and read the stored data in the y-th row and y-th column transistor Nx_y through the x-th row bit line BLx.

[0080] Indicative, for reading Figure 4 Taking the stored data ("0") in transistor N1_1 as an example, step 01 pre-charges bit line BL1, that is, inputs a high-level potential to bit line BL1; and connects the other bit lines BL2, BL3, and BL4 to ground line VSS. Then, step 02 inputs an enable signal to word line WL1 to turn on the first column of transistors. In this case, the drain of transistor N1_1 (i.e., node r1c2) is at the same potential as bit line BL2 (i.e., grounded), thereby pulling down the high-level potential input to bit line BL1 to a low potential; at this time, the stored data "0" in transistor N1_1 is read from bit line BL1.

[0081] Indicative, for reading Figure 4 Taking the stored data ("1") in transistor N2_3 as an example, step 01 pre-charges bit lines BL1 and BL2, that is, inputs a high-level potential to bit lines BL1 and BL2; and connects the other bit lines BL3 and BL4 to the ground line VSS. Then, step 02 inputs an enable signal to word line WL3 to turn on the third column transistor. Under this condition, the high potential on bit line BL2 does not change; at this time, the stored data "1" in transistor N2_3 is read from bit line BL2.

[0082] Indicative, for reading Figure 4 Taking the stored data ("0") in transistor N3_1 as an example, step 01 precharges bit lines BL1, BL2, and BL3, that is, inputs a high-level potential to bit lines BL1, BL2, and BL3; and connects the other bit line BL4 to the ground line VSS. Then, step 02 inputs an enable signal to word line WL1 to turn on the first column of transistors. In this case, the drain of transistor N3_1 (i.e., node r3c2) is at the same potential as bit line BL4 (i.e., grounded), thereby pulling down the high-level potential input to bit line BL3 to a low potential; at this time, the stored data "0" in transistor N3_1 is read from bit line BL3.

[0083] Indicative, for reading Figure 4Taking the stored data ("0") in transistor N4_1 as an example, step 01 precharges bit lines BL1, BL2, BL3, and BL4, that is, inputs a high-level potential to bit lines BL1, BL2, BL3, and BL4. Then, step 02 inputs an enable signal to word line WL1 to turn on the first column of transistors. Since the drain of transistor N4_1 (i.e., node r4c2) is connected to ground line VSS, the high-level potential input to bit line BL4 is pulled down to a low potential; at this time, the stored data "0" in transistor N4_1 is read from bit line BL4.

[0084] It should be understood here that since a separate ground line VSS is set for the last row of transistors in the storage circuit, when reading the stored data in the last row of transistors, step 01 only needs to precharge all bit lines BL1, BL2, BL3, and BL4, without controlling the bit lines to be connected to the ground line VSS.

[0085] It should be noted that, since there is an electrical connection between the transistors in adjacent rows in the read-only memory circuit provided in this application embodiment, when reading stored data from a transistor located in a certain row (row x), while precharging the bit line BLx corresponding to the transistor in row x, it is also necessary to precharge all bit lines BL1, BL2, ..., BL(x-1) located before bit line BLx at the same time, so as to reduce the influence of bit lines BL1, BL2, ..., BL(x-1) on the voltage on bit line BLx (such as voltage fluctuation) and thus prevent the accurate reading of stored data.

[0086] Furthermore, to ensure accurate reading of the stored data in each row of transistors and to avoid the potential impact on subsequent bit lines caused by an excessive number of bit lines in the preceding row, in some possible implementations, the number of rows in the transistor array can be set to be less than or equal to 32, i.e., n ≤ 32. For illustration, n can be equal to 4, 8, 16, etc.

[0087] The following section, using the layout of the read-only memory circuit described above, further explains the inter-layer distribution of this circuit within the read-only memory. It should be understood that the circuit layout corresponds to the actual distribution of components, signal lines, etc., in the product.

[0088] like Figure 6As shown, taking a 4-row, 5-column transistor array as an example, when designing the layout of this read-only memory circuit, the source and drain of the transistor array can be set, and the intermediate connection line ML between the bit line BL, the ground line VSS, and the transistors in adjacent rows is located in the first metal layer M1; m bit lines BL and ground lines VSS are located in the second metal layer M1; the transistor array is distributed on the side of the first metal layer M1 away from the second metal layer M1, or in other words, the first metal layer M1 is located between the transistor array and the second metal layer M2.

[0089] It should be understood here that a transistor array comprises multiple film layers; for example, such as Figure 6 As shown, it may include an active layer OD (as the channel layer of the transistor), a polysilicon layer PO (as the gate layer of the transistor), etc.

[0090] refer to Figure 6 As shown, the bit line BL and ground line VSS located in the second metal layer M2 can extend along the row direction. In this case, each bit line can be set one-to-one with the position opposite the transistor in each row, that is, the i-th bit line is set to the position opposite the transistor in the i-th row.

[0091] Regarding the settings for the ground VSS, such as Figure 6 As shown, in some possible implementations, the ground line VSS can be positioned outside the last row (i.e., the 4th row) of transistors, meaning the ground line VSS is positioned on the side of bit line BL4 away from the transistor array (or BL3). For example... Figure 7 As shown, in some possible implementations, the ground line VSS and the bit line BL4 (the last bit line) can both be set to the position directly opposite the 4th row transistor (the last row transistor).

[0092] Additionally, refer to Figure 6 or Figure 7 As shown, the intermediate connection line ML located in the first metal layer M1 can extend in the reverse direction along the column. Furthermore, the intermediate connection line ML is electrically connected to the bit line BL and the ground line VSS via via VIA. It should be noted that the aforementioned memory circuit is an equivalent circuit diagram; some electrical connections in this memory circuit can be designed using equivalent connection methods during fabrication, for example... Figure 7 The drains of all transistors in the fourth column are directly connected to the ground line VSS via the intermediate connection line ML. This connection method is equivalent to the connection method in which the drains of the four transistors in the fourth column of the memory circuit are connected to the ground line in sequence.

[0093] In addition, one or more of the aforementioned read-only memory circuits can be set in the ROM. This application does not limit this, and it can be set as needed in practice.

[0094] It should be noted that the "directly opposite" mentioned in the above embodiments does not refer to absolute center-to-center. Taking the aforementioned ground line VSS and bit line BL4 located directly opposite the transistors in the fourth row as an example, it means that the projections of ground line VSS and bit line BL4 on the substrate overlap with the projections of the transistors in the fourth row. Of course, in practice, the size of the overlapping area can be specifically set to ensure that the area of ​​the memory cell is minimized while meeting design requirements.

[0095] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A read-only memory circuit, characterized in that, This includes transistor arrays, switching circuits, multiple word lines, multiple bit lines, and ground lines; The transistor array includes multiple transistors; wherein, in the transistor array: multiple transistors located in the same row are connected in series, the gates of multiple transistors located in the same column are connected to the same word line, and the multiple bit lines are respectively configured to correspond one-to-one with the transistors in different rows; The multiple bit lines are connected to the ground line through the switching circuit; The transistor array includes: a first transistor and a second transistor located in the same column and in two adjacent rows, respectively; The plurality of bit lines include a first bit line and a second bit line; the first bit line corresponds to a plurality of transistors in the row where the first transistor is located, and the second bit line corresponds to a plurality of transistors in the row where the second transistor is located; The first terminal of the first transistor is connected to the first bit line, the second terminal of the first transistor is connected to the second terminal of the second transistor, and the first terminal of the second transistor is connected to the second bit line.

2. The read-only memory circuit according to claim 1, characterized in that, The transistor array also includes a third transistor and a fourth transistor located in the same column and in two adjacent rows, respectively; The plurality of bit lines include a third bit line and a fourth bit line; the third bit line corresponds to a plurality of transistors in the row where the third transistor is located, and the fourth bit line corresponds to a plurality of transistors in the row where the fourth transistor is located; The first terminal of the third transistor is connected to the first terminal of the fourth transistor, and the second terminal of the third transistor is connected to the second terminal of the fourth transistor.

3. The read-only memory circuit according to claim 1 or 2, characterized in that, The plurality of bit lines includes a fifth bit line, which corresponds to the last row of transistors in the transistor array; The last row of transistors includes a fifth transistor; The first terminal of the fifth transistor is connected to the fifth bit line or the ground line; The second terminal of the fifth transistor is connected to the fifth bit line or the ground line.

4. The read-only memory circuit according to claim 1, characterized in that, The start or end of each of the multiple transistors arranged in series in each row of the transistor array is connected to the corresponding bit line.

5. The read-only memory circuit according to claim 1, characterized in that, The transistor array comprises n rows of transistors, wherein n is less than or equal to 32.

6. The read-only memory circuit according to claim 1, characterized in that, The transistors and the bit lines, the ground lines, and the intermediate connection lines between the transistors in adjacent rows are distributed in the first metal layer; The multiple bit lines and the ground lines are distributed in the second metal layer; The first metal layer is located between the plurality of transistors and the second metal layer; The bit line and the ground line extend along the row direction of the transistor array; The intermediate connection line extends along the column direction of the transistor array; The positions of the multiple bit lines are respectively aligned with the positions of the transistors in each row.

7. The read-only memory circuit according to claim 6, characterized in that, The ground wire is positioned directly opposite the position of the last row of transistors in the transistor array.

8. The read-only memory circuit according to claim 6, characterized in that, The bit line corresponding to the last row of transistors in the transistor array is the fifth bit line; The ground line is located on the side of the fifth bit line away from the transistor array.

9. A read-only memory, characterized in that, It includes a controller and a read-only memory circuit as described in any one of claims 1-8; the controller is connected to the read-only memory circuit.

10. An electronic device, characterized in that, It includes a printed circuit board and a read-only memory as described in claim 9; the read-only memory is connected to the printed circuit board.

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