A chip, power supply design method and related device

Abstract

Embodiments of the present application provide a chip, a power supply design method, and related devices. The chip includes: a first functional module with a higher target voltage and a second functional module with a lower target voltage, both using the same power domain; a first power-on unit that supplies power to the first functional module, the voltage of which is adjusted to the target voltage of the first functional module via the first power-on unit; and a second power-on unit that supplies power to the second functional module, the voltage of which is adjusted to the target voltage of the second functional module via the first power-on unit and the second power-on unit. The chip provided in the embodiment of the present application converts the voltage of the same power supply into different target voltages through different power-on units, and transmits the voltage to the corresponding functional modules requiring the target voltage. This avoids the functional modules requiring the lower target voltage from being connected to a higher voltage, which would otherwise cause excess power consumption. This reduces the overall power consumption of the chip and improves the rationality of the chip's power supply design.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to a chip, a power supply design method, and related devices. Background Art

[0002] Synchronous circuit design, with its numerous advantages, has become the mainstream design approach for digital chips. At the same time, with advancements in process technology and increased chip integration, multiple functional modules are being integrated within a chip. Consequently, chip design must consider the power supply design for these modules. In this context, improving the rationality of chip power supply design has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a chip, a power supply design method, and related devices to reduce the power consumption of the chip and improve the rationality of the power supply design of the chip.

[0004] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0005] An embodiment of the present application provides a chip, comprising: a first functional module and a second functional module using the same power domain, wherein a target voltage of the first functional module is higher than a target voltage of the second functional module;

[0006] a first power-on unit for supplying power to the first functional module, wherein the voltage of the power supply of the power domain is adjusted to a target voltage of the first functional module by the first power-on unit;

[0007] A second power-on unit for supplying power to the second functional module, wherein the voltage of the power supply is adjusted to a target voltage of the second functional module through the first power-on unit and the second power-on unit.

[0008] Optionally, it also includes: a first voltage region and a second voltage region sharing the same power domain, the voltage of the first voltage region being higher than that of the second voltage region; wherein the first functional module is a functional module in the first voltage region, and the second functional module is a functional module in the second voltage region.

[0009] Optionally, the first power-on unit is provided in the first voltage region, and the first power-on unit in the first voltage region connects the first functional module and the same power domain;

[0010] The second power-on unit is disposed in the second voltage region. The second power-on unit in the second voltage region connects the second functional module and the first power-on unit, and the first power-on unit is connected to the same power domain.

[0011] Optionally, the target voltage of the first functional module being higher than the target voltage of the second functional module comprises: a clock frequency of the first functional module being higher than a clock frequency of the second functional module. Optionally, the first power-on unit is connected to the power supply and the first functional module; the second power-on unit is connected to the second functional module and the first power-on unit, and the first power-on unit is connected to the power supply.

[0012] Optionally, the first power-on unit includes a first metal layer, the second power-on unit includes a second metal layer, and the first metal layer is different from the second metal layer.

[0013] Optionally, the distance between the first metal layer and the functional module of the chip is smaller than the distance between the second metal layer and the functional module of the chip.

[0014] Optionally, the first metal layer is arranged on a side close to the first functional module, and the second metal layer is arranged on a side away from the first functional module.

[0015] Optionally, the resistance of the first power-on unit is lower than the resistance of the second power-on unit.

[0016] Optionally, the metal line width of the first power-on unit is greater than the metal line width of the second power-on unit.

[0017] Optionally, the voltage drop between the first functional module and the power supply is less than a first ratio; the voltage drop between the second functional module and the power supply is less than a second ratio, and the first ratio is less than the second ratio.

[0018] Optionally, the method further includes: the first metal layer is provided with a first signal line, and the first signal line is connected to the plurality of the first functional modules;

[0019] The second metal layer is provided with a second signal line, the second signal line connects a plurality of the second functional modules, and the signal rate of the first signal line is higher than the signal rate of the second signal line.

[0020] Optionally, it further includes: a substrate; wherein the first functional module and the second functional module are arranged on the substrate; the first power-on unit and the second power-on unit are arranged in the substrate.

[0021] Optionally, the first metal layer and the second metal layer form a power supply network, the power supply network connects the power supply and the first functional module, and the power supply network connects the power supply and the second functional module.

[0022] The present invention also provides a power supply design method, including:

[0023] Divide the functional modules of the chip using the same power domain into a first functional module and a second functional module, wherein the target voltage of the first functional module is higher than the target voltage of the second functional module;

[0024] a first power-on unit configured to supply power to the first functional module, wherein the voltage of the power supply of the power domain is adjusted to a target voltage of the first functional module by the first power-on unit;

[0025] and a second power-on unit configured to supply power to the second functional module, wherein the voltage of the power supply is adjusted to a target voltage of the second functional module through the first power-on unit and the second power-on unit.

[0026] Optionally, the method further includes: dividing the chip into a first voltage region and a second voltage region, wherein the first voltage region is used to set the first functional module, and the second voltage region is used to set the second functional module;

[0027] A first power supply unit in the first voltage region connects the first functional module and a power supply, a second power supply unit in the second voltage region connects the second functional module and the first power supply unit, and the first power supply unit is connected to the power supply.

[0028] Optionally, the step of dividing the chip into a first voltage region and a second voltage region includes:

[0029] The physical area where the first functional module is located is defined as a first voltage area; the physical area where the second functional module is located is defined as a second voltage area; wherein the target voltage of the first voltage area is higher than the target voltage of the second voltage area.

[0030] Optionally, the method further includes: configuring, in the first power-on unit, a first signal line connected to a plurality of the first functional modules;

[0031] In the second power-on unit, a second signal line connected to a plurality of the second functional modules is configured, and a signal rate of the first signal line is higher than a signal rate of the second signal line.

[0032] Optionally, the method further includes: checking a setup time of the first voltage region according to a target voltage required by the first functional module;

[0033] checking a setup time of the second voltage region according to a target voltage required by the second functional module;

[0034] The holding times of the first voltage region and the second voltage region are checked according to the voltage of the power supply.

[0035] The present invention also provides a power supply design device, including:

[0036] a module division module, configured to divide functional modules of the chip using the same power domain into a first functional module and a second functional module, wherein a target voltage of the first functional module is higher than a target voltage of the second functional module;

[0037] a first power configuration module, configured to configure a first power-on unit for supplying power to the first functional module, wherein the voltage of the power supply of the power domain is adjusted to a target voltage of the first functional module by the first power-on unit;

[0038] The second power configuration module is used to configure a second power-on unit for supplying power to the second functional module, wherein the voltage of the power supply is adjusted to a target voltage of the second functional module through the first power-on unit and the second power-on unit.

[0039] An embodiment of the present application also provides a design device, comprising at least one memory and at least one processor, wherein the memory stores a design program of a chip, and the processor calls the design program to execute the power supply design method as described above.

[0040] An embodiment of the present application further provides a storage medium, which stores a design program for a chip, and when the design program is executed, the power supply design method as described above is implemented.

[0041] An embodiment of the present application also provides a computer device, comprising the chip described above.

[0042] The chip provided in the embodiment of the present application uses functional modules of the same power domain, which are divided into a first functional module and a second functional module according to the target voltage required for their operation, wherein the target voltage of the first functional module is higher than the target voltage of the second functional module; in order to provide different voltages for different functional modules while using the same power supply, the embodiment of the present application respectively provides a first power-on unit for powering the first functional module and a second power-on unit for powering the second functional module in the chip; wherein the voltage of the power supply of the power domain is adjusted to the target voltage of the first functional module through the first power-on unit; the voltage of the power supply is adjusted to the target voltage of the second functional module through the first power-on unit and the second power-on unit.

[0043] As can be seen, by dividing the functional modules according to the target voltages they require when operating, different power-on units can be used to connect the functional modules with different target voltages when connecting them to the power supply. The power-on units then convert the power supply voltage to the target voltage required by the functional modules, making the power supply design of the functional modules more rational, improving the rationality of the chip's power supply design, and reducing the chip's power consumption. That is, by using different power-on units to convert the voltage of the same power supply to different target voltages and transmit them to the corresponding functional modules requiring the target voltage, this avoids the situation where the functional modules requiring lower target voltages are connected to higher voltages, which would result in unnecessary power consumption. This reduces the overall power consumption of the chip and improves the rationality of the chip's power supply design. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0045] Figure 1 A schematic diagram of the structure of a chip and the circuit board on which it is located;

[0046] Figure 2 This is a schematic diagram of a power supply structure within a chip;

[0047] Figure 3 A schematic diagram of the structure of the chip provided in the embodiment of the present application;

[0048] Figure 4 A schematic diagram of the structure of the power supply routing within the chip provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of the hierarchical structure of a chip provided in an embodiment of the present application;

[0050] Figure 6 A flowchart of a power supply design method provided in an embodiment of the present application;

[0051] Figure 7 A schematic diagram of the structure of a power supply design device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] Synchronous circuit design has become the mainstream design method for digital chips due to its many advantages. At the same time, with the advancement of technology and the improvement of chip integration, multiple functional modules are integrated into the chip. Therefore, when designing the chip, it is necessary to consider the power supply design of multiple functional modules in the chip to achieve lower power consumption and a simpler power supply design, which puts higher requirements on chip design.

[0054] A chip design approach simplifies the chip's power supply design by reducing the number of power supplies. For example, a single chip power supply can simultaneously power multiple functional modules with similar voltage requirements. This power supply must comprehensively consider the voltage requirements of these modules. Furthermore, when considering the impact of voltage drop within the chip, the same maximum voltage drop requirement must be set for each functional module to ensure that the target voltage of all functional modules is greater than the same preset voltage.

[0055] In one example, if Figure 1 As shown, a power supply 2 and a chip 3 are provided on a circuit board 1. The circuit board can be regarded as a mainboard on which the power supply and chip are provided. The chip 3 can include a substrate 4 and a bare die 5 provided on the substrate 4. The bare die can be regarded as the basic component unit of a chip, such as an independent silicon wafer or wafer. A chip can be composed of one or more bare dies. A variety of functional modules 6 are provided within the bare die. The functional modules are used to implement specific functions and can be composed of electronic components (such as transistors, resistors, capacitors, etc.) that implement specific functions.

[0056] exist Figure 1 As shown, the power supply 2 uses copper wire (or other conductive media) to supply power to the chip 3 through the circuit board 1 and the substrate 4, for example, to supply power to the bare die 5 in the chip 3, so that the functional modules of the chip can operate normally.

[0057] The path from power source 2 to die 5 in chip 3 can be called an off-die power supply path. Since resistance, capacitance, and inductance are unavoidable in the off-die power supply path, voltage loss occurs in the off-die power supply path. It should be noted that due to voltage loss in the power supply path, voltage drops occur between multiple nodes in the off-die power supply path. Figure 1 As shown, assuming that the output voltage of the power supply 2 is V1, the voltage at the connection between the circuit board 1 and the substrate 4 is V2, and the voltage at the connection between the substrate 4 and the bare chip 5 is V3, then V1>V2>V3 exists.

[0058] Furthermore, there is also voltage loss in the die of the chip. In one example, the power supply path in the die of the chip is as shown in the following figure. Figure 2 As shown in FIG, the bump 21 in the die is connected to the substrate, and the bump 21 transmits the current to the functional modules 23 at the bottom of the chip through the power mesh 22 in the die, wherein the power mesh 22 can be implemented by the metal layer in the substrate 4. Since the power supply path in the die inevitably has resistance, capacitance and inductance, the power supply path in the die also has voltage loss, that is, it causes voltage drops between multiple nodes in the power supply path in the die. For example, in the die of the chip, the voltage along the Figure 2 The A direction in the middle gradually decreases. Figure 2 As shown in the figure, assuming the voltage at the connection between bump 21 and power network 22 is V4, and the voltage at the connection between power network 22 and functional module 23 is V5, then V3 (V3 is the voltage at the connection between substrate 4 and die 5) > V4 > V5. This shows that due to the voltage drops between multiple nodes in the power supply path, the voltage V5 received by the functional module within the die is lower than the voltage V1 output by power supply 2 on the circuit board.

[0059] The higher the threshold voltage, the lower the device flip speed, that is, the greater the device delay and the worse the device performance. Usually, the lower the voltage of the functional module in the chip die, the lower the power consumption of the functional module. To reduce the power consumption of the chip, it is necessary to reduce the voltage of the functional module as much as possible while ensuring the normal operation of the devices in the chip die.

[0060] According to the aforementioned chip design method, multiple functional modules share the same power supply, and the voltages of each functional module also fall within the same voltage range. However, different functional modules have different voltage requirements. To ensure that each functional module can function properly, the chip's power supply voltage and chip voltage drop can be designed based on the functional module with the highest voltage amplitude requirement. However, because it is difficult to accurately design the power supply voltage and chip voltage drop based on the voltage requirements of each functional module, if functional modules with different voltage requirements are uniformly designed to use the same voltage, the chip's power consumption will increase.

[0061] Based on this, the embodiments of the present application consider setting up multiple power supply paths within the chip so that a single power supply can provide appropriate voltages to functional modules requiring different voltages through different power supply paths, thereby reducing the voltage supplied to functional modules with lower target voltages, thereby reducing the power consumption of the chip.

[0062] Based on the above ideas, the embodiment of the present application provides a new chip solution as an optional implementation. Figure 3 An example diagram of a chip provided in an embodiment of the present application is shown. Figure 3 As shown, the chip may include:

[0063] The first functional module 31 and the second functional module 32 use the same power domain. The target voltage required by the first functional module 31 is higher than the target voltage required by the second functional module 32. There can be multiple first functional modules 31 and second functional modules 32.

[0064] Furthermore, in an optional implementation, the chip provided in the present application also includes: a first voltage region and a second voltage region that share the same power domain, the voltage of the first voltage region being higher than that of the second voltage region; wherein the first functional module is a functional module in the first voltage region, and the second functional module is a functional module in the second voltage region.

[0065] Furthermore, in an optional implementation, the first power-on unit is set in the first voltage area, and the first power-on unit in the first voltage area connects the first functional module and the same power domain; the second power-on unit is set in the second voltage area, and the second power-on unit in the second voltage area connects the second functional module and the first power-on unit, and the first power-on unit is connected to the same power domain.

[0066] In an optional implementation, the flipping speed of the first functional module is higher than the flipping speed of the second functional module, and thus the target voltage required by the first functional module is higher than the target voltage required by the second functional module. In one example, the flipping speed of the first functional module is higher than the flipping speed of the second functional module, and the clock frequency of the first functional module is higher than the clock frequency of the second functional module, and thus the target voltage required by the first functional module is higher than the target voltage required by the second functional module. It should be noted that the clock frequency of a functional module with higher performance is higher, resulting in a faster flipping speed, and thus the target voltage of the functional module with higher performance is higher; the clock frequency of a functional module with lower performance is lower, resulting in a slower flipping speed, and thus the target voltage of the functional module with lower performance is lower.

[0067] Specifically, since the power supply voltage is fixed within the chip and voltage consumption exists between various parts of the chip, the design rule of the power supply network within the chip is: the voltage relationship between different connections within the chip.

[0068] In one example, the clock frequency of the first functional module is higher than the clock frequency of the second functional module. Figure 2The first functional module 31 has a higher clock frequency, requiring it to flip at a faster speed, resulting in higher dynamic power consumption. Therefore, the first functional module 31 requires a higher target voltage. The second functional module 32 has a lower clock frequency, resulting in a slower flipping speed than the first functional module. Therefore, the second functional module 32 requires a lower target voltage. Since the first and second functional modules 31 and 32 are both powered by the same power supply, without considering the differences in the power supply path design for different functional modules on the circuit board and substrate, it is assumed that the voltages at the bump 21 and the power network 22 of the first and second functional modules are the same, that is, VH4 = VL4.

[0069] After comprehensively considering the power supply design and the voltage requirements of the functional modules, if the voltage required by the first functional module 31 is VH5 and the voltage required by the second functional module 32 is VL5, we can know that since VH4=VL4, and VH4>VH5, VL4>VL5, and since the target voltage required by the first functional module 31 is greater than the target voltage required by the second functional module 32, that is, VH5>VL5, it is possible to control the voltage loss caused by the power supply network and control the voltage drop from the power supply to the functional module, so that the power supply voltage drops to the target voltage required by different functional modules after passing through the power supply network. That is, a power-on unit for voltage drop processing can be set between the power supply and the functional module, and the power supply network can be realized by the power-on unit. The functional module is powered by the power supply network realized by the power-on unit, so that the voltage of the power supply is adjusted to the target voltage required by the functional module.

[0070] It should be noted that, in actual production and manufacturing, reference may be made to the design principles of the power supply network within the chip to perform differentiated processing on the paths between the first functional module and the second functional module and the power supply.

[0071] Please continue to refer to Figure 3 The chip provided in this application also includes: a first power-on unit 311 for supplying power to the first functional module 31 , wherein the voltage of the power supply is adjusted to the target voltage of the first functional module 31 through the first power-on unit 311 .

[0072] A second power-on unit 321 supplies power to the second functional module 32 , wherein the voltage of the power supply is adjusted to a target voltage of the second functional module 32 through the first power-on unit 311 and the second power-on unit 321 .

[0073] Furthermore, when the power supply networks of the first functional module and the second functional module are designed according to different requirements, the voltage drop of the power supply network of the first functional module needs to be less than VH4-VH5+VM, and the voltage drop of the power supply network of the second functional module needs to be less than VL4-VL5+VM, where VM is the reserved voltage drop margin. That is, in an optional embodiment, the voltage drop between the first functional module and the power supply is less than a first ratio; the voltage drop between the second functional module and the power supply is less than a second ratio, and the first ratio is less than the second ratio. For example, if the power supply voltage is 0.9V, the voltage drop between the first functional module and the power supply is less than the first ratio, which can mean that the voltage drop between the first functional module and the power supply is less than 5% (i.e., the first ratio is 5%), i.e., the voltage between the first functional module and the power supply is greater than 0.85V, and the second ratio of the second functional module is less than 15%, i.e., the voltage between the second functional module and the power supply is greater than 0.75V.

[0074] In this way, the functional modules are divided according to the target voltages they require when operating. This allows different power-on units to be used for connecting the functional modules to the power supply, thereby converting the power supply voltage to the target voltage required by the functional modules through the power-on units. This allows for a more rational power supply design for the functional modules, improves the rationality of the chip's power supply design, and reduces chip power consumption. Specifically, different power-on units convert the voltage of the same power supply to different target voltages and transmit them to the corresponding functional modules requiring the target voltages. This prevents functional modules requiring lower target voltages from being connected to higher voltages, which would otherwise cause excess power consumption. This reduces the overall power consumption of the chip and improves the rationality of the chip's power supply design.

[0075] In an optional implementation, the chip structure provided in the embodiment of the present application is similar to Figure 1 The chips shown can be the same, wherein the functional modules are the same as Figure 1 Correspondingly, in an optional embodiment, as shown in FIG. Figure 3 As shown, the chip provided in this embodiment of the present application further includes: a substrate 4; wherein the first functional module 31 and the second functional module 32 are disposed on the substrate; and the first power supply unit 311 and the second power supply unit 321 are disposed within the substrate. It should be noted that when the power supply capacity of the first power supply unit 311 is insufficient to support the operation of the first functional module, as an optional implementation, the second power supply unit 321 can also assist in powering the first functional module.

[0076] In an implementation example, Figure 4 As shown, Figure 4Schematic diagram of the structure of the first power-on unit and the second power-on unit, wherein the first power-on unit is a group of power supply lines, and the second power-on unit is another group of power supply lines, wherein a group of power supply lines may include multiple power supply lines. Figure 4 Each line in FIG. 4 represents a power supply trace 40 . Figure 4 , power supply lines arranged in the same direction belong to the same group of power supply lines and correspond to the same power-on unit. For example, all horizontal power supply lines are in the same power-on unit, and all vertical power supply lines are in the same power-on unit. For example, the horizontal power supply lines are in the first power-on unit, and the vertical power supply lines are in the second power-on unit. One end of the power supply line is connected to the power supply of the power domain, and the other end is connected to the first functional module or the second functional module. The first power-on unit can be connected to the power supply of the power domain through the power supply line in the first power unit, and the second power unit is connected to the power supply of the power domain through the power supply lines in the first power unit and the second power unit at the same time.

[0077] In an optional embodiment, the first power supply unit connects the power supply and the first functional module; the second power supply unit connects the second functional module and the first power supply unit, and the first power supply unit is connected to the power supply. By connecting the power supply and the first or second functional module via different power supply units, the voltage delivered from the power supply to the first or second functional module can be adjusted by adjusting the resistance of the power supply traces of the power supply units.

[0078] Furthermore, since the target voltage of the first functional module using the same power domain is higher than the target voltage of the second functional module, in order to make the voltage transmitted to the first functional module greater than the voltage transmitted to the second functional module, in an optional embodiment, the resistance of the first power-on unit is lower than the resistance of the second power-on unit.

[0079] It should be noted that for the voltage transmitted to the first functional module, the resistance in its transmission path is the resistance of the first power-on unit; for the voltage transmitted to the second functional module, the resistance in its transmission path is the resistance of the second power-on unit and the resistance of the first power-on unit combined. Since the resistance of the second functional module is larger, the resistance of the second power-on unit and the resistance of the first power-on unit combined is greater than the resistance of the first power-on unit.

[0080] Further, in an optional embodiment, the first power-on unit includes a first metal layer, the second power-on unit includes a second metal layer, and the first metal layer is different from the second metal layer.

[0081] It should be noted that in the chip structure, the power supply lines can be set in the metal layer, and due to the Figure 4As shown in the figure, the projections of the power supply lines in the first power-on unit and the power supply lines in the second power-on unit are intertwined. To avoid contact between the intertwined power supply lines and causing a chip short circuit, the first power-on unit and the second power-on unit need to be two different metal layers.

[0082] Based on the above “the power supply network 22 can be realized by the metal layer in the substrate 4”, in an optional implementation, the first metal layer and the second metal layer form a power supply network, the power supply network connects the power supply and the first functional module, and the power supply network connects the power supply and the second functional module.

[0083] Furthermore, since the widths of the metal layers in the chip are equal and the density of the power supply lines inside the metal layers can also be set to be equal, the resistance difference between different metal layers is determined by the metal wire widths of the different metal layers. It should be noted that, under the premise that the materials, lengths and widths of different conductors are equal, the larger the metal wire width of the conductor through which the current flows, the smaller the resistance. Therefore, in order to ensure that the resistance of the first power-on unit is smaller, in an optional embodiment, the metal wire width of the first power-on unit is greater than that of the second power-on unit.

[0084] It should be noted that the first metal layer can be a metal layer within the chip that is closer to the chip's functional modules, also known as a high-level metal layer, and the second metal layer can be a metal layer that is farther from the chip's functional modules, also known as a mid-low metal layer. That is, the distance between the high-level metal layer and the chip's functional modules is smaller than the distance between the mid-low metal layer and the chip's functional modules. In an optional embodiment, the first metal layer 51 is disposed on a side close to the first functional module 31, and the second metal layer 52 is disposed on a side away from the first functional module 31.

[0085] Based on the characteristics of the chip manufacturing process, the thickness of the high-level metal layer can be greater than the thickness of the middle and low-level metal layers. Figure 5 As shown, within the semiconductor chip substrate 4, the metal line width of the upper metal layer (i.e., the metal line width of the first metal layer 51) close to the chip's first functional module 31 is greater than the metal line width of the middle and lower metal layers (i.e., the metal line width of the second metal layer 52) farther from the chip's first functional module 31. This ensures that the thickness of the upper metal layer is greater than that of the middle and lower metal layers. Furthermore, because the metal line width of the first metal layer 51 is greater than that of the second metal layer 52, the resistance of the first energized unit can be ensured to be less than that of the second energized unit.

[0086] Furthermore, during the actual chip production process, to facilitate chip manufacturing and the placement of power supply traces, the metal layer covered by the projection of the functional module can be used as a power supply unit for connecting to the power supply. For example, the first functional module can use all of the first power supply units covered by the projection of the first functional module to connect to the power supply. Because the voltage drop requirements for the second functional module are more relaxed, the power supply network for the second functional module can be implemented by using a portion of the first power supply units covered by the projection of the second functional module in conjunction with a portion of the second power supply units covered by the projection of the second functional module. Since the first power supply units covered by the projection of the second functional module cannot be fully utilized in this case, in order to improve the utilization rate of the first power supply units, signal traces can be set within the first power supply units covered by the projection of the second functional module to connect multiple first functional modules. The signal traces used to connect multiple second functional modules are still set within the second power supply units covered by the projection of the second functional module.

[0087] Accordingly, in an optional embodiment, as Figure 3 As shown, in the chip provided by an embodiment of the present application, the first power-on unit 311 (for example, the first metal layer) is provided with a first signal line 312, and the first signal line 312 connects multiple first functional modules 31; the second power-on unit 321 (for example, the second metal layer) is provided with a second signal line 322, and the second signal line 322 connects multiple second functional modules 32, and the signal rate of the first signal line 312 is higher than the signal rate of the second signal line 322.

[0088] It should be noted that the power supply network is implemented by a power-on unit, and the power-on unit is implemented by a metal layer. The metal layer includes a high-level metal layer and a middle-level metal layer. The signal line is set in the metal layer.

[0089] It should be noted that the first signal routing 312 has a high requirement for delay, and the transmission delay needs to be reduced as much as possible to ensure the design performance. The first power-on unit 311 is used for wiring. Since the signal attenuation is small, fewer relay modules need to be added for signal transmission, so the overall delay when transmitting the signal is also lower.

[0090] The chip provided in the embodiment of the present application, through the power supply of the chip designed by the power supply design method provided in the present application, divides the functional modules according to the target voltage required by the functional modules when they are operating, so that when connecting the functional modules and the power supply, different power-on units can be used to connect the functional modules with different target voltages, so that the voltage of the power supply is converted to the target voltage required by the functional modules by the power-on units, making the power supply design of the functional modules more reasonable, improving the rationality of the power supply design of the chip, and reducing the power consumption of the chip. Furthermore, by utilizing the different widths of metal lines in different metal layers within the chip, the power supply lines between the functional modules and the power supply are reasonably arranged, thereby achieving the purpose of avoiding the high voltage connected to the functional modules with lower target voltages and causing unnecessary power consumption without introducing more devices or changing the chip structure. In addition, multiple signal routings can be additionally arranged, reducing the overall power consumption of the chip and improving the rationality of the power supply design of the chip.

[0091] The present application also provides a power supply design method, which can achieve the different target voltages required by different functional modules in the chip described above. Figure 6 Shown, including:

[0092] Step S10: dividing the functional modules of the chip using the same power domain into a first functional module and a second functional module, wherein the target voltage of the first functional module is higher than the target voltage of the second functional module.

[0093] Step S21: configuring a first power-on unit for supplying power to the first functional module, wherein the voltage of the power supply of the power domain is adjusted to a target voltage of the first functional module by the first power-on unit.

[0094] Step S22: configuring a second power-on unit for supplying power to the second functional module, wherein the voltage of the power supply is adjusted to a target voltage of the second functional module through the first power-on unit and the second power-on unit.

[0095] In this way, the power supply of the chip designed by the power supply design method provided by the present application divides the functional modules according to the target voltages required by the functional modules during operation. Therefore, when connecting the functional modules and the power supply, different power-on units can be used to connect the functional modules with different target voltages. The power-on units convert the voltage of the power supply to the target voltage required by the functional modules, making the power supply design of the functional modules more reasonable, improving the rationality of the chip power supply design, and reducing the power consumption of the chip. That is, the voltage of the same power supply is converted to different target voltages by different power-on units and transmitted to the corresponding functional modules requiring the target voltage, thereby avoiding the need for a lower target voltage.

[0096] Further, such as Figure 6 As shown, in one embodiment, the power supply design method provided in the present application further includes step S31 in the step S10 and the step S21: dividing the chip into a first voltage region and a second voltage region, the first voltage region being used to set the first functional module, and the second voltage region being used to set the second functional module.

[0097] The method further includes step S32 between step S22 and step S41: connecting a first power-on unit in the first voltage region to the first functional module and a power supply, connecting a second power-on unit in the second voltage region to the second functional module and the first power-on unit, and connecting the first power-on unit to the power supply.

[0098] By concentrating the first functional module and the second functional module in different areas, the functional modules with different voltage requirements in the chip can be more concentrated, which facilitates the design and arrangement of power supply lines in the chip and avoids additional power consumption caused by complex circuits.

[0099] Furthermore, the functional modules and voltage regions can be divided not only into the first and second parts, but also into more functional modules and voltage regions by refining the functional module and voltage region rules according to the chip design requirements. For example, based on the voltage value required by a specific functional module, the functional module can be divided into a 0.85V functional module, a 0.8V functional module, and a 0.75V functional module, and the voltage region can be divided into a 0.85V region, a 0.8V region, and a 0.75V region.

[0100] Further, such as Figure 6 As shown, in a specific embodiment, the power supply design method provided in the present application further includes step S41: configuring a first signal line connecting a plurality of the first functional modules in the first power-on unit.

[0101] Step S42 configures, in the second power-on unit, a second signal line connecting a plurality of the second functional modules, wherein the signal rate of the first signal line is higher than the signal rate of the second signal line.

[0102] Further, such as Figure 6 As shown, in an optional implementation, the power supply design method provided in the present application further includes step S51: checking the establishment time of the first voltage region according to the voltage required by the first functional module;

[0103] S52: Checking the establishment time of the second voltage region according to the voltage required by the second functional module;

[0104] S53: Checking the holding time of the first voltage region and the second voltage region according to the power supply voltage.

[0105] Furthermore, in an optional implementation, the performance of the first functional module is higher than that of the second functional module. Based on the difference in performance between the first functional module and the second functional module, the physical area where the first functional module is located can be designated as a first voltage area, and the physical area where the second functional module is located can be designated as a second voltage area; wherein the voltage of the first voltage area is higher than the voltage of the second voltage area.

[0106] It's important to note that after a chip's power supply is designed or manufactured, the setup and hold times must be checked to ensure circuit stability. The setup time is the minimum time the input voltage must remain stable before the internal clock edge of the chip arrives; the hold time is the minimum time the input voltage must remain stable after the internal clock edge arrives. Only after confirming that the setup and hold times meet the requirements can stable timing relationships within the chip be guaranteed.

[0107] The power supply design method provided in the embodiment of the present application divides the functional modules according to the target voltage required when the functional modules are working, so that when connecting the functional modules and the power supply, different power-on units can be used to connect the functional modules with different target voltages, so that the voltage of the power supply is converted into the target voltage required by the functional modules through the power-on units, so that the power supply design of the functional modules can be more reasonable, the rationality of the power supply design of the chip is improved, and the power consumption of the chip can be reduced. That is, the voltage of the same power supply is converted into different target voltages through different power-on units and transmitted to the corresponding functional modules that require the target voltage. Further, by utilizing the different characteristics of the metal wire widths of different metal layers in the chip, the power supply lines between the functional modules and the power supply are reasonably set, so that without introducing more devices or changing the chip structure, the purpose of avoiding the high voltage connected to the functional modules with lower target voltages and causing unnecessary power consumption is achieved. In addition, multiple signal routings can be additionally set to reduce the overall power consumption of the chip and improve the rationality of the power supply design of the chip.

[0108] This application also provides a power supply design device, such as Figure 7 Shown, including:

[0109] A module division module 71 is configured to divide the functional modules of the chip using the same power domain into a first functional module and a second functional module, wherein the target voltage of the first functional module is higher than the target voltage of the second functional module;

[0110] A first power configuration module 72 is configured to configure a first power supply unit for supplying power to the first functional module, wherein the voltage of the power supply of the power domain is adjusted to a target voltage of the first functional module by the first power supply unit;

[0111] The second power configuration module 73 is used to configure a second power supply unit for supplying power to the second functional module, wherein the voltage of the power supply is adjusted to the target voltage of the second functional module through the first power supply unit and the second power supply unit.

[0112] In this way, the power supply of the chip designed by the power supply design device provided by the present application divides the functional modules into multiple categories with similar target voltages according to the target voltages required by the functional modules during operation. This allows different power-on units to be used for connecting the functional modules to the power supply according to the different categories of functional modules. The power-on units then convert the voltage of the power supply to the target voltage required by the functional modules, thereby avoiding the situation where all functional modules have the same voltage, thereby reducing the power consumption of the chip. In other words, by using different power-on units to convert the voltage of the same power supply into different voltages and transmit them to the functional modules, the voltage of the functional modules with lower target voltages is avoided, thereby avoiding the situation where the functional modules with lower target voltages are connected to higher voltages, which would cause unnecessary power consumption. This reduces the overall power consumption of the chip and improves the rationality of the chip power supply design.

[0113] Further, such as Figure 7 As shown, in a specific embodiment, the power supply design device provided by the present application further includes:

[0114] A region division module 74, configured to divide the chip into a first voltage region and a second voltage region, wherein the first voltage region is used to set the first functional module, and the second voltage region is used to set the second functional module;

[0115] The power connection module 75 is used to connect the first power-on unit in the first voltage range to the first functional module and the power supply, and to connect the second power-on unit in the second voltage range to the second functional module and the first power-on unit, and the first power-on unit is connected to the power supply.

[0116] Further, such as Figure 7 As shown, in a specific embodiment, the power supply design provided by this application

[0117] The device also includes:

[0118] a first signal routing module 76 , configured to connect a first signal routing of the second power-on unit to a plurality of the first functional modules;

[0119] The second signal routing module 77 is configured to connect the second signal routing of the second power-on unit to the plurality of second functional modules. The signal rate of the first signal routing is higher than the signal rate of the second signal routing.

[0120] Further, such as Figure 7As shown, in a specific embodiment, the power supply design device provided by the present application further includes:

[0121] A first setup time checking module 78, configured to check the setup time of the first voltage region according to the voltage required by the first functional module;

[0122] A second setup time checking module 79, configured to check the setup time of the second voltage region according to the voltage required by the second functional module;

[0123] The first holding time checking module 80 is configured to check the holding time of the first voltage region according to the voltage required by the first functional module.

[0124] The second holding time checking module 81 is configured to check the holding time of the second voltage region according to the voltage required by the second functional module.

[0125] It should be noted that the requirements for the setup time and the hold time are related to the target voltage of the functional module being tested. Therefore, the setup time and hold time of the first functional module and the second functional module need to be checked using different standards respectively. Specifically, the setup time of the first voltage region is checked using the voltage VH5 mentioned above as the standard, and the hold time of the first voltage region is checked using the voltage VH4 as the standard; the setup time of the second voltage region is checked using the voltage VL5 mentioned above as the standard, and the hold time of the second voltage region is checked using the voltage VL4 as the standard. In particular, when the design differences of the power supply paths of different functional modules of the circuit board and the chip substrate are not taken into account, VH4 = VL4, so the hold time check standards may be the same.

[0126] The power supply design device provided in the embodiments of the present application divides the functional modules into multiple categories with similar target voltages based on the target voltages required by the functional modules during operation. This allows different power-on units to be used when connecting the functional modules to the power supply, and the power-on units convert the voltage of the power supply to the target voltage required by the functional modules. This avoids the situation where all functional modules in the designed chip have the same voltage, thereby reducing the power consumption of the chip. Furthermore, by utilizing the different widths of metal lines in different metal layers within the chip, the power supply lines between the functional modules and the power supply are rationally arranged. This avoids the situation where functional modules with lower target voltages are connected to higher voltages, which would otherwise cause excessive power consumption, without introducing more components or changing the chip structure. Furthermore, multiple signal routings can be additionally provided, reducing the overall power consumption of the chip and improving the rationality of the chip's power supply design.

[0127] An embodiment of the present application also provides a design device, comprising at least one memory and at least one processor, wherein the memory stores a design program of a chip, and the processor calls the design program to execute the power supply design method described above.

[0128] An embodiment of the present application further provides a storage medium, which stores a design program for a chip, and when the design program is executed, implements the power supply design method described above.

[0129] An embodiment of the present application also provides a computer device, comprising the chip described above.

[0130] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A chip, characterized in that: include: A first functional module and a second functional module using the same power domain, wherein a target voltage of the first functional module is higher than a target voltage of the second functional module; a first power-on unit for supplying power to the first functional module, wherein the voltage of the power supply of the power domain is adjusted to a target voltage of the first functional module by the first power-on unit; a second power-on unit for supplying power to the second functional module, wherein the voltage of the power supply is adjusted to a target voltage of the second functional module through the first power-on unit and the second power-on unit; It also includes: a first voltage region and a second voltage region that share the same power domain, wherein the first functional module is a functional module in the first voltage region, the second functional module is a functional module in the second voltage region, the first power-on unit is set in the first voltage region, and the second power-on unit is set in the second voltage region.

2. The chip according to claim 1, wherein: The voltage in the first voltage region is higher than that in the second voltage region.

3. The chip according to claim 2, wherein: A first power-on unit in the first voltage region connects the first functional module and the same power domain; The second power-on unit in the second voltage region connects the second functional module and the first power-on unit, and the first power-on unit is connected to the same power domain.

4. The chip according to claim 1, wherein That the target voltage of the first functional module is higher than the target voltage of the second functional module includes: a clock frequency of the first functional module is higher than the clock frequency of the second functional module.

5. The chip according to claim 1, wherein: The first power-on unit is connected to the power supply and the first functional module; the second power-on unit is connected to the second functional module and the first power-on unit, and the first power-on unit is connected to the power supply.

6. The chip according to claim 1, wherein: The first power-on unit includes a first metal layer, and the second power-on unit includes a second metal layer, where the first metal layer is different from the second metal layer.

7. The chip according to claim 6, wherein: The distance between the first metal layer and the functional module of the chip is smaller than the distance between the second metal layer and the functional module of the chip.

8. The chip according to claim 6, wherein: The first metal layer is disposed on a side close to the first functional module, and the second metal layer is disposed on a side away from the first functional module.

9. The chip according to any one of claims 1 to 8, wherein: The resistance of the first power-on unit is lower than the resistance of the second power-on unit.

10. The chip according to claim 9, wherein: The metal line width of the first power-on unit is greater than the metal line width of the second power-on unit.

11. The chip according to any one of claims 1 to 8, wherein: The voltage drop between the first functional module and the power supply is less than a first ratio; the voltage drop between the second functional module and the power supply is less than a second ratio, and the first ratio is less than the second ratio.

12. The chip according to claim 6, wherein: The first metal layer is provided with a first signal line, and the first signal line is connected to the plurality of first functional modules; The second metal layer is provided with a second signal line, the second signal line connects a plurality of the second functional modules, and the signal rate of the first signal line is higher than the signal rate of the second signal line.

13. The chip according to any one of claims 1 to 8, wherein: Also includes: substrate; The first functional module and the second functional module are arranged on the substrate; the first power-on unit and the second power-on unit are arranged in the substrate.

14. The chip according to claim 6, wherein: The first metal layer and the second metal layer form a power network, the power network connects the power supply and the first functional module, and the power network connects the power supply and the second functional module.

15. A power supply design method, characterized in that: include: Divide the functional modules of the chip using the same power domain into a first functional module and a second functional module, wherein the target voltage of the first functional module is higher than the target voltage of the second functional module; a first power-on unit configured to supply power to the first functional module, wherein the voltage of the power supply of the power domain is adjusted to a target voltage of the first functional module by the first power-on unit; and a second power-on unit configured to supply power to the second functional module, wherein the voltage of the power supply is adjusted to a target voltage of the second functional module through the first power-on unit and the second power-on unit; Also includes: The chip is divided into a first voltage region and a second voltage region, the first voltage region is used to set the first functional module, and the second voltage region is used to set the second functional module; wherein the first power-on unit is located in the first voltage region, and the second power-on unit is located in the second voltage region.

16. The power supply design method according to claim 15, wherein: Also includes: A first power supply unit in the first voltage region connects the first functional module and a power supply, a second power supply unit in the second voltage region connects the second functional module and the first power supply unit, and the first power supply unit is connected to the power supply.

17. The power supply design method according to claim 16, wherein: The step of dividing the chip into a first voltage region and a second voltage region comprises: The physical area where the first functional module is located is defined as a first voltage area; the physical area where the second functional module is located is defined as a second voltage area; wherein the target voltage of the first voltage area is higher than the target voltage of the second voltage area.

18. The power supply design method according to claim 15, wherein: Also includes: In the first power-on unit, a first signal line connected to the plurality of the first functional modules is configured; In the second power-on unit, a second signal line connected to a plurality of the second functional modules is configured, and a signal rate of the first signal line is higher than a signal rate of the second signal line.

19. The power supply design method according to claim 16, wherein: Also includes: checking a setup time of the first voltage region according to a target voltage required by the first functional module; checking a setup time of the second voltage region according to a target voltage required by the second functional module; The holding times of the first voltage region and the second voltage region are checked according to the voltage of the power supply.

20. A power supply design device, characterized in that: include: a module division module, configured to divide functional modules of the chip using the same power domain into a first functional module and a second functional module, wherein a target voltage of the first functional module is higher than a target voltage of the second functional module; a first power configuration module, configured to configure a first power-on unit for supplying power to the first functional module, wherein the voltage of the power supply of the power domain is adjusted to a target voltage of the first functional module by the first power-on unit; a second power configuration module, configured to configure a second power-on unit for supplying power to the second functional module, wherein the voltage of the power supply is adjusted to a target voltage of the second functional module through the first power-on unit and the second power-on unit; Also includes: A region division module is used to divide the chip into a first voltage region and a second voltage region, the first voltage region is used to set the first functional module, and the second voltage region is used to set the second functional module; wherein the first power-on unit is located in the first voltage region, and the second power-on unit is located in the second voltage region.

21. A design device, characterized in that The method comprises at least one memory and at least one processor, wherein the memory stores a design program of a chip, and the processor calls the design program to execute the power supply design method according to any one of claims 15 to 19.

22. A storage medium, characterized in that The storage medium stores a design program of the chip, and when the design program is executed, the power supply design method according to any one of claims 15 to 19 is implemented.

23. A computer device, characterized in that: Comprising the chip according to any one of claims 1 to 14.

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