Interface circuit with robust electrostatic discharge

Abstract

An ESD protection circuit has a driver transistor having a drain coupled to an input / output (I / O) pad of an IC device and a source coupled to a first rail of a power supply in the IC device, and a diode coupling the I / O pad to the first rail and configured to be reverse-biased when a rated voltage is applied to the I / O pad. The ESD protection circuit has a gate pull-up transistor coupling a gate of the driver transistor to the I / O pad or the first rail. The gate pull-up transistor can be configured to present a high impedance path between the gate of the driver transistor and the I / O pad or the first rail when the rated voltage is applied to the I / O pad, and to present a low impedance path when an overvoltage signal is applied to the I / O pad.

Description

[0001] Priority statement of related applications

[0002] This patent application claims priority and benefit to non-provisional application No. 17 / 370,894, filed July 8, 2021, with the United States Patent and Trademark Office, the entire contents of which are as fully set forth herein and incorporated herein for all applicable purposes. Technical Field

[0003] This disclosure generally relates to interface circuits for integrated circuits, and more specifically to electrostatic discharge protection circuits that enhance the robustness of charged device models of integrated circuit devices. Background Technology

[0004] Electronic device technology has experienced explosive growth in recent years. For example, better communication, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding range of features and services, providing users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablets, laptops, etc.) have become more powerful and complex than ever before. Continuous service enhancements require advancements in process technology that enable integrated circuit (IC) devices to achieve ever-increasing performance and transistor density.

[0005] Advances in process technology tend to reduce transistor gate length and other feature dimensions of IC devices. This reduction in gate length and feature dimensions increases the sensitivity of IC devices to electrostatic discharge (ESD) events. IC devices typically include ESD protection circuitry that protects interface circuitry during different types of ESD events. IC devices can be tested to ensure they meet minimum industry standards for ESD protection. IC device qualification processes may include testing the sensitivity of IC devices to ESD events using Human Body Model (HBM) or Charged Device Model (CDM) characterization based on ESD events. Some ESD protection circuitry is based on HBM or CDM, or uses either HBM or CDM for evaluation. HBM is designed to characterize the device's sensitivity to damage caused by ±1kV ESD events resulting from human contact with the electronic device. CDM is designed to characterize the device's sensitivity to damage caused by ±250V ESD events, which relate to the sudden release of energy accumulated in the IC chip or package through direct contact charging or field-inductive charging.

[0006] Changes in certain aspects of large-scale IC design and semiconductor manufacturing processes (including reducing the minimum feature size of the process) may cause new or different sensitivities of IC devices to ESD events. Therefore, there is a need to continuously improve the ESD protection of IC interface circuits. Summary of the Invention

[0007] Certain aspects of this disclosure relate to systems, apparatuses, methods, and techniques for providing enhanced ESD protection circuitry in certain IC devices, including IC devices employing multiple voltage domains. Some examples disclosed herein apply to interface circuitry in ICs. Some examples disclosed herein apply to protection circuitry located at the boundary between a low-voltage domain used to implement certain core features of an IC device and a high-voltage domain used for device inputs and outputs (I / O).

[0008] In one aspect of this disclosure, an ESD protection circuit includes: a driver transistor having a drain coupled to an I / O pad of an IC device and a source coupled to a rail of a first power supply in the IC device; an ESD protection diode coupling the I / O pad to the rail of the first power supply; and a gate pull transistor coupling the gate of the driver transistor to either the I / O pad or the rail of the first power supply.

[0009] In one aspect of this disclosure, an apparatus includes: means for driving I / O pads of an IC device, wherein the means for driving the I / O pads includes a driver transistor coupled through its source to a rail of a first power supply in the IC device; means for shunting electrostatic discharge current received at the I / O pads to the rail of the first power supply during an ESD event; and means for pulling the gate of the driver transistor to a voltage level of the I / O pads or the rail of the first power supply during an ESD event, wherein the means for pulling the gate of the driver transistor includes a gate pull transistor coupled between the gate of the driver transistor and the I / O pads or the rail of the first power supply.

[0010] In one aspect of this disclosure, a method for providing ESD protection in an IC device includes: coupling the drain of a driver transistor to an I / O pad of the IC device; coupling the source of the driver transistor to a rail of a first power supply in the IC device; using an ESD protection diode to couple the I / O pad and the rail of the first power supply; and using a gate pull transistor to couple the gate of the driver transistor to the I / O pad or the rail of the first power supply.

[0011] In some examples, the source of the driver transistor is coupled to the rail of the first power supply via at least one other transistor. The gate of the driver transistor can be configured to receive an input signal provided by a pre-driver circuit powered by a second power supply.

[0012] In some examples, the clamping circuit is coupled between the rail of the first power supply and the ground reference rail of the first power supply. The clamping circuit provides a control signal to the gate of the gate-pull transistor.

[0013] In some examples, the gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to a rail of a first power supply. The gate of the gate pull transistor may be coupled to a rail of a second power supply.

[0014] In some examples, the gate pull transistor is a P-type metal-oxide-semiconductor transistor. In one example, the gate pull transistor is configured to couple the gate of the driver transistor to a first power supply rail, and the gate of the gate pull transistor is also coupleable to a second power supply rail. In another example, the gate pull transistor is configured to couple the gate of the driver transistor to an I / O pad, and the gate of the gate pull transistor is also coupleable to either a first power supply rail or a second power supply rail.

[0015] In some examples, the gate pull transistor is an N-type metal-oxide-semiconductor transistor. The driver transistor can be either a P-type metal-oxide-semiconductor transistor or an N-type metal-oxide-semiconductor transistor.

[0016] In some examples, the gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the I / O pad or the rail of the first power supply during an ESD event.

[0017] In some examples, a dummy transistor or an additional unassigned transistor within the driver layout of the IC device is used to provide the gate pull transistor. Attached Figure Description

[0018] Figure 1 An example of an ESD event is shown.

[0019] Figure 2 A first example of an interface circuit is shown, which provides ESD protection in an IC device.

[0020] Figure 3 A second example of an interface circuit in an IC device is shown, which includes ESD protection circuitry.

[0021] Figure 4 The effect of an ESD event on the interface circuitry in an IC device, which includes ESD protection circuitry, is illustrated.

[0022] Figure 5An isolated view of the P-type metal-oxide-semiconductor (PMOS) driver transistor is provided during an ESD event, including current flowing into the I / O pads of the IC device.

[0023] Figure 6 A first configuration of a gate pull circuit according to certain aspects of this disclosure is shown.

[0024] Figure 7 A second configuration of the gate pull circuit according to certain aspects of this disclosure is shown.

[0025] Figure 8 The invention relates to an interface circuit that includes a PMOS gate pull transistor coupled to a power rail and a PMOS driver transistor, according to certain aspects of this disclosure.

[0026] Figure 9 The invention relates to an interface circuit that includes a PMOS gate pull transistor and a PMOS driver transistor coupled to an I / O pad according to certain aspects of this disclosure.

[0027] Figure 10 The invention relates to an interface circuit comprising an N-type metal-oxide-semiconductor (NMOS) gate pull transistor and a PMOS driver transistor coupled to a power rail according to certain aspects of this disclosure.

[0028] Figure 11 The present disclosure relates to an interface circuit that includes an NMOS gate pull transistor and a PMOS driver transistor coupled to an I / O pad according to certain aspects of the present disclosure.

[0029] Figure 12 The invention relates to an interface circuit that includes a PMOS gate pull transistor coupled to a power rail and an NMOS driver transistor, according to certain aspects of this disclosure.

[0030] Figure 13 The invention relates to an interface circuit that includes a PMOS gate pull transistor and an NMOS driver transistor coupled to an I / O pad according to certain aspects of this disclosure.

[0031] Figure 14 The present disclosure relates to an interface circuit that includes an NMOS gate pull-up transistor coupled to a power rail and an NMOS driver transistor, according to certain aspects of the present disclosure.

[0032] Figure 15 The present disclosure relates to an interface circuit that includes an NMOS gate pull transistor coupled to an I / O pad and an NMOS driver transistor, according to certain aspects of the present disclosure.

[0033] Figure 16This is a flowchart illustrating a method for providing ESD protection according to certain aspects disclosed herein. Detailed Implementation

[0034] The detailed description below, illustrated with reference to the accompanying drawings, is intended as a description of various configurations and not as representing the only configuration in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring these concepts, well-known structures and components are shown in block diagram form.

[0035] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0036] The terms “computing device” and “mobile device” are used interchangeably herein to refer to any or all of the following: servers, personal computers, smartphones, cellular phones, tablets, laptops, netbooks, ultrabooks, handheld computers, personal data assistants (PDAs), wireless email receivers, cellular phones with multimedia internet support, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices that include programmable processors. While these aspects are particularly useful in mobile devices (e.g., smartphones, laptops, etc.) with limited resources (e.g., processing power, battery, size, etc.), they are generally useful in any computing device that can benefit from improved processor performance and reduced power consumption.

[0037] The term "multi-core processor" is used herein to refer to a single integrated circuit (IC) chip or chip package containing two or more independent processing units or cores (e.g., CPU cores) configured to read and execute program instructions. The term "multiprocessor" is used herein to refer to a system or device comprising two or more processing units configured to read and execute program instructions.

[0038] The term "System-on-a-Chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip containing multiple resources and / or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose and / or special-purpose processors (digital signal processors (DSPs), modem processors, video processors, etc.), blocks of memory (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, regulators, oscillators, etc.), any one or all of which may be included in one or more cores.

[0039] The memory technologies described herein are suitable for storing instructions, programs, control signals, and / or data for use in or by a computer or other digital electronic device. Any references to terms and / or technical details relating to individual memory types, interfaces, standards, or memory technologies are for illustrative purposes only and are not intended to limit the scope of the claims to a particular memory system or technology, unless specifically stated in the language of the claims. The complexity of mobile computing device architectures has increased and now typically includes multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnects (e.g., buses and / or structures), and numerous other resources for executing complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0040] The process technologies used to manufacture semiconductor devices (including integrated circuit devices) are constantly being improved. Process technologies include manufacturing methods used to fabricate IC devices and define transistor dimensions, operating voltages, and switching speeds. Features that are components of the circuitry within an IC device can be referred to as technology nodes and / or process nodes. The terms "technology node," "process node," and "process technology" are used to characterize a specific semiconductor manufacturing process and its corresponding design rules. By using smaller feature sizes to produce smaller transistors that enable the fabrication of higher-density ICs, faster and more efficient technology nodes are continuously being developed.

[0041] Advances in transistor technology have led to reduced gate oxide thickness and lower operating voltages. Reduced gate oxide thickness decreases the maximum gate-drain and gate-source voltages the device can withstand during ESD events. Furthermore, ICs typically provide multiple voltage domains for power-saving purposes. For example, higher voltage domains provide power at higher voltage levels than lower voltage domains. Sometimes, higher voltage domains are needed to interface with external devices, while the core circuitry can typically operate at lower voltage levels available in the lower voltage domains. Stacks of low threshold voltage transistors can be used as I / O drivers that switch over a wider voltage range than the core circuitry operates within.

[0042] Electrostatic discharge (ESD) events can generate voltages or currents within an IC device that exceed its rated operating parameters (including the rated operating voltage). The rated operating voltage can be within the nominal operating range of voltage levels defined for certain devices, circuits, or input / output (I / O) pads. As used herein, an I / O pad can be defined as a structure that serves as the coupling point between internal circuitry at the core of the IC device and external terminals, connectors, or pins of the chip package carrying the IC device. In one example, an I / O pad may be coupled to an external terminal, connector, or pin via a wire thermoacoustically bonded to the I / O pad. In another example, an I / O pad may be coupled to an external terminal, connector, or pin via a solder ball contacting the I / O pad. Without adequate protection, circuitry can be damaged near I / O pads or other sources or entry points of ESD events. ESD events can occur due to a combination of grounding faults, handling and accumulation of static charge on surfaces or contacts near the IC device.

[0043] Certain aspects of this disclosure are described in relation to a charged device model (CDM) characterization of ESD events. This CDM relates to ESD events that occur when a chip, chip carrier, or package containing an IC device comes into contact with a low-impedance electrical path. If the chip, chip carrier, or package carries accumulated electrostatic charge, a sudden discharge of energy may occur, resulting in high-voltage pulses or spikes at the I / O pads of the IC device. Voltages observable at one or more I / O pads may exceed the rated tolerances of the transistors in the IC device, and without adequate ESD protection, could cause breakdown or other damage to the transistor gates and other features of the IC device.

[0044] Figure 1An example of an ESD event 100 characterizable by a CDM is shown. The ESD event 100 occurs when an IC device 102 is placed on a metal or other conductive surface 104. In some examples, this type of ESD event 100 may occur at a manufacturing or assembly facility when IC devices on a chip, chip carrier, or package are accumulated, assembled, or sorted before being placed and bonded or soldered to a circuit board. In some examples, this type of ESD event 100 may occur at a manufacturing facility where the robot may act as the conductive surface 104, when the IC device 102 is picked up by a robot and placed on a circuit board or transported in a package. When the IC device 102 is placed on the conductive surface 104, the charge accumulated in the IC device 102 can be discharged to the conductive surface 104 through one or more potential gradients 106, 108. The discharge may occur before or after the I / O pins or pads are directly coupled to the conductive surface 104.

[0045] Graph 120 illustrates an example of the type of ESD event 100 characterized by CDM. In this example, a high percentage of electrostatic energy accumulated in IC device 102 is discharged within a short period 122 in an initial pulse or spike 130. In one example, ESD event 100 may have a duration 124 lasting approximately 5 nanoseconds, with the initial spike 130 ending after approximately 1 nanosecond. In some instances, the discharge may result in a first peak 126 at a current level 128 of 4.7 amps or greater. Current spikes flowing through the I / O pads of IC device 102 may result in corresponding voltage spikes in the interface circuitry of IC device 102.

[0046] Current ESD protection schemes for protecting output drivers typically include a diode connected between the interface pad and the output power rail, and may include a clamping circuit in series with the diode discharge path, which can carry ESD current and thus prevent damage to the driver device.

[0047] Figure 2 A first example of an interface circuit 200 is shown, which provides ESD protection in an IC device. The interface circuit 200 includes a driver 204 that can be used to send signals through I / O pads 202 of the IC device. The driver 204 can be configured to provide an output on the power rail (V... DD 210) and ground reference (V SS Switching between 212). ESD protection is provided by the pairing of diodes 206 and 208. The first diode 206 is coupled to V. DD 210 and I / O pad 202, and the voltage of I / O pad 202 is kept below V. DD At 210, it is reverse biased. The second diode 208 is coupled to V. SS212 and I / O pad 202, and the voltage of I / O pad 202 is kept higher than V. SS At 212, it is reverse biased. An ESD event can cause a current surge through I / O pad 202 and one or more interconnects between I / O pad 202 and driver 204. The interconnects have low resistance, which can significantly change the voltage of I / O pad 202 when conducting multi-amp ESD surge current. This voltage change is sufficient to forward bias one of diodes 206 and 208, thereby allowing the ESD surge current to be shunted to other circuitry away from driver 204 and IC devices. DD 210 or V SS 212.

[0048] Divert ESD surge current to V DD 210 or V SS 212 can increase V DD 210 and V SS The voltage difference between 212, if left unchecked, could stress or damage the devices in interface circuit 200. The interface circuit 200 shown includes components coupled to V... DD 210 and V SS A power rail clamping circuit 220 is provided between 212. The power rail clamping circuit 220 includes an N-type metal-oxide-semiconductor (NMOS) transistor 222 biased by a series RC network 224. The RC network 224 has a capacitor 232 coupled in series with a resistor 234. In the illustrated example, the series RC network 224 is coupled to the power supply V. DD 210 and ground reference V SS Between 212. Node 230 of coupling capacitor 232 and resistor 234 is coupled to the gate of transistor 222 via a buffer amplifier arrangement comprising a first series-connected inverter 226 and a second series-connected inverter 228. When an ESD pulse is applied to I / O pad 202, causing V... DD 210 and V SS When the voltage difference between 212 increases, the power rail clamping circuit 220 ensures that the power supply rail is clamped from V... DD 210 to V SS 212 low impedance path.

[0049] In one example, V DD The rising voltage on 210 is coupled to the input of the first inverter 226 through capacitor 232, thereby forcing its output to a low voltage state. In response, the output of the second inverter 228 goes high, thereby turning on transistor 222. When transistor 222 is turned on, ESD current can begin to rise at V. DD 210 and V SSThe flow occurs between 212. Some ESD protection circuits provided in this disclosure may use the outputs of the first inverter 226 and the second inverter 228 as complementary ESD event indicator signals 236, 238.

[0050] Figure 3 A second example of interface circuitry 300 in an IC device is shown, which includes ESD protection circuitry. For the purposes of this description, a conceptual division 330 between the high-voltage and low-voltage domains is shown, but a clear physical separation between the voltage domains may not be discernible. The high-voltage domain is connected via V... DD 1 track 308 with V DD 1. Voltage level supplies power, and the low voltage domain passes through V DD 2 tracks 320 with V DD 2. Voltage level power supply. Interface circuit 300 includes components configured to drive I / O pads 302 to V. DD Two sets of P-type metal-oxide-semiconductor (PMOS) transistors (PMOS driver transistors 304, 314). Pull I / O pad 302 to ground reference (V). SS Voltage level (V) of rail 310 SS The interface circuit 300 is not shown in detail. The gates of the four PMOS driver transistors 304 are supplied with a cross-domain signal (C) provided by the low-voltage pre-driver transistor 322, which operates in the low-voltage domain. trl_0 -C trl_3 ) drive. A low-voltage pre-driver transistor 322 is provided to drive the signal applied to the gate 316 of the PMOS driver transistor 304 from V DD 2. Voltage level shifted to V DD 1. Voltage level.

[0051] In some examples, V DD 2 tracks 320 to V DD The 1-rail 308 provides power at a lower voltage level, and low-voltage domain signals can be delivered at V. SS With V DD Switching between voltage levels of 2. In these examples, V DD 1 can represent a voltage level of 3.3 volts or 1.8 volts, and V DD 2 can represent a voltage level of 1.8 volts or 1.2 volts. In other examples, the core circuitry can operate at the same voltage level as the interface circuitry or at a higher voltage level.

[0052] The pairing of diodes 306a and 306b nominally provides ESD protection for the circuitry coupled to I / O pad 302 (including PMOS driver transistor 304). The voltage at I / O pad 302 increases to V. DDA voltage of 1 or higher can exceed the minimum forward bias voltage (V) of diode 306a. f The forward-biased diode 306a limits the voltage increase at I / O pad 302, and the voltage rise at the drain of the PMOS driver transistor 304 is expected to be limited to not significantly greater than V. DD 1+V f The voltage. Similarly, due to the operation of diode 306b, the expected drop in the drain voltage of PMOS driver transistor 304 can be limited to V. SS -V f .

[0053] In various examples, the ESD orbit clamp 312 can be configured to limit V. DD The voltage difference between rail 308 and the ground reference voltage (i.e., V) DD 1-V SS The change of ). In one example, Figure 2 The power rail clamping circuit 220 can be configured to function as an ESD rail clamping section 312. In some examples, the ESD rail clamping section 324 can be configured to limit V DD The voltage difference between rail 320 and ground reference (i.e., V) DD 2-V SS ) changes.

[0054] Figure 4 The effect of ESD event 416 on interface circuitry 400 in an IC device, which includes ESD protection circuitry, is illustrated. When either ESD protection diode 406a or 406b becomes forward biased during ESD event 416, the ESD current is expected to be shunted to V through one of the ESD protection diodes 406a or 406b. DD 1 track 408 or V SS Rail 410. A negative CDM stress test can be used to simulate an ESD event 416, where an ESD current 418 enters the I / O pad 402. The ESD current 418 flowing through the I / O pad 402 can generate... Figure 1 The voltage waveform corresponding to the ESD event 100 shown is illustrated, where the first peak 126 is positive and increases to the V of the IC device. DD Above the voltage level of rail 408. During negative CDM testing on I / O pad 402, ESD current 418 is expected to be shunt to V through ESD protection diode 406a. DD Track 1, 408.

[0055] The interface circuit 400 can be similar in some respects to Figure 3The interface circuit 300 shown is illustrated. The interface circuit 400 shown includes two sets of PMOS transistors 404 and 414, which are configured to drive the I / O pad 402 to V. DD Voltage level of rail 408 (V) DD 1). Pull I / O pad 402 to the ground reference (here, V SS The portion of the interface circuit 400 for the rail 410 voltage is not shown in detail. The gates of the four PMOS driver transistors 404 are controlled by a lower V... DD The low-voltage pre-driver transistor 422, operating at 2 voltage levels, provides the cross-domain signal (C). trl_0 -C trl_3 (Driven by) a low-voltage pre-driver transistor 422 to shift the signal applied to the gate of the PMOS driver transistor 404 from the low-voltage domain to the high-voltage domain. The low-voltage domain signal can be shifted to the high-voltage domain at V. SS With V DD Switching between 2 and 3. In some examples, V DD 1 indicates a voltage level of 3.3 volts or 1.8 volts. In some examples, V DD 2 indicates a voltage level of 1.8 volts or 1.2 volts.

[0056] Coupled in V DD Track 1, 408 and V SS A pair of ESD protection diodes 406a and 406b between rails 410 is provided for ESD protection of a circuit coupled to I / O pad 402, which includes a PMOS driver transistor 404. In one example, the simulation of ESD event 416 can be configured to generate a 250-volt peak voltage at I / O pad 402. When the voltage at I / O pad 402 exceeds V... DD 1+V f When coupled to V DD The ESD protection diode 406a of rail 408 is switched to forward bias, where V f This indicates the forward bias voltage of the ESD protection diode 406a. The forward-biased ESD protection diode 406a shunts the ESD current 418 generated by the ESD event 416 to V. DD Track 1, 408.

[0057] The ESD rail clamping circuit 412 can mitigate the impact of shunting the ESD current to V. DD 1 track 408 (or V) SS V caused by track 410) DD The voltage level rises on rail 408. ESD rail clamping circuit 412 is configured to limit V... DD The voltage difference between rail 408 and ground (i.e., V) DD 1-VSS The change in voltage (V) is significant. In the low voltage domain, the ESD track clamping circuit 424 can be configured to limit V. DD The voltage difference between rail 420 and ground (i.e., V) DD 2-V SS The change of ). In one example, Figure 2 The power rail clamping circuit 220 can be configured to function as the ESD rail clamping circuit 412.

[0058] Conventional ESD protection circuits can protect I / O devices operating in higher voltage domains, but they can make the interface between the low and high voltage domains susceptible to ESD-related damage. For example, PMOS driver transistor 404, which has a gate driven by a cross-voltage domain signal, may be damaged.

[0059] Figure 5 An isolated view 500 of the PMOS driver transistor 504 is provided during an ESD event 516 generated by a negative CDM test on the I / O pad 502 of an IC device. The ESD event 516 may involve a negative CDM stress test, where an ESD current 514 enters the I / O pad 502. The ESD current 514 may have a... Figure 1 The waveform corresponding to the ESD event 100 shown is shown, where the first peak 126 is positive and increases to the power V supplied to the IC device. DD The nominal V of 1 track 508 DD Above voltage level 1. During negative CDM testing on the I / O pad 502 of the IC device, the ESD current 514 is expected to be shunt to V through the ESD protection diode 506. DD Track 508. In some instances, an overvoltage condition occurring between the drain 510 and gate 512 of the PMOS driver transistor 504 during an ESD event 516 can damage the PMOS driver transistor 504. A sufficiently high differential voltage 518 (|Vgd|) between the drain 510 and gate 512 of the PMOS driver transistor 504 can cause physical breakdown of the transistor gate.

[0060] The differential voltage 518 that reaches a destructive overvoltage level during ESD event 516 can be attributed to a cross-domain signal 522 driving the gate 512 of the PMOS driver transistor 504. For example, ESD event 516 can cause a power rail (here, V) supplying power within the voltage domain of the PMOS driver transistor 504 to... DD The voltage on track 1 (508) suddenly increased. V DD The voltage increase of rail 508 may not be affected by the V supplied with power within the voltage domain of pre-driver 524. DDThe changes in track 520 are closely tracked. The pre-driver 524 provides the transdomain signal 522 to the gate 512 of the PMOS driver transistor 504. V DD Track 1508 and V DD The resulting increase in the voltage difference between rails 520 can propagate with an increase in the relative voltage between the transverse signal 522 and the voltage at the drain 510 of the PMOS driver transistor 504. In one example, the absolute voltage of the transverse signal 522 may remain constant for a short period of time, while the voltage at the drain 510 follows the voltage of the I / O pad 502 during ESD event 516, causing a change in the differential voltage 518 sufficient to damage the PMOS driver transistor 504. ESD rail clamping circuits 412, 424 (see...) Figure 4 Operational delays can lead to V DD Track 1508 and V DD The change in voltage difference between the two 520 rails.

[0061] Applying a 250V ESD peak voltage to I / O pad 502 can cause an overvoltage condition between the drain 510 and gate 512 of the PMOS driver transistor 504, while V DD Track 1508 and V DD The polarity or amplitude of the voltage difference between the two rails (520) is irrelevant. Regardless of V DD 1>V DD 2. V DD 1 <V DD 2 or V DD 1 = V DD 2. Overvoltage conditions can occur in both cases. In some instances, overvoltage conditions may occur because AC decoupling of one or more power rails or ground rails is performed between different parts of the IC device. ESD events 416 and 516 are described for interface circuits constructed with double-stacked PMOS transistors, although ESD-induced overvoltage conditions can affect interface circuits constructed with NMOS transistors, or interface circuits using single, three, or more transistor stacks.

[0062] Certain aspects of this disclosure can reduce or eliminate overvoltage conditions caused by the interaction between an ESD event and multiple voltage domains or voltage rails. In some examples, a gate pull-up circuit can be employed to reduce the transient gate-drain voltage difference during an ESD event. The gate pull-up circuit can be configured to... Figure 5This describes how to prevent additional overvoltage conditions that might occur between the drain 510 and gate 512 of the PMOS driver transistor 504 during an ESD event 516 as described. A gate pull-up circuit can be used to prevent overvoltage conditions that could affect PMOS or NMOS driver transistors in various interface circuits. In one example, the gate pull-up circuit is coupled between the gate of the driver transistor and a voltage rail or I / O pad. The gate pull-up circuit is activated when the voltage level of the voltage rail or I / O pad is affected by an ESD event. When activated, the gate pull-up circuit pulls the voltage level of the driver transistor's gate towards the voltage level of the I / O pad, and thus reduces the voltage difference between the gate and drain of the driver transistor.

[0063] Figure 6 The present disclosure relates to interface circuitry 600, which illustrates a first configuration of gate pull-up circuitry 6100-6103 according to certain aspects of this disclosure. Gate pull-up circuitry 6100-6103 is configured to pull the gates 6120-6123 of PMOS driver transistors 6040-6043 to the rails of the power supply in the IC device during an ESD event (here, V...). DD The voltage level of track 608. ESD events can be modeled, characterized, or initiated as a negative CDM test on the I / O pad 602 of an IC device. In one example, an ESD event corresponds to a negative CDM stress test, where ESD current enters the I / O pad 602 and is guided to V through the ESD protection diode 606. DD Track 608. During an ESD event, the gate pull circuits 6100-6103 are enabled and a high potential is applied to the gates 6120-6123 of the PMOS driver transistors 6040-6043.

[0064] By using PMOS driver transistors 6040-6043 and V DD A low-impedance path is provided between rails 608, and gate pull circuits 6100-6103 can reduce the voltage difference between the gates 6120-6123 and the corresponding drains 6140-6143 of the PMOS driver transistors 6040-6043 during ESD events. In some examples, gate pull circuits 6100-6103 can be configured to pull the gates 6120-6123 of the PMOS driver transistors 6040-6043 to V during negative CDM ESD testing. DDThe voltage level of rail 608. Gate pull-up circuits 6100-6103 maintain the gate 6120-6123 of PMOS driver transistors 6040-6043 close to the drain 6140-6143 of PMOS driver transistors 6040-6043 during ESD events. In some examples, the voltage level of gate 6120-6123 differs from the voltage level of drain 6140-6143 by approximately the forward bias voltage of ESD protection diode 606. Gate pull-up circuits 6100-6103 are configured to remain in a high-impedance state during normal circuit operation.

[0065] Figure 7 The present disclosure relates to an interface circuit 700 in an IC device, illustrating a second configuration of gate pull-up circuits 7100-7103 according to certain aspects of this disclosure. Gate pull-up circuits 7100-7103 are configured to pull the gates 7120-7123 of PMOS driver transistors 7040-7043 to the voltage level of I / O pad 702 during an ESD event. ESD events can be modeled, characterized, or initiated as a negative CDM test on the I / O pad 702 of the IC device. In one example, the ESD event corresponds to a negative CDM stress test, where ESD current enters the I / O pad 702 and is guided to the voltage rail (here, V) via the ESD protection diode 706. DD 1 track 708). During an ESD event, the gate pull circuit 7100-7103 is enabled and a high potential is applied to the gates 7120-7123 of the PMOS driver transistors 7040-7043.

[0066] By providing a low-impedance path between the PMOS driver transistors 7040-7043 and the I / O pads 702, the gate pull-up circuits 7100-7103 can reduce the voltage difference between the gates 7120-7123 and the corresponding drains 7140-7143 of the PMOS driver transistors 7040-7043 during ESD events. In this example, the gate pull-up circuits 7100-7103 are configured to pull the gates 7120-7123 of the PMOS driver transistors 7040-7043 to the voltage level of the I / O pads 702 during a negative CDM ESD test. The drains 7140-7143 of the PMOS driver transistors 7040-7043 are also coupled to I / O pads 702, and the gate pull circuits 7100-7103 can maintain the voltage level of the gates 7120-7123 of the PMOS driver transistors 7040-7043 close to the voltage level of the drains 7140-7143 of the PMOS driver transistors 7040-7043 during ESD events. The gate pull circuits 7100-7103 can be configured to remain in a high-impedance state during normal circuit operation.

[0067] Figure 8 The present disclosure relates to an interface circuit 800 in an IC device, which includes PMOS driver transistors 8040-8043 and PMOS gate pull transistors 8100-8103 configured according to certain aspects of the present disclosure. The PMOS gate pull transistors 8100-8103 are configured to pull the gates 8060-8063 of the PMOS driver transistors 8040-8043 to the rails of a power supply (here, V...) during an ESD event. DD The voltage level of track 808). In one example, the gates of PMOS gate pull transistors 8100-8103 can be clamped to different low voltage domains via tie-high circuits 8120-8123. DD 2 tracks. Using V DD The clamping circuits 8120-8123 are implemented using direct coupling of two rails. In another example, passive components such as resistors are used to couple the gate of the PMOS gate pull transistors 8100-8103 to V. DD Two rails are used to implement the clamping circuit 8120-8123.

[0068] During normal operation, PMOS gate pull transistors 8100-8103 are turned off and remain in the off state. A negative CDM-type ESD event causes the potential of I / O pad 802 to rise to a level greater than V. DD Track 1, 808 and V DD The voltage level of rail 2 is a higher voltage level. PMOS gate pull transistors 8100-8103 are turned on and the voltage difference (|Vgd|) between gate 8060-8063 and drain 8140-8143 is reduced.

[0069] Each of the PMOS gate pull transistors 8100-8103 in interface circuit 800 is typically mismatched with any other transistor in or elsewhere in interface circuit 800, and can be implemented using matched or unmatched gates that are initially designated as spare or additional unused gates within a portion of the IC layout that includes interface circuit 800. In one example, for balancing purposes, some techniques or designs provide unused transistors at both edges of the driver layout group. In other examples, unused transistors may be present at or near the center of the driver layout group. The driver layout group can define the physical location of the gate group used to implement interface circuit 800 within the IC. In some instances, unused transistors may have an elongated physical shape and may be referred to as “dummy fingers” or “dummy transistors.” In some examples, unused transistors (which may also be referred to as unassigned transistors) may be provided in certain areas of the IC device to help prevent transistor performance mismatch due to layout dependency effects. Unused transistors may have the structure of used transistors without having connections to another transistor, device, or circuit. The PMOS gate pull transistors 8100-8103 remain at high impedance during normal operation without affecting the operation of other IC circuits. Therefore, one or more of these dummy transistors or unassigned transistors can be used to implement the PMOS gate pull transistors 8100-8103 for ESD protection purposes. It will be understood that the transistors selected during design layout from the transistor groups or blocks designated as unassigned transistors for use as PMOS gate pull transistors 8100-8103 may be physically adjacent to one or more unused and unassigned transistors in the final IC layout.

[0070] Figure 9 The present disclosure relates to an interface circuit 900 in an IC device, which includes PMOS driver transistors 9040-9043 and PMOS gate pull-up transistors 9100-9103 configured according to certain aspects of the present disclosure. The PMOS gate pull-up transistors 9100-9103 are coupled between the gates 9060-9063 of the PMOS driver transistors 9040-9043 and I / O pads 902. The PMOS gate pull-up transistors 9100-9103 are configured to pull the gates 9060-9063 of the PMOS driver transistors 9040-9043 to the voltage level of the I / O pads 902 during an ESD event. The gates of the PMOS gate pull-up transistors 9100-9103 can be clamped to the power rails (V) via clamping circuits 9120-9123. DD 1 rail 908 or V in different voltage domains DD 2 tracks). In one example, V is used. DDA 1-track 908 is directly coupled to implement the clamping circuit 9120-9123. In another example, V is used. DD The clamping circuits 9120-9123 are implemented using direct coupling of two rails. In some instances, passive components such as resistors are used to couple the gate of the PMOS gate pull transistors 9100-9103 to V. DD 1 track 908 or V DD Two rails are used to implement the clamping circuit 9120-9123.

[0071] During normal operation, PMOS gate pull transistors 9100-9103 are turned off and remain in the off state. A negative CDM-type ESD event causes the potential of I / O pad 902 to rise to a level greater than V. DD Track 1, 908 and V DD Two rails provide higher voltage levels. PMOS gate pull transistors 9100-9103 are turned on and can reduce the voltage difference (|Vgd|) between the gate 9060-9063 and the drain 9140-9143.

[0072] Each of the PMOS gate pull transistors 9100-9103 in the interface circuit 900 is typically mismatched with any other transistor in or elsewhere in the interface circuit 900, and can be implemented using a spare or additional unused gate near the interface circuit 900 within the IC. In one example, for balancing purposes, some techniques or designs have unused transistors at both edges of the driver layout group. In other examples, unused transistors may be present at or near the center of the driver layout group. Unused transistors may have an elongated physical shape and may be referred to as “dummy fingers” or “dummy transistors.” In some examples, unused transistors (which may also be referred to as unassigned transistors) may be provided in regions of the IC device to help prevent transistor performance mismatch due to layout dependency effects. The PMOS gate pull transistors 9100-9103 remain at high impedance during normal operation and do not affect the operation of other IC circuits. Therefore, one or more of these dummy transistors or unassigned transistors can be used to implement the PMOS gate pull transistors 9100-9103 for ESD protection purposes.

[0073] Figure 10 The present disclosure relates to an interface circuit 1000 in an IC device, which includes PMOS driver transistors 10040-10043 and NMOS gate pull transistors 10100-10103 configured according to certain aspects of the present disclosure. The NMOS gate pull transistors 10100-10103 are configured to pull the gates 10060-10063 of the PMOS driver transistors 10040-10043 to the rails of a power supply (here, V0) during an ESD event. DDThe voltage level of rail 1008. Each gate of the NMOS gate pull transistors 10100-10103 can be clamped to ESD control input 1012. ESD control input 1012 can be provided to indicate an ESD event and trigger or enable one or more types of ESD protection circuitry. Each ESD control input in ESD control input 1012 can be provided by the same ESD controller. In some examples, the ESD controller can be implemented in the ESD detection circuitry used in the ESD rail clamp, which is common in ESD protection designs. In one example, it can be obtained from the voltage level of rail 1008. Figure 2 One or more of the ESD event indicator signals 236 and 238 generated by the power rail clamping circuit 220 shown are used to derive the ESD control input 1012.

[0074] During normal operation, NMOS gate pull transistors 10100-10103 are turned off and remain in the off state. A negative CDM-type ESD event causes the potential of I / O pad 1002 to rise to a level higher than V. DD Track 1008 and V DD The two rails (which power the pre-drivers of the gates 10060-10063 of the PMOS driver transistors 10040-10043) have higher voltage levels. The NMOS gate pull transistors 10100-10103 turn on in response to an ESD event and can reduce the voltage difference (|Vgd|) between the gates 10060-10063 and the drains 10140-10143.

[0075] Figure 11 The present disclosure relates to an interface circuit 1100 in an IC device, which includes PMOS driver transistors 11040-11043 and NMOS gate pull transistors 11100-11103 configured according to certain aspects of the present disclosure. The NMOS gate pull transistors 11100-11103 may be coupled between the gates 11060-11063 of the PMOS driver transistors 11040-11043 and I / O pads 1102. Each gate of the NMOS gate pull transistors 11100-11103 may be clamped to an ESD control input 1112. The ESD control input 1112 may be provided to indicate an ESD event and trigger or enable one or more types of ESD protection circuitry. The ESD control input 1112 may be provided by the same ESD controller. In one example, the ESD controller may be implemented in an ESD detection circuitry used in an ESD rail clamp, which is common in ESD protection designs. ESD control input 1112 can be derived from the same signal output by the ESD track clamping unit.

[0076] During normal operation, NMOS gate pull transistors 11100-11103 are turned off and remain in the off state. A negative CDM-type ESD event causes the potential of I / O pad 1102 to rise to a level greater than V. DD Track 1108 and V DD The higher voltage level of the two rails (which power the pre-driver) and the turn-on of the NMOS gate pull transistors 11100-11103 reduce the voltage difference (|Vgd|) between the gates 11060-11063 and the drains 11140-11143.

[0077] Each of the NMOS gate pull transistors 10100-10103 and 11100-11103 in interface circuits 1000 and 1100 is typically mismatched with any other transistor in or elsewhere in interface circuits 1000 and 1100, and can be implemented using a spare or additional unused gate near interface circuits 1000 and 1100 within the IC. In one example, for balancing purposes, some techniques or designs provide unused transistors at both edges of the driver layout group. In other examples, unused transistors may be present at or near the center of the driver layout group. Unused transistors may have an elongated physical shape and may be referred to as dummy fingers. In some examples, unused transistors (which may also be referred to as unassigned transistors) may be provided in regions of the IC device to help prevent transistor performance mismatch due to layout dependency effects. NMOS gate pull transistors 10100-10103 and 11100-11103 remain at high impedance during normal operation and do not affect the operation of other IC circuits. Therefore, one or more of these dummy transistors or unassigned transistors can be used to implement NMOS gate pull transistors 10100-10103 and 11100-11103 for ESD protection purposes.

[0078] The use of gate pull transistors 8100-8103, 9100-9103, 10100-10103, and 11100-11103 enables PMOS driver transistors 8040-8043, 9040-9043, 10040-10043, and 11040-11043 to withstand ESD events more reliably. Gate pull transistors 8100-8103, 9100-9103, 10100-10103, and 11100-11103 can be configured as either thin-gate oxide transistors or thick-gate oxide transistors.

[0079] In the first example, when gate pull transistors 8100-8103 and 10100-10103 are used to pull the gates 8060-8063 and 10060-10063 of PMOS driver transistors 8040-8043 and 10040-10043 to V...DD At 1808 and 1008, an improvement of approximately 27.18% in |Vgd| can be expected. In the second example, when gate pull transistors 9100-9103 and 11100-11103 are used to pull the gates 9060-9063 and 11060-11063 of PMOS driver transistors 9040-9043 and 11040-11043 to the voltage levels of I / O pads 902 and 1102, an improvement of approximately 29.73% in |Vgd| can be expected.

[0080] When the gate is pulled to V DD When selecting between rails 808 and 1008 and gate-pull-to-I / O pads 902 and 1102, other factors may be considered. In one example, the coupling of gate-pull transistors 9100-9103 and 11100-11103 to I / O pads 902 and 1102 may result in a coupling relative to V... DD The gate pull of the 1-rail 808, 1008 provides an additional capacitive load. In another example, it is clamped to V. DD The use of gate pull transistors 8100-8103 and 10100-10103 for rails 808 and 1008 can be limited to circuits involving two or more voltage domains, while gate pull to the voltage level of I / O pads 802 and 1002 can be used within a single voltage domain.

[0081] In some aspects of this disclosure, when an NMOS transistor is used as a driver transistor in an interface circuit of an IC device, a gate pull-up circuit can be used. Figure 12 The present disclosure relates to an interface circuit 1200 in an IC device, which includes NMOS driver transistors 12040-12043 and PMOS gate pull transistors 12100-12103 configured according to certain aspects of the present disclosure. The PMOS gate pull transistors 12100-12103 are configured to pull the gates 12060-12063 of the NMOS driver transistors 12040-12043 to the rails of a power supply (here, V0) during an ESD event. DD The voltage level of rail 1208). The gates of PMOS gate pull transistors 12100-12103 can be clamped to V in the second voltage domain through clamping circuits 12120-12123. DD 2 tracks. In one example, V is used. DD The clamping circuits 12120-12123 are implemented using direct coupling of two rails. In another example, passive components such as resistors are used to couple the gate of the PMOS gate pull transistors 12100-12103 to V. DD Two rails are used to implement the clamping circuit 12120-12123.

[0082] During normal operation, PMOS gate pull transistors 12100-12103 are turned off and remain in the off state. A negative CDM-type ESD event causes the potential of I / O pad 1202 to rise to a level higher than V. DD Track 1208 and V DD The two rails have a higher voltage level, and the PMOS gate pull transistors 12100-12103 are turned on, thereby reducing the voltage difference (|Vgd|) between the gate 12060-12063 and the drain 12140-12143.

[0083] Figure 13 The present disclosure relates to an interface circuit 1300 in an IC device, which includes NMOS driver transistors 13040-13043 and PMOS gate pull-up transistors 13100-13103 configured according to certain aspects of the present disclosure. The PMOS gate pull-up transistors 13100-13103 are coupled between the gates 13060-13063 of the NMOS driver transistors 13040-13043 and I / O pads 1302. The PMOS gate pull-up transistors 13100-13103 are configured to pull the gates 13060-13063 of the NMOS driver transistors 13040-13043 to the voltage level of the I / O pads 1302 during an ESD event. The gates of the PMOS gate pull-up transistors 13100-13103 can be clamped to the power rails via clamping circuits 13120-13123. In one example, a V associated with the interface circuit is used. DD A direct coupling of one rail is used to implement the clamping circuits 13120-13123. In another example, V is used in conjunction with the core circuit. DD The clamping circuits 13120-13123 are implemented using direct coupling of two rails. In some instances, passive components such as resistors are used to couple the gate of the PMOS gate pull transistors 13100-13103 to V. DD 1 track or V DD Two rails are used to implement the clamping circuit 13120-13123.

[0084] During normal operation, PMOS gate pull transistors 13100-13103 are turned off and remain in the off state. A negative CDM-type ESD event causes the potential of I / O pad 1302 to rise to a level higher than V. DD 1 track and V DD The two rails have a higher voltage level, and the PMOS gate pull transistors 13100-13103 are turned on, thereby reducing the voltage difference (|Vgd|) between the gate 13060-13063 and the drain 13140-13143.

[0085] Each of the PMOS gate pull transistors 12100-12103 and 13100-13103 in interface circuits 1200 and 1300 is typically mismatched with any other transistor in or elsewhere in interface circuits 1200 and 1300, and can be implemented using a spare or additional unused gate near interface circuits 1200 and 1300 within the IC. In one example, for balancing purposes, some techniques or designs have unused transistors at both edges of the driver layout group. In other examples, unused transistors may be present at or near the center of the driver layout group. Unused transistors may have an elongated physical shape and may be referred to as dummy fingers or dummy transistors. In some examples, unused transistors (which may also be referred to as unallocated transistors) may be provided in regions of the IC device to help prevent transistor performance mismatch due to layout dependency effects. PMOS gate pull transistors 12100-12103 and 13100-13103 remain at high impedance during normal operation and do not affect the operation of other IC circuits. Therefore, one or more of these edge dummy fingers or dummy transistors can be used to implement PMOS gate pull transistors 12100-12103, 13100-13103 for ESD protection purposes. PMOS gate pull transistors 12100-12103, 13100-13103 can be formed as thin gate oxide transistors or thick gate oxide transistors.

[0086] Figure 14 The present disclosure relates to an interface circuit 1400 in an IC device, which includes NMOS driver transistors 14040-14043 and NMOS gate pull transistors 14100-14103 configured according to certain aspects of the present disclosure. The NMOS gate pull transistors 14100-14103 are configured to pull the gates 14060-14063 of the NMOS driver transistors 14040-14043 to the rails of a power supply (here, V0) during an ESD event. DD 1 rail 1408). Each gate of the NMOS gate pull transistors 14100-14103 can be clamped to an ESD control input 1412. ESD control inputs 1412 can be provided to indicate an ESD event and trigger or enable one or more types of ESD protection circuitry. Each ESD control input in the ESD control inputs 1412 can be provided by the same ESD controller. In some examples, the ESD controller can be implemented in the ESD detection circuitry used in the ESD rail clamp, which is common in ESD protection designs. In one example, it can be obtained from... Figure 2 One or more of the ESD event indicator signals 236 and 238 generated by the power rail clamping circuit 220 shown are used to derive the ESD control input 1412.

[0087] During normal operation, NMOS gate pull transistors 14100-14103 are turned off and remain in the off state. A negative CDM-type ESD event causes the potential of I / O pad 1402 to rise to a level higher than V. DD Track 1408 and V DD The two rails have a higher voltage level, and the NMOS gate pull transistors 14100-14103 are turned on, thereby reducing the voltage difference (|Vgd|) between the gate 14060-14063 and the drain 14140-14143.

[0088] Figure 15 The present disclosure relates to an interface circuit 1500 in an IC device, which includes NMOS driver transistors 15040-15043 and NMOS gate pull transistors 15100-15103 configured according to certain aspects of the present disclosure. The NMOS gate pull transistors 15100-15103 may be coupled between the gates 15060-15063 of the NMOS driver transistors 15040-15043 and I / O pads 1502. Each gate of the NMOS gate pull transistors 15100-15103 may be clamped to an ESD control input 1512. The ESD control input 1512 may be provided to indicate an ESD event and trigger or enable one or more types of ESD protection circuitry. The ESD control input 1512 may be provided by the same ESD controller. In one example, the ESD controller may be implemented in an ESD detection circuitry used in an ESD rail clamp, which is common in ESD protection designs. ESD control input 1512 can be derived from the same signal output by the ESD track clamp.

[0089] During normal operation, NMOS gate pull transistors 15100-15103 are turned off and remain in the off state. A negative CDM-type ESD event causes the potential of I / O pad 1502 to rise to a level higher than V. DD 1 track and V DD The two rails have a higher voltage level, and the NMOS gate pull transistors 15100-15103 are turned on, thereby reducing the voltage difference (|Vgd|) between the gate 15060-15063 and the drain 15140-15143.

[0090] Each of the NMOS gate pull transistors 14100-14103 and 15100-15103 in interface circuits 1400 and 1500 is typically mismatched with any other transistor in or elsewhere in interface circuits 1400 and 1500, and can be implemented using a spare or additional unused gate near interface circuits 1400 and 1500 within the IC. In one example, for balancing purposes, some techniques or designs have unused transistors at both edges of the driver layout group. In other examples, unused transistors may be present at or near the center of the driver layout group. Unused transistors may have an elongated physical shape and may be referred to as dummy fingers or dummy transistors. In some examples, unused transistors (which may also be referred to as unallocated transistors) may be provided in regions of the IC device to help prevent transistor performance mismatch due to layout dependency effects. The NMOS gate pull transistors 14100-14103 and 15100-15103 remain at high impedance during normal operation and do not affect the operation of other IC circuits. Therefore, one or more of these dummy transistors or unassigned transistors can be used to implement NMOS gate pull transistors 14100-14103, 15100-15103 for ESD protection purposes. NMOS gate pull transistors 14100-14103, 15100-15103 can be formed as thin gate oxide transistors or thick gate oxide transistors.

[0091] Figure 16 This is a flowchart illustrating an example of a method 1600 for providing ESD protection in an IC device according to certain aspects disclosed herein. The method may involve... Figures 6 to 15 The diagram illustrates various features and aspects of the ESD protection circuit. At block 1602, the drain of a driver transistor can be coupled to an I / O pad of the IC device. The driver transistor can be a PMOS or NMOS transistor. At block 1604, the source of the driver transistor can be coupled to a first power supply rail in the IC device. In one example, the source of the driver transistor can be coupled to the first power supply rail via at least one other transistor. At block 1606, an electrostatic discharge protection diode can be used to couple the I / O pad and the first power supply rail. In some examples, the diode is reverse biased when a rated voltage is applied to the I / O pad. The rated voltage can be within the nominal operating range of the voltage level defined for the I / O pad. At block 1608, a gate pull transistor can be used to couple the gate of the driver transistor to either the I / O pad or the first power supply rail.

[0092] In some examples, the driver transistor can be coupled to the rail of the first power supply via at least one other transistor. The gate of the driver transistor can be configured to receive an input signal provided by a pre-driver circuit operating in a voltage domain corresponding to the second power supply.

[0093] In some examples, the clamping circuit may be coupled between the rail of the first power supply and the ground reference rail of the first power supply. The clamping circuit may be configured to provide a control signal to the gate of the gate-pull transistor.

[0094] In some examples, the gate pull transistor is a PMOS transistor configured to couple the gate of the driver transistor to the rail of a first power supply. The gate of the gate pull transistor may be coupled to the rail of a second power supply.

[0095] In some examples, the gate pull transistor is a PMOS transistor configured to couple the gate of the driver transistor to the I / O pad. In some instances, the gate of the gate pull transistor may be coupled to a first power supply rail. In some instances, the gate of the gate pull transistor may be coupled to a second power supply rail.

[0096] In some examples, the gate pull transistor is an NMOS transistor. In some examples, the gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the I / O pad or the rail of the first power supply during an electrostatic discharge event. In some examples, the driver transistor is a PMOS transistor. In some examples, the driver transistor is an NMOS transistor.

[0097] It should be noted that the operational steps described in any exemplary aspect herein are described for illustrative purposes only. The described operations may be performed in numerous different orders besides the order shown. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, numerous different modifications may be made to the operational steps shown in the flowcharts. Those skilled in the art will also understand that any of a variety of different technologies and processes can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the description above may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0098] The various operations described above can be performed by any suitable means capable of performing the corresponding functions. Such means may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Typically, where the operations shown in the figures are present, those operations may have corresponding means plus functional components with similar numbering. In some aspects, an apparatus performing certain functions disclosed herein may include: means for driving I / O pads of an IC device; means for shunting ESD current received at the I / O pads to a rail of a first power supply during an ESD event; and means for pulling the gate of a driver transistor to the voltage level of the I / O pads or the rail of the first power supply during an ESD event. The means for driving the I / O pads may include a driver transistor coupled through its source to a rail of the first power supply in the I / C device. The means for pulling the gate of the driver transistor may include a gate-pull transistor coupled between the gate of the driver transistor and the I / O pads or the rail of the first power supply. In one example, the driver transistor is coupled to the rail of the first power supply through at least one other transistor. In some examples, the gate of the driver transistor is configured to receive an input signal provided by a pre-driver circuit operating in a voltage domain corresponding to a second power supply.

[0099] In some examples, the device includes means for clamping a rail of a first power supply. The means for clamping the rail of the first power supply can be implemented using clamping circuitry coupled between the rail of the first power supply and a ground reference rail of the first power supply. The means for clamping the rail of the first power supply is configured to provide a control signal to the gate of a gate-pull transistor.

[0100] In some examples, the device includes means for controlling the gate pull transistor when the gate pull transistor is a PMOS transistor configured to couple the gate of the driver transistor to a rail of a first power supply. The means for controlling the gate pull transistor may include a connector or resistor configured to couple the gate of the gate pull transistor to a rail of a second power supply.

[0101] In some examples, the device includes means for controlling the gate pull transistor when the gate pull transistor is a PMOS transistor configured to couple the gate of a driver transistor to an I / O pad. In some instances, the means for controlling the gate pull transistor includes a connector or resistor configured to couple the gate of the gate pull transistor to a rail of a first power supply. In some instances, the means for controlling the gate pull transistor includes a connector or resistor configured to couple the gate of the gate pull transistor to a rail of a second power supply.

[0102] In one example, the gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the I / O pads during an ESD event. In another example, the gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the rail of a first power supply during an ESD event.

[0103] In some examples, the device used to shunt the electrostatic discharge current includes an ESD protection diode.

[0104] In one example, a dummy transistor or another unassigned transistor within the driver layout of the IC device is used to implement the gate pull transistor. In some examples, the gate pull transistor is an NMOS transistor. In some examples, an NMOS transistor is used to implement the driver transistor. In some examples, a PMOS transistor is used to implement the driver transistor.

[0105] In one example, the ESD protection circuit includes: a driver transistor having a drain coupled to an I / O pad of an IC device and a source coupled to a rail of a first power supply in the IC device; an ESD diode that couples the I / O pad to the rail of the first power supply; and a gate pull transistor that couples the gate of the driver transistor to either the I / O pad or the rail of the first power supply.

[0106] In one example, the source of the driver transistor is coupled to the rail of a first power supply via at least one other transistor. In some instances, the gate of the driver transistor is configured to receive an input signal provided by a pre-driver circuit powered by a second power supply.

[0107] In some examples, the device has a clamping circuit coupled between the rail of the first power supply and the ground reference rail of the first power supply. The clamping circuit can provide a control signal to the gate of the gate-pull transistor.

[0108] In some examples, the gate pull transistor is a PMOS transistor configured to couple the gate of the driver transistor to the rail of a first power supply, and the gate pull transistor's gate is coupled to the rail of a second power supply.

[0109] In some examples, the gate pull transistor is a PMOS transistor configured to couple the gate of the driver transistor to the I / O pad. The gate of the gate pull transistor can be coupled to a first power supply rail. The gate of the gate pull transistor can be coupled to a second power supply rail.

[0110] In some examples, the gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the I / O pad or the rail of the first power supply during an ESD event.

[0111] In some examples, a dummy transistor within a driver layout in the integrated circuit device is used to implement the gate pull transistor. In other examples, an additional unassigned transistor within a driver layout in the integrated circuit device is used to implement the gate pull transistor.

[0112] In some examples, NMOS transistors are used to implement the gate pull transistor. In some examples, PMOS transistors are used to implement the driver transistor. In some examples, NMOS transistors are used to implement the driver transistor.

[0113] Some implementation examples are described in the following numbered clauses.

[0114] 1. An electrostatic discharge (ESD) protection circuit, comprising: a driver transistor having a drain coupled to an input / output pad of an integrated circuit device and a source coupled to a rail of a first power supply in the integrated circuit device; an ESD protection diode coupling the input / output pad to the rail of the first power supply; and a gate pull transistor coupling the gate of the driver transistor to either the input / output pad or the rail of the first power supply.

[0115] 2. The electrostatic discharge protection circuit according to Clause 1, wherein the source of the driver transistor is coupled to the rail of the first power supply via at least one other transistor.

[0116] 3. The electrostatic discharge protection circuit according to Clause 1 or Clause 2, wherein the gate of the driver transistor is configured to receive an input signal provided by a pre-driver circuit powered by a second power supply.

[0117] 4. The electrostatic discharge protection circuit according to any one of clauses 1 to 5 further includes: a clamping circuit, said clamping circuit being coupled between the rail of the first power supply and the ground reference rail of the first power supply;

[0118] 5. The electrostatic discharge protection circuit according to Clause 6, wherein the clamping circuit provides a control signal to the gate of the gate pull transistor.

[0119] 6. The electrostatic discharge protection circuit according to any one of clauses 1 to 5, wherein: the gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to the rail of the first power supply; and the gate of the gate pull transistor is coupled to the rail of the second power supply.

[0120] 7. The electrostatic discharge protection circuit according to any one of clauses 1 to 5, wherein: the gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to the input / output pad; and the gate of the gate pull transistor is coupled to the rail of the first power supply or the rail of the second power supply.

[0121] 8. The electrostatic discharge protection circuit according to any one of Clauses 1 to 6, wherein the gate pull transistor comprises an N-type metal-oxide-semiconductor transistor.

[0122] 9. An electrostatic discharge protection circuit according to any one of clauses 1 to 8, wherein the gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the input / output pad or the rail of the first power supply during an electrostatic discharge event.

[0123] 10. The electrostatic discharge protection circuit according to any one of clauses 1 to 9, wherein the gate pull transistor includes an unassigned transistor or dummy transistor within a driver layout in the integrated circuit device.

[0124] 11. The electrostatic discharge protection circuit according to any one of clauses 1 to 10, wherein the driver transistor comprises a P-type metal-oxide-semiconductor transistor.

[0125] 12. The electrostatic discharge protection circuit according to any one of clauses 1 to 10, wherein the driver transistor comprises an N-type metal-oxide-semiconductor transistor.

[0126] 13. An apparatus comprising: means for driving input / output pads of an integrated circuit device, wherein the means for driving the input / output pads includes a driver transistor, the driver transistor being coupled via its source to a rail of a first power supply in the integrated circuit device; means for shunting an electrostatic discharge current received at the input / output pads to the rail of the first power supply during an electrostatic discharge event; and means for pulling the gate of the driver transistor to a voltage level of the input / output pads or the rail of the first power supply during the electrostatic discharge event, wherein the means for pulling the gate of the driver transistor includes a gate-pulling transistor coupled between the gate of the driver transistor and the input / output pads or the rail of the first power supply.

[0127] 14. The device according to Clause 13, wherein the driver transistor is coupled to the rail of the first power supply via at least one other transistor.

[0128] 15. The apparatus according to claim 13 or claim 14, wherein the gate of the driver transistor is configured to receive an input signal provided by a pre-driver circuit operating in a voltage domain corresponding to a second power supply.

[0129] 16. The device according to any one of clauses 13 to 15 further includes means for clamping the rail of the first power supply, including clamping circuitry coupled between the rail of the first power supply and the ground reference rail of the first power supply.

[0130] 17. The apparatus according to Clause 16, wherein the means for clamping the rail of the first power supply is configured to provide a control signal to the gate of the gate-pulling transistor.

[0131] 18. The device according to any one of claims 13 to 16, further comprising: means for controlling the gate pull transistor, wherein the gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to the rail of the first power supply, and wherein the means for controlling the gate pull transistor includes a connector or resistor configured to couple the gate of the gate pull transistor to the rail of the second power supply.

[0132] 19. The device according to any one of claims 13 to 16, further comprising means for controlling the gate pull transistor, wherein the gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to the input / output pad, and wherein the means for controlling the gate pull transistor includes a connector or resistor configured to couple the gate of the gate pull transistor to the rail of the first power supply or the rail of the second power supply.

[0133] 20. The device according to any one of clauses 13 to 17, wherein the gate pull transistor comprises an N-type metal-oxide-semiconductor transistor.

[0134] 21. The device according to any one of clauses 13 to 20, wherein the gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the input / output pad or the rail of the first power supply during the electrostatic discharge event.

[0135] 22. The device as described in Clause 21, wherein the means for shunting electrostatic discharge current includes an electrostatic discharge protection diode.

[0136] 23. The device according to any one of clauses 13 to 22, wherein the gate pull transistor includes an unassigned transistor or dummy transistor within a driver layout in the integrated circuit device.

[0137] 24. The device according to any one of clauses 13 to 23, wherein the driver transistor comprises an N-type metal-oxide-semiconductor transistor.

[0138] 25. The device according to any one of clauses 13 to 23, wherein the driver transistor comprises a P-type metal-oxide-semiconductor transistor.

[0139] 26. A method for providing electrostatic discharge protection in an integrated circuit device, comprising: coupling the drain of a driver transistor to an input / output pad of the integrated circuit device; coupling the source of the driver transistor to a rail of a first power supply in the integrated circuit device; using an electrostatic discharge protection diode to couple the input / output pad and the rail of the first power supply; and using a gate pull transistor to couple the gate of the driver transistor to the input / output pad or the rail of the first power supply.

[0140] 27. The method according to Clause 26 further comprises: coupling the driver transistor to the rail of the first power supply via at least one other transistor.

[0141] 28. The method according to Clause 26 or Clause 27, wherein the gate of the driver transistor is configured to receive an input signal provided by a pre-driver circuit operating in a voltage domain corresponding to a second power supply.

[0142] 29. The clamping circuit is coupled between the rail of the first power supply and the ground reference rail of the first power supply, according to any one of clauses 26 to 28.

[0143] 30. The method of claim 29, wherein the clamping circuit is configured to provide a control signal to the gate of the gate-pull transistor.

[0144] 31. The method according to any one of claims 26 to 29, wherein the gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to the rail of the first power supply, further comprising: coupling the gate of the gate pull transistor to the rail of the second power supply.

[0145] 32. The method according to any one of claims 26 to 29, wherein the gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to the input / output pad, further comprising: coupling the gate of the gate pull transistor to the rail of the first power supply or the rail of the second power supply.

[0146] 33. The method according to any one of clauses 26 to 30, wherein the gate pull transistor comprises an N-type metal-oxide-semiconductor transistor.

[0147] 34. The method according to any one of clauses 26 to 33, further comprising: configuring the gate pull transistor to provide a low-impedance path between the gate of the driver transistor and the input / output pad or the rail of the first power supply during an electrostatic discharge event.

[0148] 35. The method according to any one of clauses 26 to 34, wherein the driver transistor comprises a P-type metal-oxide-semiconductor transistor.

[0149] 36. The method according to any one of clauses 26 to 35, wherein the driver transistor comprises an N-type metal-oxide-semiconductor transistor.

[0150] 37. Electrostatic discharge protection circuit according to any one of Clauses 1 to 12, and according to Clause 13

[0151] The device according to any one of claims 25 or the method according to any one of claims 26 to 36, wherein the drain of the gate pull transistor is coupled to the gate of the driver transistor, and the source of the gate pull transistor is coupled to the input / output pad or the rail of the first power supply.

[0152] 38. Electrostatic discharge protection circuit according to any one of Clauses 1 to 12 or according to Clause 26

[0153] The method of any one of 36, wherein the electrostatic discharge protection diode is configured to be forward biased during an electrostatic discharge event and reverse biased prior to the occurrence of an electrostatic discharge event.

[0154] As used herein, the phrase “at least one of” in a list of entries refers to any combination of those entries (including a single member). For example, “at least one of a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0155] This disclosure is provided so that any person skilled in the art can make or use any aspect of it. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electrostatic discharge protection circuit in an integrated circuit device, the electrostatic discharge protection circuit comprising: A driver transistor having a drain coupled to an input / output pad of the integrated circuit device and a source coupled to a rail of a first power supply in the integrated circuit device via at least one other transistor, the driver transistor being configured to drive the input / output pad of the integrated circuit device; An electrostatic discharge (ESD) protection diode is provided that couples the input / output pads to the rails of the first power supply, and the ESD protection diode is configured to shunt an ESD current received at the input / output pads to the rails of the first power supply during an ESD event. A gate pull transistor that couples the gate of the driver transistor to the input / output pad, the gate pull transistor being configured to pull the gate of the driver transistor to the voltage level of the input / output pad during the electrostatic discharge event; as well as A clamping circuit, coupled between the rail of the first power supply and the ground reference rail of the first power supply, is configured to clamp the rail of the first power supply and provide a control signal to the gate of the gate pull transistor.

2. The electrostatic discharge protection circuit according to claim 1, wherein, The gate of the driver transistor is configured to receive an input signal provided by a pre-driver circuit powered by a second power supply.

3. The electrostatic discharge protection circuit according to claim 1, wherein: The gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to the input / output pad; and The gate of the gate pull transistor is coupled to the rail of the first power supply or the rail of the second power supply.

4. The electrostatic discharge protection circuit according to claim 1, wherein, The gate pull transistor includes an N-type metal-oxide-semiconductor transistor.

5. The electrostatic discharge protection circuit of claim 1, wherein the gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the input / output pad during the electrostatic discharge event.

6. The electrostatic discharge protection circuit according to claim 1, wherein, The gate pull transistor includes an unassigned transistor or dummy transistor within the driver layout of the integrated circuit device.

7. The electrostatic discharge protection circuit according to claim 1, wherein, The driver transistor includes a P-type metal-oxide-semiconductor transistor.

8. The electrostatic discharge protection circuit according to claim 1, wherein, The driver transistor includes an N-type metal-oxide-semiconductor transistor.

9. An apparatus for providing electrostatic discharge protection in an integrated circuit device, comprising: A means for driving the input / output pads of the integrated circuit device, wherein the means for driving the input / output pads includes a driver transistor, the driver transistor being coupled from its source to a rail of a first power supply in the integrated circuit device through at least one other transistor; A means for shunting electrostatic discharge current received at the input / output pads to the rail of the first power supply during an electrostatic discharge event; A means for pulling the gate of the driver transistor to the voltage level of the input / output pad during the electrostatic discharge event, wherein the means for pulling the gate of the driver transistor includes a gate pulling transistor coupled between the gate of the driver transistor and the input / output pad; as well as The means for clamping the rail of the first power supply includes a clamping circuit coupled between the rail of the first power supply and a ground reference rail of the first power supply. The means for clamping the rail of the first power supply is configured to provide a control signal to the gate of the gate-pulling transistor.

10. The device of claim 9, wherein the gate of the driver transistor is configured to receive an input signal provided by a pre-driver circuit operating in a voltage domain corresponding to a second power supply.

11. The device according to claim 9, further comprising: A means for controlling the gate pull transistor, wherein the gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to the input / output pad, and wherein the means for controlling the gate pull transistor includes a connector or resistor configured to couple the gate of the gate pull transistor to a rail of a first power supply or a rail of a second power supply.

12. The device of claim 9, wherein the gate pull transistor comprises an N-type metal-oxide-semiconductor transistor.

13. The device of claim 9, wherein the gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the input / output pad during the electrostatic discharge event.

14. The device of claim 13, wherein the means for shunting the electrostatic discharge current includes an electrostatic discharge protection diode.

15. The device of claim 9, wherein the gate pull transistor comprises an unassigned transistor or dummy transistor within a driver layout in the integrated circuit device.

16. The device of claim 9, wherein the driver transistor comprises an N-type metal-oxide-semiconductor transistor.

17. The device of claim 9, wherein the driver transistor comprises a P-type metal-oxide-semiconductor transistor.

18. A method for providing electrostatic discharge protection in an integrated circuit device, comprising: The drain of the driver transistor is coupled to the input / output pads of the integrated circuit device to drive the input / output pads of the integrated circuit device; The source of the driver transistor is coupled to the rail of a first power supply in the integrated circuit device via at least one other transistor. Electrostatic discharge protection diodes are used to couple the input / output pads and the rails of the first power supply to shunt the electrostatic discharge current received at the input / output pads to the rails of the first power supply during an electrostatic discharge event. A gate pull transistor is used to couple the gate of the driver transistor to the input / output pad to pull the gate of the driver transistor to the voltage level of the input / output pad during the electrostatic discharge event; as well as A clamping circuit is coupled between the rail of the first power supply and the ground reference rail of the first power supply to clamp the rail of the first power supply. The clamping circuit is configured to provide a control signal to the gate of the gate-pull transistor.

19. The method of claim 18, wherein the gate of the driver transistor is configured to receive an input signal provided by a pre-driver circuit operating in a voltage domain corresponding to a second power supply.

20. The method of claim 18, wherein the gate pull transistor is a P-type metal-oxide-semiconductor transistor configured to couple the gate of the driver transistor to the input / output pad, the method further comprising: The gate of the gate pull transistor is coupled to the rail of the first power supply or the rail of the second power supply.

21. The method of claim 18, wherein the gate pull transistor comprises an N-type metal-oxide-semiconductor transistor.

22. The method of claim 18, further comprising: The gate pull transistor is configured to provide a low-impedance path between the gate of the driver transistor and the input / output pads during the electrostatic discharge event.

23. The method of claim 18, wherein the driver transistor comprises a P-type metal-oxide-semiconductor transistor.

24. The method of claim 18, wherein the driver transistor comprises an N-type metal-oxide-semiconductor transistor.

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