Method and apparatus for timing recovery decoupled ffe adaptation in a serial receiver

Abstract

An apparatus and method for a receiver configured to perform timing recovery decoupling feedforward equalizer (FFE) adaptation. The receiver apparatus may include an analog front-end (AFE) device coupled to a time-interleaving (TI) interface. The TI interface is coupled in a timing recovery feedback loop to an FFE equalizer, a digital signal processor (DSP), a delay-timing loop (DTL) device, and a clock device, with the clock device feeding back to the TI interface. The DSP has an additional path to the FFE equalizer, which in turn has an additional path to the DTL device. The DTL loop is equipped with an interleaving-specific enable / disable vector Q[1:N] that can enable / disable the contribution of specific time-interleaving errors to the timing recovery loop, allowing the FFE adaptation process to be decoupled from the timing recovery loop.

Description

[0001] Cross-references to related applications

[0002] This application is a PCT international application of U.S. Patent Application No. 17 / 334,281, filed May 28, 2021. The entire disclosure of the above application is incorporated herein by reference. For all purposes, this application also incorporates, by reference, all of the following commonly owned patent applications: U.S. Patent Application No. 14 / 806,346 (now U.S. Patent No. 9,467,315), filed July 22, 2015, entitled “CIRCUIT AND METHOD FOR PERFORMING ADAPTATION ON ALL RECIEVER BRANCHES”; and U.S. Patent Application No. 15 / 260,692 (now U.S. Patent No. 9,660,841), a continuation of the above application, filed September 9, 2016. Background Technology

[0003] This invention generally relates to communication systems and integrated circuit (IC) devices. More specifically, this invention provides a method and apparatus for timing recovery of decoupled feedforward equalizer (FFE) adaptation in a serializer / deserializer (SerDes) receiver device.

[0004] The use of communication networks has exploded over the past few decades. In the early days of the Internet, popular applications were limited to email, bulletin boards, and most information-based, text-based web browsing. The amount of data transmitted by these applications was relatively small. Today, the Internet and mobile applications require massive amounts of bandwidth to transmit photos, videos, music, and other multimedia files. For example, social networking platforms can process more than 500TB of data per day. Due to this high demand for data storage and transmission, existing data communication systems need to be improved to meet these needs.

[0005] With the rapidly growing demand for higher operating speeds and data throughput, a crucial aspect of signal processing that needs to be addressed is signal equalization at the receiver—the process of eliminating distortion caused by signals transmitted through the channel. This impairment of signal integrity can be mitigated by using signal equalization techniques such as feedforward equalization (FFE), decision feedback equalization (DFE), continuous-time linear equalization (CTLE), and combinations thereof.

[0006] Many traditional methods and devices already exist for signal equalization. Unfortunately, these traditional methods and devices have various drawbacks and limitations, including those related to performance, size, and cost. Therefore, there is a high demand for improved communication systems that utilize more efficient signal equalization devices and methods. Summary of the Invention

[0007] This invention generally relates to communication systems and integrated circuit (IC) devices. More specifically, it provides a method and apparatus for adapting a feedforward equalizer (FFE) for timing recovery decoupling in a serializer / deserializer (SerDes) receiver device. By way of example only, this invention is applied to communication systems using pulse amplitude modulation (PAM). However, this invention has a wider range of applications, such as other Ethernet systems, optical systems, etc.

[0008] According to one example, the present invention provides a communication system and a receiver device configured to perform an FFE adaptation process decoupled from the timing recovery loop of the device. The receiver device may include an analog front-end (AFE) device coupled to a time-interleaving (TI) interface. The TI interface is coupled in a timing recovery feedback loop to an FFE equalizer, a digital signal processor (DSP), a delay-timing loop (DTL) device, and a clock device. The clock device feeds back to the TI interface to complete the timing recovery loop. The DSP has an additional path to the FFE equalizer, and the FFE equalizer has an additional path to the DTL device. In a particular example, the DTL loop is equipped with an interleaving-specific enable / disable vector Q[1:N] that can enable / disable the contribution of a specific time-interleaving error to the timing recovery loop. Using this interleaving vector, the receiver device can decouple the FFE adaptation process from the timing recovery loop.

[0009] According to one example, the present invention provides a method for operating a communication system and a receiver device configured to perform a timing recovery decoupling (FFE) adaptation process. The method may include: receiving and processing an input signal by an AFE device; then, a TI interface samples the input signal according to multiple indices associated with its multiple channels. In preparation for the iterative adaptation process, the method may include: determining one or more phase conditions for multiple FFEs coupled to the TI interface in a timing recovery loop configuration. The iterative adaptation process may include: performing an iterative FFE adaptation process on the input signal via each TI interface channel, and simultaneously performing an FFE adaptation process on a target channel, using an interleaving-specific vector to disable the target channel's contribution to the timing recovery loop configuration. Other variations, modifications, and alternatives will be recognized by those skilled in the art.

[0010] Numerous benefits have been recognized through various embodiments of the present invention. These benefits include improved bit error rate and the ability to optimize phase in FFE during task mode. According to embodiments, the techniques implemented in the present invention are also cost-effective and relatively simple to implement. Other such benefits will be recognized by those skilled in the art.

[0011] These and other benefits are achieved within the context of known IC manufacturing processes. However, a further understanding of the nature and advantages of the invention can be achieved by referring to the latter part of the specification and the accompanying drawings. Attached Figure Description

[0012] The illustrations below are merely examples and should not be construed as limiting the scope of the claims herein. Those skilled in the art will recognize many other variations, modifications, and alternatives. It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or alterations thereto will be suggested to those skilled in the art and will be included within the spirit and scope of the process and the appended claims.

[0013] Figure 1 This is a simplified block diagram illustrating a receiver device based on a conventional example.

[0014] Figure 2 This is a simplified circuit block diagram illustrating a receiver device according to an example of the present invention.

[0015] Figure 3 This is a simplified block diagram illustrating a feedforward equalizer (FFE) configuration in a receiver device according to an example of the present invention. Detailed Implementation

[0016] This invention generally relates to communication systems and integrated circuit (IC) devices. More specifically, it provides a method and apparatus for adapting a feedforward equalizer (FFE) for timing recovery decoupling in a serializer / deserializer (SerDes) receiver device. By way of example only, this invention is applied to communication systems using pulse amplitude modulation (PAM). However, this invention has a wider range of applications, such as other Ethernet systems, optical systems, etc.

[0017] The following description is presented to enable those skilled in the art to make and use the invention and to incorporate it into the context of a particular application. Various modifications and uses in different applications will be apparent to those skilled in the art, and the general principles defined herein can be applied to a wide range of embodiments. Therefore, the invention is not intended to be limited to the presented embodiments, but is accorded the broadest scope consistent with the principles and novel features disclosed herein.

[0018] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the invention.

[0019] The reader's attention is directed to all papers and documents submitted concurrently with this specification and made publicly available for examination, the contents of which are incorporated herein by reference. All features disclosed in this specification (including any appended claims, abstracts, and drawings) may be replaced by alternative features for the same, equivalent, or similar purposes, unless expressly stated otherwise. Therefore, unless expressly stated otherwise, each disclosed feature is merely an example of an equivalent or similar feature in a general series.

[0020] Furthermore, any element not expressly designated in the claims as a “component” for performing the specified function or a “step” for performing a particular function shall not be construed as a “component” or “step” as specified in paragraph 6 of Section 112 of 35 U.S.SC. In particular, the use of “step” or “action” in the claims herein is not intended to invoke the provisions of paragraph 6 of 35 U.S.SC.

[0021] Note that, if used, the markings left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are for convenience only and are not intended to suggest any particular fixed direction. Rather, they are used to reflect the relative position and / or orientation between the various parts of an object.

[0022] Figure 1 This is a simplified block diagram illustrating a communication system 100 according to a conventional example. System 100 includes a transmitter device 110 coupled to a receiver device 120 (marked by dashed lines) via channel 111. As shown, receiver device 120 first receives a signal from transmitter device 110 via channel 111 at analog front-end (AFE) device 130, which is coupled to a serial-to-parallel (S / P) time-interleaved (TI) interface 140. TI interface 140 is coupled in a timing recovery feedback loop to an FFE equalizer 150, a digital signal processor (DSP) 160, a delay-timing loop (DTL) device 170, and a clock device 180. Clock device 180 feeds back to TI interface 140 to complete the timing recovery loop.

[0023] In this example, the FFE adaptation process interacts with the timing recovery loop (i.e., the DTL loop). If the DTL loop shifts phase in a given direction, the FFE will adapt to the new phase without constraints on the FFE coefficients, causing the system to move to the edge of the eye and fail. The following examples of the invention provide a method and apparatus for adapting the FFE of a time-interleaved SerDes receiver in mission mode while eliminating interaction with the timing recovery loop.

[0024] Figure 2This is a simplified circuit block diagram illustrating a receiver device 200 according to an example of the present invention. Device 200 may be... Figure 1 The example circuit configuration of receiver device 101 is shown. As illustrated, device 200 includes an AFE 210 coupled to an interleaving interface 220, which is coupled to a time interleaving (TI) array 230. The TI array 230 includes multiple slices, and the interleaving interface 220 includes corresponding multiple interleaving branches. As an example, device 220 is shown with 16 slices in the TI array 230, and the interleaving interface 220 is configured in corresponding 16 interleavings. However, other arrays and corresponding interleaving interface sizes may be used depending on the application. Further details are provided below.

[0025] In one example, AFE 210 includes a tunable termination block 211 to minimize reflections at the interface of the channel. The tunable termination block 211 may have a resistance ranging from 50 to 100 ohms. Other resistance ranges may be used depending on the application.

[0026] The next block after terminal block 211 can be an optional block labeled Continuous Time Linear Equalizer (CTLE) device 212, which can potentially be added or removed using metal options. This CTLE device 212 provides intermediate frequency (IF) and high frequency (HF) boosts to the signal to compensate for signal loss experienced during transmission through the channel. This boost function can be implemented using a 1-zero, 2-pole equalizer, or more complex equalizers such as 2-zero, 3-pole, or others. In a particular example, the boost amount ranges from approximately 0 dB to approximately 6 dB and can be adjusted by settings to change the frequency boost distribution, i.e., the zero-point position and peak amount. Other boost ranges may be used depending on the application.

[0027] A first variable gain amplifier (VGA) 213, denoted as "VGA1", can be coupled to either CTLE 212 or termination block 211 and can be configured to provide gain. In one example, the gain range can be from approximately 0 to approximately 6 dB, but other gain values ​​and ranges can be used depending on the application. In this case, the CTLE+VGA1 distribution can be optimized together, whereas in the absence of CTLE 212, the range requirement of only VGA1 213 after termination block 211 can be different.

[0028] Following AFE 210, the input signal is then sampled by TI array 230 via TI interface 220. As discussed earlier, TI array 230 has N=16 and interleaving interface 220 is configured as a 16-way interleaving system, which can send the input signal to each of the 16 slices. Each slice in TI array 230 can be configured with its own clock offset adjustment to optimize for variations in delay and bandwidth (BW) of each sampler in the sampler.

[0029] Each slice in the TI array 230 may also include an FFE 240 (e.g., a C-tap sampled FFE), a decision feedback equalizer (DFE) 250 (e.g., a D-tap DFE), and an analog-to-digital converter (labeled by region 260), which includes multiple decision devices 270 (represented as "data and error limiters"). Figure 2 As shown, each slice receives input signals from the interleaving interface 220 and is configured to perform FFE and DFE processes, etc.

[0030] In one example, the FFE 240 may be coupled to buffer 231 to drive long interconnects running to / from adjacent slices, as well as summing circuitry 242. FFE buffer 231 (with some gain adjustment capability, e.g., -2 to 2 dB) may also help mitigate gain variations between interleaved slices, a common problem in time-interleaved designs. This helps reduce the gain range required on subsequent amplifier stages and reduces tap range requirements due to the increased variability on the individual vertex of the N slices. Each slice may also include a probe limiter 232 that receives the input signal from interleaving interface 220. FFE 240 may include a switch 241 coupled to FFE summer 242 (i.e., summing circuitry), which is configured to equalize the effects of the prescaler and postscaler.

[0031] DFE 250 may include a second VGA 251 (referred to as "VGA2") coupled to FFE summer 241 and a DFE summer 252 configured to equalize the effects of the prescaler. Following DFE 250, array 230 may include an amplifier 260 (e.g., a source follower, etc.) coupled to decision device 270 (e.g., a data and error limiter). These limiters 270 may also be connected to other slices in array 230. Further, these limiters 270 are configured as described above for… Figure 1 The timed recovery loop discussed. Those skilled in the art will recognize other variations, modifications, and alternatives.

[0032] Interleaving configurations provide the necessary time delay (e.g., Ts = 1 / 56 GHz) for the implementation of sampling FFE and DFE equalizers. For example, suppose increasing the number of slices means further sampling in time. From the perspective of slice 2 ((x+2)*Ts), the output of slice 1 ((x+1)*Ts) will be the first suffix, and the output of slice 3 will be the first prescript. Further, the output of slice 4 will be the second prescript, and so on.

[0033] As an example configuration of device 200, the number of taps for the FFE can be C=10, including 3 prescripts and 6 postscripts. The number of taps can be limited during system optimization by combining CTLE and DFE to balance the mid-range (MR) and long-range (LR) channels with losses up to 3-+dB at the Nyquist frequency. One or more prescripts in the FFE are also delayed via a switching path (e.g., sample and hold circuitry) to allow for additional settling time.

[0034] Based on the example of PAM-4 signal detection, three data limiters (-2, 0, +2) and four error limiters (+ / -3, + / -1) are used in... Figure 2 Limiting is performed at the threshold shown. While one error limiter is sufficient in some implementations, four error limiters in this example allow for high-bandwidth baud rate timing recovery. This configuration also accelerates the adaptation of the FFE, DFE, gain, and offset loops. In non-return-to-zero mode, only two error limiters are used, and all data limiters are set to the same threshold to limit the center of the eye. Additionally, four error limiters can enable an optional data path for optical enhancement. Another limiter can be used as a calibration limiter, which is used to find the true amplitude of the eye, and in mission mode, one data limiter is toggled each time (+2, 0, or -2) to enable background calibration of the bias. Other variations, modifications, and alternatives for other signal types will be recognized by those skilled in the art.

[0035] During link startup and the acquisition phase, the signals sampled by TI are derived from the derived clocks fed to each track and hold. (Reference) Figure 1 The clock device 180 drives the TI interface 140, which has multiple interleaved channels (i.e., interleaved) to sample the input signal from the AFE 130. Each of the multiple interleaved channels includes a track-and-hold switch, such as... Figure 2The TI interface 220 is shown. This process determines the sampling time for each interleaving path. The task of the FFE is to equalize the signal at that phase and remove intersymbol interference. As discussed earlier, these systems face the problem of interaction between the timing recovery loop and the FFE. If the DTL loop shifts phase in a given direction, without constraints on the FFE coefficients, the FFE will adapt to the new phase, causing the system to move to the edge of the eye and fail.

[0036] Therefore, a common solution is to freeze the adaptation of the first preamble or first postamble in the FFE. This fixes the phase and prevents DTL deviation. When the chip temperature changes, the frequency / phase response of the AFE changes, causing a change in the sampling phase and equalization of the FFE. However, if the phase of the FFE is fixed because the first preamble or first postamble is fixed, the sampling phase becomes suboptimal, resulting in a worse bit error rate.

[0037] According to one example, the present invention provides a method and apparatus for decoupling the adaptation of FFE from the DTL loop (i.e., the timing recovery loop) using an interleaving-specific vector configured in a DTL device, thereby enabling phase optimization in task mode. Figure 3 This is a simplified block diagram illustrating a feedforward equalizer (FFE) configuration in a receiver device according to an example of the present invention. As shown, device 300 includes a TI interface 340, an FFE equalizer 350, a DSP 360, a DTL device 370, and a clock device 380. Figure 1 Compared to receiver device 101, DSP 360 has an additional path to FFE equalizer 350, which in turn has an additional path to DTL device 370.

[0038] refer to Figure 2 The data and error limiter 270 generates a limited data vector and an error vector from the input signals processed by the FFE 240 and DFE 250. A timing recovery loop configured for each array slice uses the limited data vector and error vector to calculate the timing information required for manipulating clock recovery. The error vector includes errors generated from N consecutive interleaved values ​​from the TI interface 220. Of course, the limiter configuration can be varied, modified, and alternatives can be made.

[0039] In one example, the DTL loop (i.e., the timing recovery loop) is equipped in the DTL device 370 with an interleaving-specific enable / disable vector Q[1:N]. The ability to enable or disable the contribution of a specific interleaving enables the FFE to adapt to decoupling from timing recovery, thus avoiding catastrophic events where the FFE and CDR drive each other in the loop and lose lock. This vector enables / disables the contribution of a specific timing interleaving error to the timing recovery loop. Figure 3The additional path from DSP 360 through FFE equalizer 350 to DTL 370 shown illustrates this functionality. Under the control of DSP 360, FFE equalizer 350 can enable and disable interleaving-specific vectors in DTL device 370 during the FFE adaptation process, as further described below.

[0040] In a specific example, each of the N FFEs is equipped with a Least Mean Square (LMS) engine for adaptation. Each FFE has C engines to adapt to each tap. Therefore, there are N×C distinct taps to adapt to. The step size of the LMS, denoted by "mu", determines the speed of adaptation. Each FFE engine has a vector MU[1:C] containing C distinct mu. The mu values ​​at interleaving I and tap J are denoted as MU[I][J]. A value of 0 for MU[I][J] means that adaptation is disabled at FFE index I and tap J.

[0041] The method for operating a SerDes receiver device using an orthogonalization adaptation algorithm according to an example of the present invention is briefly described below:

[0042] 1. Receive input signals;

[0043] 2. The input signal is sampled using a time-interleaving (TI) interface with multiple channels, based on multiple indices associated with the multiple channels;

[0044] 3. Determine one or more phase conditions for multiple feedforward equalizers (FFEs), each FFE having multiple taps; and

[0045] 4. An iterative orthogonal adaptation process is performed on the input signal via multiple FFEs, through each of the multiple channels of the TI interface serving as the target channel, wherein the iterative orthogonal adaptation process includes: using an interleaving-specific vector to decouple the contribution of the target channel from the timing recovery loop, while performing an FFE adaptation process on the input signal through the target channel.

[0046] The sequence of the above steps is used to operate a multi-instance TI system to align the divider phases of multiple TI devices (i.e., TI system instances) according to embodiments of the present invention. Depending on the embodiments, one or more of these steps may be combined or removed, or other steps may be added, without departing from the scope of the claims herein. Other variations, modifications, and alternatives will be recognized by those skilled in the art. Further details of these steps are discussed below.

[0047] Referring to step (1), the receiver can receive the input signal from the transmitter via a communication channel. This input signal can be received at the analog front end (AFE), such as... Figure 1 and Figure 2As shown above. Figure 2 The AFE discussed may include a tunable termination block, a continuous-time linear equalizer (CTLE), and a variable-gain amplifier (VGA).

[0048] Referring to step (2), the input signal received at the AFE is sampled through the TI interface, such as... Figure 1 and Figure 2 As shown above, the TI interface can be referenced based on multiple indices associated with each channel / interleaving of the TI interface. Figure 1 and Figure 2 As discussed, each TI interface channel may include a track-and-hold switch driven by a clock source. Each channel may be coupled to a slice of the TI array, where each slice includes one of the FFE equalizers. Furthermore, each slice of the TI array may be configured with its own clock offset adjustment.

[0049] Referring to step (3), determine that the phase conditions for the FFE can be performed via a finite state machine (FSM) configured in the firmware / DSP. This step may include performing a phase scan for each FFE using predetermined scan conditions. A variety of scan conditions can be used for the phase scan of the FFE. In one example, the phase scan conditions may include fixing the first prefix, fixing the first suffix, fixing both the first prefix and the first suffix, or fixing the difference between the first prefix and the first suffix. This can be done by disabling adaptation (or both or the difference) at a particular tap while simultaneously scanning its value.

[0050] In one example, the phase of the scanned FFE is used to determine the desired location / sampling point in the receiver eye, which characterizes the input signal. The desired location in the receiver eye can be determined by evaluating the signal-to-noise ratio (SNR) and jitter tolerance (e.g., jitter resistance with optimal SNR). The phase of the FFE can then be fixed based on this desired location.

[0051] Determining the phase conditions for FFE may also include performing an FFE adaptation process on an input signal with a constant phase. This process may include activating the data channel (i.e., the receiver channel) using various constant phases. In one example, the constant phase may include a constant first preamble, a constant second preamble, or a constant difference between the first and second preambles. This tap index may be denoted by "P" (used below to set the adaptation constant).

[0052] Referring to step (4), if the change in device temperature (T) exceeds a predetermined threshold (e.g., |T) 当前 -T 先前If |>Δ), then the orthogonal adaptation method can be triggered. In one example, the current device temperature and the previous device temperature are registered values, and after a temperature change threshold is reached, the previous temperature can be set to the current temperature in preparation for evaluation of subsequent device temperature changes. Alternatively, the orthogonal adaptation method can be triggered based on other conditions or on a periodic basis.

[0053] As briefly outlined above, the iterative orthogonal adaptation process may include an iterative process configured to iterate through each interleaving index in the interleaving indexes (i.e., for index = 1:N). The iterative orthogonal adaptation process may include: (1) disabling the contribution of the target channel / interleaving of the TI interface to the timing recovery loop using an interleaving-specific vector at the relevant index, (2) performing an FFE adaptation process without any constraints on all taps of the FFE coupled to the target channel, and (3) enabling the contribution of the target channel / interleaving of the TI interface to the timing recovery loop using an interleaving-specific vector at the relevant index.

[0054] When the FFE adaptation process is already in progress, the FFE adaptation on the target interleaving must first be stopped before using the interleaving-specific vector. In some cases, the gain of the DTL loop will need to be changed after the FFE adaptation process decouples from the timing recovery loop. In a specific example, the iterative adaptation process includes fixing the phase of the FFE associated with the target interleaving after the FFE adaptation process and before re-enabling the contribution of the target interleaving. Further, the iterative process may include waiting for a predetermined stabilization period between these previously described steps to allow changes to propagate through the receiver device (e.g., after FFE adaptation starts / stops, interleaving index is disabled / enabled, DTL gain is changed, phase is fixed, etc.). Other variations, modifications, and alternatives to this iterative adaptation process will be recognized by those skilled in the art.

[0055] In one example, an interleaving-specific enable / disable vector (denoted as Q[i]) can be enabled for all index entries of the interleaving (e.g., setting Q[1:N] = 1) to prepare for the iterative adaptation process. In one example, the orthogonal adaptation method may include interleaving for each index (e.g., indexes I from 1 to N). 交织 The iterative process adapts to all taps. For each index, interleaving a specific vector is disabled at the target index (e.g., setting Q[I]). 交织 ] = 0); This brings the interleaving contribution at the target index out of the DTL loop. Then, adaptation of all taps for the target index can be enabled (e.g., enabling FFE[I 交织 In a specific example, this action can be achieved by changing the adaptation constant (mu) for that tap to be far from zero (e.g., MU[I]). 交织[P] ~=0). Before the adaptation engine is stopped, it can be enabled for the target index during a predetermined adaptation period. This can include changing the adaptation constant (mu) for the tap to return zero (e.g., setting MU[I...). 交织 [P] = 0).

[0056] Subsequently, interleaving specific enable / disable vectors can be enabled again for the target index (i.e., setting Q[I]). 交织 The method can then incorporate the interleaving contribution at the target index back into the DTL loop. The iterative process can then include waiting for a predetermined stabilization period to allow the DTL loop to stabilize. After the iterative process, the method can include enabling interleaving-specific enable / disable vectors for all interleaved index entries (e.g., setting Q[1:N] = 1) to prepare for normal operation. Of course, other variations, modifications, and alternatives are possible for the iterative adaptation process.

[0057] While the foregoing is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. Therefore, the foregoing description and illustrations should not be construed as limiting the scope of the invention as defined by the appended claims.

Claims

1. A receiver circuit, comprising: Multiple feedforward equalizers are configured to recover data from a received signal. Each of the multiple feedforward equalizers is configured to perform feedforward adaptation, which includes adjusting at least one of a pre-index tap and a post-index tap in phase to determine a phase position where a characteristic eye of the received signal is to be sampled, and to provide a metric for the phase position indicating the signal quality when sampled at the phase position. A processor configured to selectively enable feedforward adaptation of one or more of the plurality of feedforward equalizers; as well as A timing recovery circuit is configured to: selectively block the use of contributions from the plurality of feedforward equalizers with feedforward adaptation enabled, selectively allow the use of contributions from the plurality of feedforward equalizers with feedforward adaptation disabled, and perform timing recovery, the timing recovery including adjusting the phase of a clock based on contributions received from the plurality of feedforward equalizers with feedforward adaptation disabled, the received contributions including the metrics from the plurality of feedforward equalizers with feedforward adaptation disabled and the recovered data.

2. The receiver circuit of claim 1, wherein the timing recovery circuit is configured to: store an interleaved specific vector comprising a plurality of indices indicating whether contributions from a corresponding feedforward equalizer among the plurality of feedforward equalizers are used, and, based on the plurality of indices, use contributions from the plurality of feedforward equalizers with feedforward adaptation disabled.

3. The receiver circuit of claim 1, wherein the plurality of feedforward equalizers are configured to provide a plurality of interleaved sampled slices of the received signal accordingly, and are further configured to perform an iterative adaptation process on the plurality of interleaved sampled slices of the received signal to provide the recovered data.

4. The receiver circuit according to claim 3, wherein the iterative adaptation process includes: The plurality of interleaved sampling slices are iteratively traversed, and during each stage of traversing the plurality of interleaved sampling slices, feedforward adaptation is enabled for the corresponding interleaved sampling slice among the plurality of interleaved sampling slices, and feedforward adaptation is disabled for the other interleaved sampling slices among the plurality of interleaved sampling slices.

5. The receiver circuit according to claim 1, wherein: The processor is configured to: enable feedforward adaptation of one of the plurality of feedforward equalizers, while disabling feedforward adaptation of the other feedforward equalizers in the plurality of feedforward equalizers; and The timing recovery circuit is configured to allow the use of contributions from one of the plurality of feedforward equalizers that has feedforward adaptation disabled, and to prevent the use of contributions from the other feedforward equalizers among the plurality of feedforward equalizers.

6. The receiver circuit according to claim 1, wherein: The processor is configured to iteratively cycle through the plurality of feedforward equalizers, wherein each iteration includes: one of the feedforward equalizers performing feedforward adaptation and not contributing to the timing recovery; and The timing recovery circuit is configured to prevent the use of contributions from one of the plurality of feedforward equalizers performing feedforward adaptation during each iteration of the iteration.

7. The receiver circuit according to claim 6, wherein: The processor is configured to: during each iteration of the iteration, disable feedforward adaptation of the plurality of feedforward equalizers, except for the one feedforward equalizer among the plurality of feedforward equalizers that performs feedforward adaptation; and The timing recovery circuit is configured to allow the use of contributions from other feedforward equalizers that have feedforward adaptation disabled during each iteration of the iteration.

8. The receiver circuit of claim 1, wherein each of the plurality of feedforward equalizers is configured to: when enabled, perform feedforward adaptation based on the signal-to-noise ratio of a corresponding sample of the received signal.

9. The receiver circuit of claim 1, wherein each of the plurality of feedforward equalizers is configured to: during feedforward adaptation, scan the phase of at least one of the pre-label taps and the post-label taps on a plurality of phases to measure a metric at each of the plurality of phases, and sample the characteristic eye of the received signal at the phase of one of the plurality of phases that provides a better metric compared to the other phases of the plurality of phases.

10. The receiver circuit according to claim 1, further comprising: An analog front-end device, the analog front-end device being configured to receive and amplify an input signal to provide the received signal; as well as An interleaving interface configured to direct the received signal to each of the plurality of feedforward equalizers based on the phase of the clock.

11. The receiver circuit of claim 10, wherein the analog front-end device includes a continuous-time linear equalizer configured to boost a predetermined frequency range of the input signal based on a frequency boost distribution.

12. A method of operating a receiver device, the method comprising: Signals are received at multiple feedforward equalizers, and data is recovered using the multiple feedforward equalizers; Selectively enable feedforward adaptation of one or more of the plurality of feedforward equalizers; At one or more of the plurality of feedforward equalizers, feedforward adaptation is performed, the feedforward adaptation comprising: adjusting at least one of a pre-index tap and a post-index tap in phase to determine a phase position at which a characteristic eye of the received signal is to be sampled, and providing a metric for the phase position indicating the signal quality when sampled at the phase position; Selectively prevent the use of contributions from the multiple feedforward equalizers with feedforward adaptation enabled; Selectively allow the use of contributions from the plurality of feedforward equalizers with feedforward adaptation disabled; and Perform timing recovery, which includes adjusting the phase of the clock based on contributions received from the plurality of feedforward equalizers with feedforward adaptation disabled, the received contributions including the metrics from the plurality of feedforward equalizers with feedforward adaptation disabled and the recovered data.

13. The method of claim 12, further comprising: The storage includes an interleaved specific vector comprising multiple indices, which indicate whether contributions from the respective feedforward equalizers among the multiple feedforward equalizers are used. as well as Based on the multiple indexes, contributions from the multiple feedforward equalizers with feedforward adaptation disabled are used for timing recovery.

14. The method of claim 12, wherein an iterative adaptation process is performed on the received signal at the plurality of feedforward equalizers to provide the recovered data, wherein a plurality of interleaved sampled slices of the received signal are sampled by the plurality of feedforward equalizers respectively.

15. The method of claim 12, further comprising: Enable feedforward adaptation of one of the plurality of feedforward equalizers, while disabling feedforward adaptation of the other feedforward equalizers in the plurality of feedforward equalizers. as well as Contributions from one of the plurality of feedforward equalizers with feedforward adaptation disabled are allowed, while contributions from the other feedforward equalizers are prevented.

16. The method of claim 12, further comprising: The process iteratively loops through the plurality of feedforward equalizers, wherein each iteration includes: performing feedforward adaptation at one of the feedforward equalizers, and not providing any contribution from that one feedforward equalizer to the timing recovery; and During each iteration of the iteration, the contribution from one of the feedforward equalizers performing feedforward adaptation is prevented.

17. The method of claim 16, wherein the iterative loop through the plurality of feedforward equalizers comprises: Perform multiple iterations, wherein each iteration includes: allowing the corresponding feedforward equalizer among the plurality of feedforward equalizers to perform feedforward adaptation for the loop, and disabling the other feedforward equalizers among the plurality of feedforward equalizers.

18. The method of claim 16, wherein: During each iteration of the iteration, feedforward adaptation of the plurality of feedforward equalizers is disabled, except for the one feedforward equalizer among the plurality of feedforward equalizers that performs feedforward adaptation. and During each iteration of the iteration, contributions from other feedforward equalizers with feedforward adaptation disabled are allowed.

19. The method of claim 12, further comprising: At each of the plurality of feedforward equalizers, when enabled, feedforward adaptation is performed based on the signal-to-noise ratio of the corresponding sample of the received signal.

20. The method of claim 12, further comprising: At each of the plurality of feedforward equalizers with feedforward adaptation enabled, the phase of at least one of the pre-label taps and the post-label taps is scanned across a plurality of phases, a metric is measured at each of the plurality of phases, and the characteristic eye of the received signal is sampled at the phase of the plurality of phases that provides a better metric than the other phases of the plurality of phases.

21. The method of claim 12, further comprising: Receive and amplify the input signal to provide the received signal; as well as Based on the phase of the clock, the received signal is directed to each of the plurality of feedforward equalizers.

22. The method of claim 21, further comprising: Based on the frequency boost distribution, the predetermined frequency range of the input signal is increased.

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